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-rw-r--r--arch/arm/cpu/arm926ejs/mxs/clock.c2
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c85
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock.c8
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c16
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c62
-rw-r--r--arch/arm/cpu/armv7/omap3/Makefile1
-rw-r--r--arch/arm/cpu/armv7/omap3/am35x_musb.c75
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h11
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware.h4
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-exynos/dwmmc.h36
-rw-r--r--arch/arm/include/asm/arch-mxs/clock.h1
-rw-r--r--arch/arm/include/asm/arch-omap3/am35x_def.h27
-rw-r--r--arch/arm/include/asm/arch-omap3/musb.h28
-rw-r--r--arch/arm/include/asm/imx-common/mx5_video.h21
-rw-r--r--arch/arm/include/asm/omap_musb.h32
-rw-r--r--arch/arm/lib/board.c12
17 files changed, 417 insertions, 6 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index bfea6ab..4ff19c3 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -333,6 +333,8 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
return mx28_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK:
return mx28_get_sspclk(MXC_SSPCLK3);
+ case MXC_XTAL_CLK:
+ return XTAL_FREQ_KHZ * 1000;
}
return 0;
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index e4c123c..da5bc73 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -33,6 +33,11 @@
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -63,3 +68,83 @@ void setup_clocks_for_console(void)
/* Not yet implemented */
return;
}
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
+ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN (1 << 0)
+#define CM_PHY_OTG_PWRDN (1 << 1)
+#define OTGVDET_EN (1 << 19)
+#define OTGSESSENDEN (1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+ if (on) {
+ clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+ OTGVDET_EN | OTGSESSENDEN);
+ } else {
+ clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+ }
+}
+
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
+{
+ am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+ .set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+ .mode = CONFIG_AM335X_USB0_MODE,
+ .config = &musb_config,
+ .power = 50,
+ .platform_ops = &musb_dsps_ops,
+ .board_data = &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
+{
+ am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+ .set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+ .mode = CONFIG_AM335X_USB1_MODE,
+ .config = &musb_config,
+ .power = 50,
+ .platform_ops = &musb_dsps_ops,
+ .board_data = &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+ musb_register(&otg0_plat, &otg0_board_data,
+ (void *)AM335X_USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+ musb_register(&otg1_plat, &otg1_board_data,
+ (void *)AM335X_USB1_OTG_BASE);
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index bc2abb6..0b4cb4e 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -40,6 +40,7 @@
#define CLK_MODE_MASK 0xfffffff8
#define CLK_DIV_SEL 0xFFFFFFE0
#define CPGMAC0_IDLE 0x30000
+#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -194,6 +195,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
;
+
+ /* MUSB */
+ writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
+ while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
+ ;
}
static void mpu_pll_config(void)
@@ -290,6 +296,8 @@ static void per_pll_config(void)
while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
;
+
+ writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
}
void ddr_pll_config(unsigned int ddrpll_m)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..c6c6681 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -919,6 +919,20 @@ static int exynos5_set_spi_clk(enum periph_id periph_id,
clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
return 0;
+
+static unsigned long exynos4_get_i2c_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long sclk, aclk_100;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(APLL);
+
+ ratio = (readl(&clk->div_top)) >> 4;
+ ratio &= 0xf;
+ aclk_100 = sclk / (ratio + 1);
+ return aclk_100;
}
unsigned long get_pll_clk(int pllreg)
@@ -941,6 +955,8 @@ unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5()) {
return exynos5_get_i2c_clk();
+ } else if (cpu_is_exynos4()) {
+ return exynos4_get_i2c_clk();
} else {
debug("I2C clock is not set for this CPU\n");
return 0;
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index f02f441..b479965 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -385,6 +385,68 @@ static int exynos4_pinmux_config(int peripheral, int flags)
return 0;
}
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+ struct exynos4_gpio_part1 *gpio1 =
+ (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
+static int exynos4_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos4_i2c_config(peripheral, flags);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
index ac597be..de167ee 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -38,6 +38,7 @@ endif
COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o
COBJS-$(CONFIG_EMIF4) += emif4.o
COBJS-$(CONFIG_SDRC) += sdrc.o
+COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c
new file mode 100644
index 0000000..7183c4f
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap3/am35x_musb.c
@@ -0,0 +1,75 @@
+/*
+ * This file configures the internal USB PHY in AM35X.
+ *
+ * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
+ *
+ * Based on omap_phy_internal.c code from Linux by
+ * Hema HK <hemahk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/am35x_def.h>
+
+void am35x_musb_reset(void)
+{
+ /* Reset the musb interface */
+ clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
+ 0, USBOTGSS_SW_RST);
+ clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
+ USBOTGSS_SW_RST, 0);
+}
+
+void am35x_musb_phy_power(u8 on)
+{
+ unsigned long start = get_timer(0);
+
+ if (on) {
+ /*
+ * Start the on-chip PHY and its PLL.
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
+ CONF2_PHY_PLLON);
+
+ debug("Waiting for PHY clock good...\n");
+ while (!(readl(&am35x_scm_general_regs->devconf2)
+ & CONF2_PHYCLKGD)) {
+
+ if (get_timer(start) > CONFIG_SYS_HZ / 10) {
+ printf("musb PHY clock good timed out\n");
+ break;
+ }
+ }
+ } else {
+ /*
+ * Power down the on-chip PHY.
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_PHY_PLLON,
+ CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+ }
+}
+
+void am35x_musb_clear_irq(void)
+{
+ clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
+ 0, USBOTGSS_INT_CLR);
+ readl(&am35x_scm_general_regs->lvl_intr_clr);
+}
+
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 819fd2f..d6c038e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -82,7 +82,8 @@ struct cm_wkuppll {
unsigned int clkseldpllcore; /* offset 0x68 */
unsigned int resv9[1];
unsigned int idlestdpllper; /* offset 0x70 */
- unsigned int resv10[3];
+ unsigned int resv10[2];
+ unsigned int clkdcoldodpllper; /* offset 0x7c */
unsigned int divm4dpllcore; /* offset 0x80 */
unsigned int divm5dpllcore; /* offset 0x84 */
unsigned int clkmoddpllmpu; /* offset 0x88 */
@@ -275,12 +276,16 @@ struct ctrl_stat {
/* Control Device Register */
struct ctrl_dev {
unsigned int deviceid; /* offset 0x00 */
- unsigned int resv1[11];
+ unsigned int resv1[7];
+ unsigned int usb_ctrl0; /* offset 0x20 */
+ unsigned int resv2;
+ unsigned int usb_ctrl1; /* offset 0x28 */
+ unsigned int resv3;
unsigned int macid0l; /* offset 0x30 */
unsigned int macid0h; /* offset 0x34 */
unsigned int macid1l; /* offset 0x38 */
unsigned int macid1h; /* offset 0x3c */
- unsigned int resv2[4];
+ unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
};
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 5bd4bc8..24ab365 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -87,4 +87,8 @@
/* RTC base address */
#define AM335X_RTC_BASE 0x44E3E000
+/* OTG */
+#define AM335X_USB0_OTG_BASE 0x47401000
+#define AM335X_USB1_OTG_BASE 0x47401800
+
#endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index d1b2ea8..f06af2e 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -28,6 +28,8 @@
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 */
+#define EXYNOS4_I2C_SPACING 0x10000
+
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
#define EXYNOS4_PRO_ID 0x10000000
#define EXYNOS4_SYSREG_BASE 0x10010000
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
new file mode 100644
index 0000000..8acdf9b
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#define DWMCI_CLKSEL 0x09C
+#define DWMCI_SHIFT_0 0x0
+#define DWMCI_SHIFT_1 0x1
+#define DWMCI_SHIFT_2 0x2
+#define DWMCI_SHIFT_3 0x3
+#define DWMCI_SET_SAMPLE_CLK(x) (x)
+#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+
+int exynos_dwmci_init(u32 regbase, int bus_width, int index);
+
+static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
+{
+ unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
+ return exynos_dwmci_init(base, bus_width, index);
+}
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index 1700fe3..3d39ef2 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -35,6 +35,7 @@ enum mxc_clock {
MXC_SSP1_CLK,
MXC_SSP2_CLK,
MXC_SSP3_CLK,
+ MXC_XTAL_CLK,
};
enum mxs_ioclock {
diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h
index bbaf1bc..67698bc 100644
--- a/arch/arm/include/asm/arch-omap3/am35x_def.h
+++ b/arch/arm/include/asm/arch-omap3/am35x_def.h
@@ -32,9 +32,34 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
+/* LVL_INTR_CLEAR bits */
+#define USBOTGSS_INT_CLR (1 << 4)
+
/* IP_SW_RESET bits */
+#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */
#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */
+/* DEVCONF2 bits */
+#define CONF2_PHY_GPIOMODE (1 << 23)
+#define CONF2_OTGMODE (3 << 14)
+#define CONF2_NO_OVERRIDE (0 << 14)
+#define CONF2_FORCE_HOST (1 << 14)
+#define CONF2_FORCE_DEVICE (2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN (1 << 13)
+#define CONF2_VBDTCTEN (1 << 12)
+#define CONF2_REFFREQ_24MHZ (2 << 8)
+#define CONF2_REFFREQ_26MHZ (7 << 8)
+#define CONF2_REFFREQ_13MHZ (6 << 8)
+#define CONF2_REFFREQ (0xf << 8)
+#define CONF2_PHYCLKGD (1 << 7)
+#define CONF2_VBUSSENSE (1 << 6)
+#define CONF2_PHY_PLLON (1 << 5)
+#define CONF2_RESET (1 << 4)
+#define CONF2_PHYPWRDN (1 << 3)
+#define CONF2_OTGPWRDN (1 << 2)
+#define CONF2_DATPOL (1 << 1)
+
/* General register mappings of system control module */
#define AM35X_SCM_GEN_BASE 0x48002270
struct am35x_scm_general {
@@ -49,6 +74,8 @@ struct am35x_scm_general {
};
#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
+#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
+
#endif /*__ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
diff --git a/arch/arm/include/asm/arch-omap3/musb.h b/arch/arm/include/asm/arch-omap3/musb.h
new file mode 100644
index 0000000..423ac50
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/musb.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, <ilya.yanok@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __ASM_ARCH_OMAP3_MUSB_H
+#define __ASM_ARCH_OMAP3_MUSB_H
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+#endif
diff --git a/arch/arm/include/asm/imx-common/mx5_video.h b/arch/arm/include/asm/imx-common/mx5_video.h
new file mode 100644
index 0000000..e54c25a
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/mx5_video.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012
+ * Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#ifndef __MX5_VIDEO_H
+#define __MX5_VIDEO_H
+
+#ifdef CONFIG_VIDEO
+void lcd_enable(void);
+void setup_iomux_lcd(void);
+#else
+static inline void lcd_enable(void) { }
+static inline void setup_iomux_lcd(void) { }
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h
new file mode 100644
index 0000000..b04d865
--- /dev/null
+++ b/arch/arm/include/asm/omap_musb.h
@@ -0,0 +1,32 @@
+/*
+ * Board data structure for musb gadget on OMAPs
+ *
+ * Copyright (C) 2012, Ilya Yanok <ilya.yanok@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_OMAP_MUSB_H
+#define __ASM_ARM_OMAP_MUSB_H
+
+extern struct musb_platform_ops musb_dsps_ops;
+extern const struct musb_platform_ops am35x_ops;
+extern const struct musb_platform_ops omap2430_ops;
+
+struct omap_musb_board_data {
+ u8 interface_type;
+ void (*set_phy_power)(u8 on);
+ void (*clear_irq)(void);
+ void (*reset)(void);
+};
+
+enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
+#endif /* __ASM_ARM_OMAP_MUSB_H */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 92cad9a..e0cb635 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -224,6 +224,13 @@ int __arch_cpu_init(void)
int arch_cpu_init(void)
__attribute__((weak, alias("__arch_cpu_init")));
+int __power_init_board(void)
+{
+ return 0;
+}
+int power_init_board(void)
+ __attribute__((weak, alias("__power_init_board")));
+
init_fnc_t *init_sequence[] = {
arch_cpu_init, /* basic arch cpu dependent setup */
@@ -525,6 +532,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r();
#endif
+ power_init_board();
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
@@ -532,15 +540,13 @@ void board_init_r(gd_t *id, ulong dest_addr)
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
- char *s = getenv("flashchecksum");
-
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
- if (s && (*s == 'y')) {
+ if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
generated by cgit v1.1 at 2024-11-10 06:06:19 +0000