6 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 4501884..1da5455 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -77,6 +77,16 @@ int clock_twi_onoff(int port, int state)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+	if (port == 5) {
+		if (state)
+			prcm_apb0_enable(
+				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+		else
+			prcm_apb0_disable(
+				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+		return 0;
+	}
+
 	/* set the apb clock gate for twi */
 	if (state)
 		setbits_le32(&ccm->apb2_gate,
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
index 19b4938..e1d091f 100644
--- a/arch/arm/cpu/armv7/sunxi/prcm.c
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -33,3 +33,15 @@ void prcm_apb0_enable(u32 flags)
 	/* deassert reset for module */
 	setbits_le32(&prcm->apb0_reset, flags);
 }
+
+void prcm_apb0_disable(u32 flags)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	/* assert reset for module */
+	clrbits_le32(&prcm->apb0_reset, flags);
+
+	/* close the clock for module */
+	clrbits_le32(&prcm->apb0_gate, flags);
+}
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 63b161a..0cdefdc 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -134,6 +134,7 @@
 #define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
 #define SUN6I_CPUCFG_BASE		0x01f01c00
+#define SUNXI_R_TWI_BASE		0x01f02400
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUN6I_P2WI_BASE			0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index a2a9a38..649f6cd 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -199,6 +199,8 @@ enum sunxi_gpio_number {
 #define SUN6I_GPL1_R_P2WI_SDA	3
 
 #define SUN8I_GPL_R_RSB		2
+#define SUN8I_H3_GPL_R_TWI	2
+#define SUN8I_A23_GPL_R_TWI	3
 #define SUN8I_GPL_R_UART	2
 
 #define SUN9I_GPN_R_RSB		3
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 561cd2b..4dfd313 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -23,6 +23,9 @@
 #ifdef CONFIG_I2C4_ENABLE
 #define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
 #endif
+#ifdef CONFIG_R_I2C_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
+#endif
 
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
 #define CONFIG_SYS_TCLK		24000000
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 82ed541..556c1af 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -236,5 +236,7 @@ struct sunxi_prcm_reg {
 };
 
 void prcm_apb0_enable(u32 flags);
+void prcm_apb0_disable(u32 flags);
+
 #endif /* __ASSEMBLY__ */
 #endif /* _PRCM_H */