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-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.c5
-rw-r--r--arch/arm/cpu/arm720t/tegra124/cpu.c4
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c25
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_am43xx.c1
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c5
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c2
-rw-r--r--arch/arm/cpu/at91-common/spl.c4
-rw-r--r--arch/arm/include/asm/arch-at91/gpio.h2
-rw-r--r--arch/arm/include/asm/arch-at91/spl.h4
-rw-r--r--arch/arm/include/asm/arch-tegra/pmc.h11
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra.h5
-rw-r--r--arch/arm/include/asm/arch-tegra114/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tegra124/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tegra30/tegra.h2
15 files changed, 67 insertions, 9 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 2c5cd63..168f525 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
void halt_avp(void)
{
for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
+ writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+ FLOW_CTLR_HALT_COP_EVENTS);
}
}
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
index c03aaf1..97f5928 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
tegra124_init_clocks();
/* Set power-gating timer multiplier */
- clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
- setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+ writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+ &pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
enable_cpu_clocks();
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 99a3913..6b51d5f 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask)
}
#endif
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+ /* Enable mci clock */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
+
+ at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
+
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+ at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
+ at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
+#else
+ at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
+#endif
+}
+#endif
+
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 57f5949..d0bc234 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -97,6 +97,7 @@ void enable_basic_clocks(void)
&cmper->gpio4clkctrl,
&cmper->gpio5clkctrl,
&cmper->i2c1clkctrl,
+ &cmper->cpgmac0clkctrl,
&cmper->emiffwclkctrl,
&cmper->emifclkctrl,
&cmper->otfaemifclkctrl,
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index d05e666..9a625c4 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -80,8 +80,8 @@ static void configure_mr(int nr, u32 cs)
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
- writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
- writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+ writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
@@ -96,6 +96,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
configure_mr(nr, 0);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index d28fceb..3e39752 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -113,7 +113,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
;
- writel(0x0, &ddrctrl->ddrioctrl);
+ writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
index 37c0cc4..7f4debb 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -52,6 +52,10 @@ u32 spl_boot_device(void)
{
#ifdef CONFIG_SYS_USE_MMC
return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+ return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+ return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_NONE;
}
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
index ff6142b..7121388 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/include/asm/arch-at91/gpio.h
@@ -214,7 +214,7 @@ static inline unsigned pin_to_mask(unsigned pin)
/* The following macros are need for backward compatibility */
#define at91_set_GPIO_periph(x, y) \
- at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
+ at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_A_periph(x, y) \
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_B_periph(x, y) \
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
index 68c5349..d8a87da 100644
--- a/arch/arm/include/asm/arch-at91/spl.h
+++ b/arch/arm/include/asm/arch-at91/spl.h
@@ -14,6 +14,10 @@ enum {
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_MMC2_2,
+#elif CONFIG_SYS_USE_NANDFLASH
+ BOOT_DEVICE_NAND,
+#elif CONFIG_SYS_USE_SERIALFLASH
+ BOOT_DEVICE_SPI,
#endif
};
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 4c3264b..1dd3154 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -298,14 +298,25 @@ struct pmc_ctlr {
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
+#if defined(CONFIG_TEGRA114)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT 0
+#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT 3
+#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
#define MULT_1 0
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16 4
+#endif
#define AMAP_WRITE_SHIFT 20
#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 5fe19ae..d63af0e 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -34,7 +34,12 @@
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+ defined(CONFIG_TEGRA114)
#define NV_PA_CSITE_BASE 0x70040000
+#else
+#define NV_PA_CSITE_BASE 0x70800000
+#endif
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index 5d426b5..705ca57 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -17,6 +17,8 @@
#ifndef _TEGRA114_H_
#define _TEGRA114_H_
+#define CONFIG_TEGRA114
+
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
index db3d837..86ebd19 100644
--- a/arch/arm/include/asm/arch-tegra124/tegra.h
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -8,6 +8,8 @@
#ifndef _TEGRA124_H_
#define _TEGRA124_H_
+#define CONFIG_TEGRA124
+
#define NV_PA_SDRAM_BASE 0x80000000
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 18856ac..6a4b40e 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -8,6 +8,8 @@
#ifndef _TEGRA20_H_
#define _TEGRA20_H_
+#define CONFIG_TEGRA20
+
#define NV_PA_SDRAM_BASE 0x00000000
#include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index c02c5d8..4ad8b1c 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -17,6 +17,8 @@
#ifndef _TEGRA30_H_
#define _TEGRA30_H_
+#define CONFIG_TEGRA30
+
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
#include <asm/arch-tegra/tegra.h>
generated by cgit v1.1 at 2024-11-19 14:59:55 +0000