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-rw-r--r--arch/arm/mach-at91/Kconfig5
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/armv7/Makefile1
-rw-r--r--arch/arm/mach-at91/armv7/sama5d2_devices.c57
-rw-r--r--arch/arm/mach-at91/armv7/sama5d4_devices.c55
-rw-r--r--arch/arm/mach-at91/atmel_sfr.c21
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h9
-rw-r--r--arch/arm/mach-at91/include/mach/atmel_pio4.h48
-rw-r--r--arch/arm/mach-at91/include/mach/atmel_usba_udc.h3
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-at91/include/mach/sama5_sfr.h1
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d2.h203
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d4.h28
-rw-r--r--arch/arm/mach-at91/matrix.c34
14 files changed, 406 insertions, 63 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index fdaf328..c333647 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -71,6 +71,10 @@ config TARGET_AT91SAM9X5EK
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_SAMA5D2_XPLAINED
+ bool "SAMA5D2 Xplained board"
+ select CPU_V7
+
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
select CPU_V7
@@ -123,6 +127,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 30f2b49..5b89617 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-y += spl.o
endif
diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile
index f4f35a4..9538bc1 100644
--- a/arch/arm/mach-at91/armv7/Makefile
+++ b/arch/arm/mach-at91/armv7/Makefile
@@ -8,6 +8,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o
obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
obj-y += clock.o
diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c
new file mode 100644
index 0000000..88f8f2c
--- /dev/null
+++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d2.h>
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d2()) {
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D21CU:
+ return "SAMA5D21";
+ case ARCH_EXID_SAMA5D22CU:
+ return "SAMA5D22-CU";
+ case ARCH_EXID_SAMA5D22CN:
+ return "SAMA5D22-CN";
+ case ARCH_EXID_SAMA5D23CU:
+ return "SAMA5D23-CU";
+ case ARCH_EXID_SAMA5D24CX:
+ return "SAMA5D24-CX";
+ case ARCH_EXID_SAMA5D24CU:
+ return "SAMA5D24-CU";
+ case ARCH_EXID_SAMA5D26CU:
+ return "SAMA5D26-CU";
+ case ARCH_EXID_SAMA5D27CU:
+ return "SAMA5D27-CU";
+ case ARCH_EXID_SAMA5D27CN:
+ return "SAMA5D27-CN";
+ case ARCH_EXID_SAMA5D28CU:
+ return "SAMA5D28-CU";
+ case ARCH_EXID_SAMA5D28CN:
+ return "SAMA5D28-CN";
+ }
+ }
+
+ return "Unknown CPU type";
+}
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+void at91_udp_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+
+ at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c
index 76301d6..ce33cd4 100644
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -10,7 +10,6 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
-#include <asm/arch/sama5_matrix.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/sama5d4.h>
@@ -46,57 +45,3 @@ void at91_udp_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_UDPHS);
}
#endif
-
-#ifdef CONFIG_SPL_BUILD
-void matrix_init(void)
-{
- struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
- struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
- int i;
-
- /* Disable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
- /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
- for (i = 4; i <= 10; i++) {
- writel(0x000f0f0f, &h64mx->ssr[i]);
- writel(0x0000ffff, &h64mx->sassr[i]);
- writel(0x0000000f, &h64mx->srtsr[i]);
- }
-
- /* CS3 */
- writel(0x00c0c0c0, &h32mx->ssr[3]);
- writel(0xff000000, &h32mx->sassr[3]);
- writel(0xff000000, &h32mx->srtsr[3]);
-
- /* NFC SRAM */
- writel(0x00010101, &h32mx->ssr[4]);
- writel(0x00000001, &h32mx->sassr[4]);
- writel(0x00000001, &h32mx->srtsr[4]);
-
- /* Configure Programmable Security peripherals on matrix 64 */
- writel(readl(&h64mx->spselr[0]) | 0x00080000, &h64mx->spselr[0]);
- writel(readl(&h64mx->spselr[1]) | 0x00180000, &h64mx->spselr[1]);
- writel(readl(&h64mx->spselr[2]) | 0x00000008, &h64mx->spselr[2]);
-
- /* Configure Programmable Security peripherals on matrix 32 */
- writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]);
- writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]);
-
- /* Enable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-}
-
-void redirect_int_from_saic_to_aic(void)
-{
- struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
- u32 key32;
-
- if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
- key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
- writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
- }
-}
-#endif
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
new file mode 100644
index 0000000..2bccb84
--- /dev/null
+++ b/arch/arm/mach-at91/atmel_sfr.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_sfr.h>
+
+void redirect_int_from_saic_to_aic(void)
+{
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ u32 key32;
+
+ if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
+ key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
+ writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
+ }
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 5a51be6..3f50f77 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -78,7 +78,8 @@ typedef struct at91_pmc {
#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4)
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
#else
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
@@ -97,7 +98,8 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4) || \
defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
@@ -127,10 +129,7 @@ typedef struct at91_pmc {
#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
-#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
#endif
diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h
new file mode 100644
index 0000000..8bb4b12
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation.
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ATMEL_PIO4_H
+#define __ATMEL_PIO4_H
+
+#ifndef __ASSEMBLY__
+
+struct atmel_pio4_port {
+ u32 mskr; /* 0x00 PIO Mask Register */
+ u32 cfgr; /* 0x04 PIO Configuration Register */
+ u32 pdsr; /* 0x08 PIO Pin Data Status Register */
+ u32 locksr; /* 0x0C PIO Lock Status Register */
+ u32 sodr; /* 0x10 PIO Set Output Data Register */
+ u32 codr; /* 0x14 PIO Clear Output Data Register */
+ u32 odsr; /* 0x18 PIO Output Data Status Register */
+ u32 reserved0;
+ u32 ier; /* 0x20 PIO Interrupt Enable Register */
+ u32 idr; /* 0x24 PIO Interrupt Disable Register */
+ u32 imr; /* 0x28 PIO Interrupt Mask Register */
+ u32 isr; /* 0x2C PIO Interrupt Status Register */
+ u32 reserved1[3];
+ u32 iofr; /* 0x3C PIO I/O Freeze Register */
+};
+
+#endif
+
+#define AT91_PIO_PORTA 0x0
+#define AT91_PIO_PORTB 0x1
+#define AT91_PIO_PORTC 0x2
+#define AT91_PIO_PORTD 0x3
+
+int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value);
+int atmel_pio4_get_pio_input(u32 port, u32 pin);
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
index 38b5012..46a329b 100644
--- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
@@ -31,7 +31,8 @@ static struct usba_ep_data usba_udc_ep[] = {
EP("ep5", 5, 1024, 3, 1, 1),
EP("ep6", 6, 1024, 3, 1, 1),
};
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4)
static struct usba_ep_data usba_udc_ep[] = {
EP("ep0", 0, 64, 1, 0, 0),
EP("ep1", 1, 1024, 3, 1, 0),
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index ff6b71b..38abfda 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -23,6 +23,8 @@
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
+#elif defined(CONFIG_SAMA5D2)
+# include <asm/arch/sama5d2.h>
#elif defined(CONFIG_SAMA5D3)
# include <asm/arch/sama5d3.h>
#elif defined(CONFIG_SAMA5D4)
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
index 3081d37..7b19a20 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
@@ -32,7 +32,6 @@ struct atmel_sfr {
#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
/* Bit field in AICREDIR */
-#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
new file mode 100644
index 0000000..c85571c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -0,0 +1,203 @@
+/*
+ * Chip-specific header file for the SAMA5D2 SoC
+ *
+ * Copyright (C) 2015 Atmel
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5D2_H
+#define __SAMA5D2_H
+
+/*
+ * definitions to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* It's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */
+/* 1 */
+#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */
+#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */
+#define ATMEL_ID_GMAC 5 /* Ethernet MAC */
+#define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
+#define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */
+#define ATMEL_ID_ICM 8 /* Integrity Check Monitor */
+#define ATMEL_ID_AES 9 /* Advanced Encryption Standard */
+#define ATMEL_ID_AESB 10 /* AES bridge */
+#define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */
+#define ATMEL_ID_SHA 12 /* SHA Signature */
+#define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */
+#define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
+#define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
+#define ATMEL_ID_SECUMOD 16 /* Secure Module */
+#define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
+#define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */
+#define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */
+#define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */
+#define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */
+#define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */
+#define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */
+#define ATMEL_ID_UART0 24 /* UART0 */
+#define ATMEL_ID_UART1 25 /* UART1 */
+#define ATMEL_ID_UART2 26 /* UART2 */
+#define ATMEL_ID_UART3 27 /* UART3 */
+#define ATMEL_ID_UART4 28 /* UART4 */
+#define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
+#define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
+#define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
+#define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */
+#define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
+#define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */
+/* 37 */
+#define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */
+/* 39 */
+#define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */
+#define ATMEL_ID_UHPHS 41 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 42 /* USB Device High Speed */
+#define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_LCDC 45 /* LCD Controller */
+#define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */
+#define ATMEL_ID_TRNG 47 /* True Random Number Generator */
+#define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */
+#define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */
+#define ATMEL_ID_SFC 50 /* Fuse Controller */
+#define ATMEL_ID_SECURAM 51 /* Secure RAM */
+#define ATMEL_ID_QSPI0 52 /* QSPI0 */
+#define ATMEL_ID_QSPI1 53 /* QSPI1 */
+#define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
+#define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */
+#define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
+#define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */
+/* 58 */
+#define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */
+#define ATMEL_ID_SFR 60 /* Special Function Register */
+#define ATMEL_ID_SAIC 61 /* Secured AIC */
+#define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */
+#define ATMEL_ID_L2CC 63 /* L2 Cache Controller */
+#define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */
+#define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */
+#define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */
+#define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */
+#define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */
+#define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */
+#define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */
+/* 73 */
+#define ATMEL_ID_SYS 74 /* System Controller Interrupt */
+#define ATMEL_ID_ACC 75 /* Analog Comparator */
+#define ATMEL_ID_RXLP 76 /* UART Low-Power */
+#define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */
+#define ATMEL_ID_CHIPID 78 /* Chip ID */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_LCDC 0xf0000000
+#define ATMEL_BASE_XDMAC1 0xf0004000
+#define ATMEL_BASE_MPDDRC 0xf000c000
+#define ATMEL_BASE_XDMAC0 0xf0010000
+#define ATMEL_BASE_PMC 0xf0014000
+#define ATMEL_BASE_QSPI0 0xf0020000
+#define ATMEL_BASE_QSPI1 0xf0024000
+#define ATMEL_BASE_SPI0 0xf8000000
+#define ATMEL_BASE_GMAC 0xf8008000
+#define ATMEL_BASE_TC0 0xf800c000
+#define ATMEL_BASE_TC1 0xf8010000
+#define ATMEL_BASE_HSMC 0xf8014000
+#define ATMEL_BASE_UART0 0xf801c000
+#define ATMEL_BASE_UART1 0xf8020000
+#define ATMEL_BASE_UART2 0xf8024000
+#define ATMEL_BASE_TWI0 0xf8028000
+#define ATMEL_BASE_SYSC 0xf8048000
+#define ATMEL_BASE_SPI1 0xfc000000
+#define ATMEL_BASE_UART3 0xfc008000
+#define ATMEL_BASE_UART4 0xfc00c000
+#define ATMEL_BASE_TWI1 0xfc028000
+#define ATMEL_BASE_UDPHS 0xfc02c000
+
+#define ATMEL_BASE_PIOA 0xfc038000
+
+#define ATMEL_CHIPID_CIDR 0xfc069000
+#define ATMEL_CHIPID_EXID 0xfc069004
+
+/*
+ * Address Memory Space
+ */
+#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000
+#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000
+#define ATMEL_BASE_SDMMC0 0xa0000000
+#define ATMEL_BASE_SDMMC1 0xb0000000
+#define ATMEL_BASE_QSPI0_MEM 0xd0000000
+#define ATMEL_BASE_QSPI1_MEM 0xd8000000
+
+/*
+ * Internal Memories
+ */
+#define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */
+
+/*
+ * SYSC Spawns
+ */
+#define ATMEL_BASE_RSTC ATMEL_BASE_SYSC
+#define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10)
+#define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30)
+#define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40)
+#define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50)
+#define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0)
+
+/*
+ * Other misc definitions
+ */
+#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70)
+#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500)
+
+#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
+#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
+#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40)
+
+#define ATMEL_PIO_PORTS 4
+#define CPU_HAS_PCR
+#define CPU_HAS_H32MXDIV
+
+/* SAMA5D2 series chip id definitions */
+#define ARCH_ID_SAMA5D2 0x8a5c08c0
+#define ARCH_EXID_SAMA5D21CU 0x0000005a
+#define ARCH_EXID_SAMA5D22CU 0x00000059
+#define ARCH_EXID_SAMA5D22CN 0x00000069
+#define ARCH_EXID_SAMA5D23CU 0x00000058
+#define ARCH_EXID_SAMA5D24CX 0x00000004
+#define ARCH_EXID_SAMA5D24CU 0x00000014
+#define ARCH_EXID_SAMA5D26CU 0x00000012
+#define ARCH_EXID_SAMA5D27CU 0x00000011
+#define ARCH_EXID_SAMA5D27CN 0x00000021
+#define ARCH_EXID_SAMA5D28CU 0x00000010
+#define ARCH_EXID_SAMA5D28CN 0x00000020
+
+#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2)
+
+/* PIT Timer(PIT_PIIR) */
+#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
+
+/* No PMECC Galois table in ROM */
+#define NO_GALOIS_TABLE_IN_ROM
+
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 3da8aff..90085da 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -179,6 +179,34 @@
#define CPU_HAS_PCR
#define CPU_HAS_H32MXDIV
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_VDEC 2 /* Video Decoder */
+#define H64MX_SLAVE_DDRC_PORT0 3 /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1 4 /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2 5 /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3 6 /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4 7 /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5 8 /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6 9 /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7 10 /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM 11 /* Internal SRAM 128K */
+#define H64MX_SLAVE_H32MX_BRIDGE 12 /* Bridge from H64MX to H32MX */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI 3 /* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */
+#define H32MX_SLAVE_USB 5 /* USB Device & Host */
+#define H32MX_SLAVE_SMD 6 /* Soft Modem (SMD) */
+
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+
/* sama5d4 series chip id definitions */
#define ARCH_ID_SAMA5D4 0x8a5c07c0
#define ARCH_EXID_SAMA5D41 0x00000001
diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
new file mode 100644
index 0000000..57d7270
--- /dev/null
+++ b/arch/arm/mach-at91/matrix.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_matrix.h>
+
+void matrix_init(void)
+{
+ struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
+ struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
+ int i;
+
+ /* DDR port 1 ~ port 7 */
+ for (i = H64MX_SLAVE_DDRC_PORT1; i <= H64MX_SLAVE_DDRC_PORT7; i++) {
+ writel(0x000f0f0f, &h64mx->ssr[i]);
+ writel(0x0000ffff, &h64mx->sassr[i]);
+ writel(0x0000000f, &h64mx->srtsr[i]);
+ }
+
+ /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */
+ writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]);
+ writel(0xff000000, &h32mx->sassr[H32MX_SLAVE_EBI]);
+ writel(0xff000000, &h32mx->srtsr[H32MX_SLAVE_EBI]);
+
+ /* NFC SRAM */
+ writel(0x00010101, &h32mx->ssr[H32MX_SLAVE_NFC_SRAM]);
+ writel(0x00000001, &h32mx->sassr[H32MX_SLAVE_NFC_SRAM]);
+ writel(0x00000001, &h32mx->srtsr[H32MX_SLAVE_NFC_SRAM]);
+}
generated by cgit v1.1 at 2024-11-06 06:24:15 +0000