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-rw-r--r--arch/arm/mach-uniphier/dram/cmd_ddrphy.c3
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c3
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c3
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c3
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-regs.h179
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-training.c3
-rw-r--r--arch/arm/mach-uniphier/dram/umc-ph1-ld4.c7
-rw-r--r--arch/arm/mach-uniphier/dram/umc-ph1-pro4.c7
-rw-r--r--arch/arm/mach-uniphier/dram/umc-ph1-sld8.c7
-rw-r--r--arch/arm/mach-uniphier/dram/umc-regs.h119
10 files changed, 320 insertions, 14 deletions
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index f9b79ab..078eb6f 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -6,7 +6,8 @@
#include <common.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */
#if 1
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
index 991d929..d2bc5a1 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
@@ -6,7 +6,8 @@
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
index bc47ba3..2c8cbc2 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
@@ -6,7 +6,8 @@
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
index 39024a0..6510690 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
@@ -7,7 +7,8 @@
#include <config.h>
#include <linux/types.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
new file mode 100644
index 0000000..03aedc2
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -0,0 +1,179 @@
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+ u32 ridr; /* Revision Identification Register */
+ u32 pir; /* PHY Initialixation Register */
+ u32 pgcr[2]; /* PHY General Configuration Register */
+ u32 pgsr[2]; /* PHY General Status Register */
+ u32 pllcr; /* PLL Control Register */
+ u32 ptr[5]; /* PHY Timing Register */
+ u32 acmdlr; /* AC Master Delay Line Register */
+ u32 acbdlr; /* AC Bit Delay Line Register */
+ u32 aciocr; /* AC I/O Configuration Register */
+ u32 dxccr; /* DATX8 Common Configuration Register */
+ u32 dsgcr; /* DDR System General Configuration Register */
+ u32 dcr; /* DRAM Configuration Register */
+ u32 dtpr[3]; /* DRAM Timing Parameters Register */
+ u32 mr0; /* Mode Register 0 */
+ u32 mr1; /* Mode Register 1 */
+ u32 mr2; /* Mode Register 2 */
+ u32 mr3; /* Mode Register 3 */
+ u32 odtcr; /* ODT Configuration Register */
+ u32 dtcr; /* Data Training Configuration Register */
+ u32 dtar[4]; /* Data Training Address Register */
+ u32 dtdr[2]; /* Data Training Data Register */
+ u32 dtedr[2]; /* Data Training Eye Data Register */
+ u32 pgcr2; /* PHY General Configuration Register 2 */
+ u32 rsv0[8]; /* Reserved */
+ u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
+ u32 rdimmcr0[2]; /* RDIMM Control Register */
+ u32 dcuar; /* DCU Address Register */
+ u32 dcudr; /* DCU Data Register */
+ u32 dcurr; /* DCU Run Register */
+ u32 dculr; /* DCU Loop Register */
+ u32 dcugcr; /* DCU General Configuration Register */
+ u32 dcutpr; /* DCU Timing Parameters Register */
+ u32 dcusr[2]; /* DCU Status Register */
+ u32 rsv1[8]; /* Reserved */
+ u32 bistrr; /* BIST Run Register */
+ u32 bistwcr; /* BIST Word Count Register */
+ u32 bistmskr[3]; /* BIST Mask Register */
+ u32 bistlsr; /* BIST LFSR Sed Register */
+ u32 bistar[3]; /* BIST Address Register */
+ u32 bistudpr; /* BIST User Data Pattern Register */
+ u32 bistgsr; /* BIST General Status Register */
+ u32 bistwer; /* BIST Word Error Register */
+ u32 bistber[4]; /* BIST Bit Error Register */
+ u32 bistwcsr; /* BIST Word Count Status Register */
+ u32 bistfwr[3]; /* BIST Fail Word Register */
+ u32 rsv2[10]; /* Reserved */
+ u32 gpr[2]; /* General Purpose Register */
+ struct ddrphy_zq { /* ZQ */
+ u32 cr[2]; /* Impedance Control Register */
+ u32 sr[2]; /* Impedance Status Register */
+ } zq[4];
+ struct ddrphy_datx8 { /* DATX8 */
+ u32 gcr; /* General Configuration Register */
+ u32 gsr[2]; /* General Status Register */
+ u32 bdlr[5]; /* Bit Delay Line Register */
+ u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
+ u32 mdlr; /* Master Delay Line Register */
+ u32 gtr; /* General Timing Register */
+ u32 gsr2; /* General Status Register 2 */
+ u32 rsv[2]; /* Reserved */
+ } dx[9];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT BIT(0) /* Initialization Trigger */
+#define PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PIR_DCAL BIT(5) /* DDL Calibration */
+#define PIR_PHYRST BIT(6) /* PHY Reset */
+#define PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PIR_WL BIT(9) /* Write Leveling */
+#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PIR_INITBYP BIT(31) /* Initialization Bypass */
+
+#define PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PGSR0_IERR BIT(16) /* Initialization Error */
+#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
+#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
+#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
+#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN (0 << 5)
+#define DXCCR_DQSRES_688_OHM (1 << 5)
+#define DXCCR_DQSRES_611_OHM (2 << 5)
+#define DXCCR_DQSRES_550_OHM (3 << 5)
+#define DXCCR_DQSRES_500_OHM (4 << 5)
+#define DXCCR_DQSRES_458_OHM (5 << 5)
+#define DXCCR_DQSRES_393_OHM (6 << 5)
+#define DXCCR_DQSRES_344_OHM (7 << 5)
+
+#define DXCCR_DQSNRES_OPEN (0 << 9)
+#define DXCCR_DQSNRES_688_OHM (1 << 9)
+#define DXCCR_DQSNRES_611_OHM (2 << 9)
+#define DXCCR_DQSNRES_550_OHM (3 << 9)
+#define DXCCR_DQSNRES_500_OHM (4 << 9)
+#define DXCCR_DQSNRES_458_OHM (5 << 9)
+#define DXCCR_DQSNRES_393_OHM (6 << 9)
+#define DXCCR_DQSNRES_344_OHM (7 << 9)
+
+#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY 2
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+#define NR_DDRPHY_PER_CH 1
+#else
+#define NR_DDRPHY_PER_CH 2
+#endif
+
+#define NR_DDRCH 2
+
+#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c
index 4852f2d..a348136 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-training.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c
@@ -7,7 +7,8 @@
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
+
+#include "ddrphy-regs.h"
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
{
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index 8124685..ffd7aa9 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -8,9 +8,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index 8c9f057..4d976e3 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -8,9 +8,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index bc60a34..09f9ccf 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -8,9 +8,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
static void umc_start_ssif(void __iomem *ssif_base)
{
diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h b/arch/arm/mach-uniphier/dram/umc-regs.h
new file mode 100644
index 0000000..6159281
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-regs.h
@@ -0,0 +1,119 @@
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE 0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE UMC_BASE
+
+#define UMC_CPURST 0x00000700
+#define UMC_IDSRST 0x0000070C
+#define UMC_IXMRST 0x00000714
+#define UMC_HDMRST 0x00000718
+#define UMC_MDMRST 0x0000071C
+#define UMC_HDDRST 0x00000720
+#define UMC_MDDRST 0x00000724
+#define UMC_SIORST 0x00000728
+#define UMC_GIORST 0x0000072C
+#define UMC_HD2RST 0x00000734
+#define UMC_VIORST 0x0000073C
+#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST 0x00000748 /* Pro4 */
+#define UMC_RGLRST 0x00000750
+#define UMC_VPERST 0x00000758
+#define UMC_AIORST 0x00000764
+#define UMC_DMDRST 0x00000770
+
+#define UMC_HDMCHSEL 0x00000898
+#define UMC_MDMCHSEL 0x0000089C
+#define UMC_DVCCHSEL 0x000008C8
+#define UMC_DMDCHSEL 0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH 0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
+#define UMC_CLKEN_SSIF_WC 0x0000C07C
+#define UMC_CLKEN_SSIF_RC 0x0000C080
+#define UMC_CLKEN_SSIF_DST 0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA 0x00000000
+#define UMC_CMDCTLB 0x00000004
+#define UMC_INITCTLA 0x00000008
+#define UMC_INITCTLB 0x0000000C
+#define UMC_INITCTLC 0x00000010
+#define UMC_INITSET 0x00000014
+#define UMC_INITSTAT 0x00000018
+#define UMC_DRMMR0 0x0000001C
+#define UMC_DRMMR1 0x00000020
+#define UMC_DRMMR2 0x00000024
+#define UMC_DRMMR3 0x00000028
+#define UMC_SPCCTLA 0x00000030
+#define UMC_SPCCTLB 0x00000034
+#define UMC_SPCSETA 0x00000038
+#define UMC_SPCSETB 0x0000003C
+#define UMC_SPCSETC 0x00000040
+#define UMC_SPCSETD 0x00000044
+#define UMC_SPCSTATA 0x00000050
+#define UMC_SPCSTATB 0x00000054
+#define UMC_SPCSTATC 0x00000058
+#define UMC_ACSSETA 0x00000060
+#define UMC_FLOWCTLA 0x00000400
+#define UMC_FLOWCTLB 0x00000404
+#define UMC_FLOWCTLC 0x00000408
+#define UMC_FLOWCTLG 0x00000508
+#define UMC_RDATACTL_D0 0x00000600
+#define UMC_WDATACTL_D0 0x00000604
+#define UMC_RDATACTL_D1 0x00000608
+#define UMC_WDATACTL_D1 0x0000060C
+#define UMC_DATASET 0x00000610
+#define UMC_DCCGCTL 0x00000720
+#define UMC_DICGCTLA 0x00000724
+#define UMC_DICGCTLB 0x00000728
+#define UMC_DIOCTLA 0x00000C00
+#define UMC_DFICUPDCTLA 0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+ u32 nmask = ~mask;
+ u32 data;
+ do {
+ data = readl(address) & nmask;
+ } while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+ writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+ while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+ ;
+}
+
+#endif
+
+#endif
generated by cgit v1.1 at 2024-11-02 09:59:03 +0000