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-rw-r--r--arch/arm/mach-mvebu/Makefile24
-rw-r--r--arch/arm/mach-mvebu/cpu.c249
-rw-r--r--arch/arm/mach-mvebu/dram.c144
-rw-r--r--arch/arm/mach-mvebu/gpio.c30
-rw-r--r--arch/arm/mach-mvebu/include/mach/config.h91
-rw-r--r--arch/arm/mach-mvebu/include/mach/cpu.h130
-rw-r--r--arch/arm/mach-mvebu/include/mach/soc.h63
-rw-r--r--arch/arm/mach-mvebu/lowlevel_spl.S61
-rw-r--r--arch/arm/mach-mvebu/mbus.c468
-rw-r--r--arch/arm/mach-mvebu/serdes/Makefile6
-rw-r--r--arch/arm/mach-mvebu/serdes/board_env_spec.h262
-rw-r--r--arch/arm/mach-mvebu/serdes/high_speed_env_lib.c1572
-rw-r--r--arch/arm/mach-mvebu/serdes/high_speed_env_spec.c185
-rw-r--r--arch/arm/mach-mvebu/serdes/high_speed_env_spec.h87
-rw-r--r--arch/arm/mach-mvebu/spl.c38
-rw-r--r--arch/arm/mach-mvebu/timer.c147
-rw-r--r--arch/arm/mach-mvebu/u-boot-spl.lds57
17 files changed, 3614 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
new file mode 100644
index 0000000..4f477cd
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile
@@ -0,0 +1,24 @@
+#
+# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_KIRKWOOD
+
+obj-y = dram.o
+obj-y += gpio.o
+obj-y += timer.o
+
+else
+
+obj-y = cpu.o
+obj-y += dram.o
+obj-y += gpio.o
+obj-y += mbus.o
+obj-y += timer.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+
+obj-y += serdes/
+endif
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
new file mode 100644
index 0000000..04681fc
--- /dev/null
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
+
+static struct mbus_win windows[] = {
+ /* PCIE MEM address space */
+ { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+
+ /* PCIE IO address space */
+ { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+
+ /* SPI */
+ { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+ CPU_ATTR_SPIFLASH },
+
+ /* NOR */
+ { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+ CPU_ATTR_BOOTROM },
+};
+
+void reset_cpu(unsigned long ignored)
+{
+ struct mvebu_system_registers *reg =
+ (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
+
+ writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
+ writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
+ while (1)
+ ;
+}
+
+int mvebu_soc_family(void)
+{
+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+
+ if (devid == SOC_MV78460_ID)
+ return MVEBU_SOC_AXP;
+
+ if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
+ devid == SOC_88F6828_ID)
+ return MVEBU_SOC_A38X;
+
+ return MVEBU_SOC_UNKNOWN;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+ u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+
+ puts("SoC: ");
+
+ switch (devid) {
+ case SOC_MV78460_ID:
+ puts("MV78460-");
+ break;
+ case SOC_88F6810_ID:
+ puts("MV88F6810-");
+ break;
+ case SOC_88F6820_ID:
+ puts("MV88F6820-");
+ break;
+ case SOC_88F6828_ID:
+ puts("MV88F6828-");
+ break;
+ default:
+ puts("Unknown-");
+ break;
+ }
+
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ switch (revid) {
+ case 1:
+ puts("A0\n");
+ break;
+ case 2:
+ puts("B0\n");
+ break;
+ default:
+ printf("?? (%x)\n", revid);
+ break;
+ }
+ }
+
+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+ switch (revid) {
+ case MV_88F68XX_Z1_ID:
+ puts("Z1\n");
+ break;
+ case MV_88F68XX_A0_ID:
+ puts("A0\n");
+ break;
+ default:
+ printf("?? (%x)\n", revid);
+ break;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * This function initialize Controller DRAM Fastpath windows.
+ * It takes the CS size information from the 0x1500 scratch registers
+ * and sets the correct windows sizes and base addresses accordingly.
+ *
+ * These values are set in the scratch registers by the Marvell
+ * DDR3 training code, which is executed by the BootROM before the
+ * main payload (U-Boot) is executed. This training code is currently
+ * only available in the Marvell U-Boot version. It needs to be
+ * ported to mainline U-Boot SPL at some point.
+ */
+static void update_sdram_window_sizes(void)
+{
+ u64 base = 0;
+ u32 size, temp;
+ int i;
+
+ for (i = 0; i < SDRAM_MAX_CS; i++) {
+ size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
+ if (size != 0) {
+ size |= ~(SDRAM_ADDR_MASK);
+
+ /* Set Base Address */
+ temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
+ writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
+
+ /*
+ * Check if out of max window size and resize
+ * the window
+ */
+ temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
+ ~(SDRAM_ADDR_MASK)) | 1;
+ temp |= (size & SDRAM_ADDR_MASK);
+ writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
+
+ base += ((u64)size + 1);
+ } else {
+ /*
+ * Disable window if not used, otherwise this
+ * leads to overlapping enabled windows with
+ * pretty strange results
+ */
+ clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
+ }
+ }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+
+ /*
+ * We need to call mvebu_mbus_probe() before calling
+ * update_sdram_window_sizes() as it disables all previously
+ * configured mbus windows and then configures them as
+ * required for U-Boot. Calling update_sdram_window_sizes()
+ * without this configuration will not work, as the internal
+ * registers can't be accessed reliably because of potenial
+ * double mapping.
+ * After updating the SDRAM access windows we need to call
+ * mvebu_mbus_probe() again, as this now correctly configures
+ * the SDRAM areas that are later used by the MVEBU drivers
+ * (e.g. USB, NETA).
+ */
+
+ /*
+ * First disable all windows
+ */
+ mvebu_mbus_probe(NULL, 0);
+
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ /*
+ * Now the SDRAM access windows can be reconfigured using
+ * the information in the SDRAM scratch pad registers
+ */
+ update_sdram_window_sizes();
+ }
+
+ /*
+ * Finally the mbus windows can be configured with the
+ * updated SDRAM sizes
+ */
+ mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ /* Nothing yet, perhaps we need something here later */
+ return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVNETA
+int cpu_eth_init(bd_t *bis)
+{
+ u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
+ MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
+ u8 phy_addr[] = CONFIG_PHY_ADDR;
+ int i;
+
+ /*
+ * Only Armada XP supports all 4 ethernet interfaces. A38x has
+ * slightly different base addresses for its 2-3 interfaces.
+ */
+ if (mvebu_soc_family() != MVEBU_SOC_AXP) {
+ enet_base[1] = MVEBU_EGIGA2_BASE;
+ enet_base[2] = MVEBU_EGIGA3_BASE;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
+ mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
+
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Avoid problem with e.g. neta ethernet driver */
+ invalidate_dcache_all();
+
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c
new file mode 100644
index 0000000..db18791
--- /dev/null
+++ b/arch/arm/mach-mvebu/dram.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sdram_bank {
+ u32 win_bar;
+ u32 win_sz;
+};
+
+struct sdram_addr_dec {
+ struct sdram_bank sdram_bank[4];
+};
+
+#define REG_CPUCS_WIN_ENABLE (1 << 0)
+#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
+#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
+#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+
+/*
+ * mvebu_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 mvebu_sdram_bar(enum memory_bank bank)
+{
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
+ u32 result = 0;
+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+
+ result = readl(&base->sdram_bank[bank].win_bar);
+ return result;
+}
+
+/*
+ * mvebu_sdram_bs_set - writes SDRAM Bank size
+ */
+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
+ /* Read current register value */
+ u32 reg = readl(&base->sdram_bank[bank].win_sz);
+
+ /* Clear window size */
+ reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
+
+ /* Set new window size */
+ reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+
+ writel(reg, &base->sdram_bank[bank].win_sz);
+}
+
+/*
+ * mvebu_sdram_bs - reads SDRAM Bank size
+ */
+u32 mvebu_sdram_bs(enum memory_bank bank)
+{
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
+ u32 result = 0;
+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+ result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
+ result += 0x01000000;
+ return result;
+}
+
+void mvebu_sdram_size_adjust(enum memory_bank bank)
+{
+ u32 size;
+
+ /* probe currently equipped RAM size */
+ size = get_ram_size((void *)mvebu_sdram_bar(bank),
+ mvebu_sdram_bs(bank));
+
+ /* adjust SDRAM window size accordingly */
+ mvebu_sdram_bs_set(bank, size);
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
+ gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ /*
+ * Don't report more than 3GiB of SDRAM, otherwise there is no
+ * address space left for the internal registers etc.
+ */
+ if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
+ (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* If above loop terminated prematurely, we need to set
+ * remaining banks' start address & size as 0. Otherwise other
+ * u-boot functions and Linux kernel gets wrong values which
+ * could result in crash */
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/mach-mvebu/gpio.c b/arch/arm/mach-mvebu/gpio.c
new file mode 100644
index 0000000..56e54e0
--- /dev/null
+++ b/arch/arm/mach-mvebu/gpio.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+/*
+ * mvebu_config_gpio - GPIO configuration
+ */
+void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
+ u32 gpp0_oe, u32 gpp1_oe)
+{
+ struct kwgpio_registers *gpio0reg =
+ (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ struct kwgpio_registers *gpio1reg =
+ (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+
+ /* Init GPIOS to default values as per board requirement */
+ writel(gpp0_oe_val, &gpio0reg->dout);
+ writel(gpp1_oe_val, &gpio1reg->dout);
+ writel(gpp0_oe, &gpio0reg->oe);
+ writel(gpp1_oe, &gpio1reg->oe);
+}
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
new file mode 100644
index 0000000..9dde710
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for MVEBU platforms
+ */
+
+#ifndef _MVEBU_CONFIG_H
+#define _MVEBU_CONFIG_H
+
+#include <asm/arch/soc.h>
+
+#if defined(CONFIG_ARMADA_XP)
+#define MV88F78X60 /* for the DDR training bin_hdr code */
+#endif
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Add target to build it automatically upon "make" */
+#ifdef CONFIG_SPL
+#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
+#endif
+
+/* end of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS 0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS 0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_PHYLIB
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SYS_I2C_SOFT
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+/* Common SPL configuration */
+#ifndef CONFIG_SPL_LDSCRIPT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds"
+#endif
+
+#endif /* __MVEBU_CONFIG_H */
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
new file mode 100644
index 0000000..3b48460
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MVEBU_CPU_H
+#define _MVEBU_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
+#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
+
+enum memory_bank {
+ BANK0,
+ BANK1,
+ BANK2,
+ BANK3
+};
+
+enum cpu_winen {
+ CPU_WIN_DISABLE,
+ CPU_WIN_ENABLE
+};
+
+enum cpu_target {
+ CPU_TARGET_DRAM = 0x0,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
+ CPU_TARGET_ETH23 = 0x3,
+ CPU_TARGET_PCIE02 = 0x4,
+ CPU_TARGET_ETH01 = 0x7,
+ CPU_TARGET_PCIE13 = 0x8,
+ CPU_TARGET_SASRAM = 0x9,
+ CPU_TARGET_NAND = 0xd,
+};
+
+enum cpu_attrib {
+ CPU_ATTR_SASRAM = 0x01,
+ CPU_ATTR_DRAM_CS0 = 0x0e,
+ CPU_ATTR_DRAM_CS1 = 0x0d,
+ CPU_ATTR_DRAM_CS2 = 0x0b,
+ CPU_ATTR_DRAM_CS3 = 0x07,
+ CPU_ATTR_NANDFLASH = 0x2f,
+ CPU_ATTR_SPIFLASH = 0x1e,
+ CPU_ATTR_BOOTROM = 0x1d,
+ CPU_ATTR_PCIE_IO = 0xe0,
+ CPU_ATTR_PCIE_MEM = 0xe8,
+ CPU_ATTR_DEV_CS0 = 0x3e,
+ CPU_ATTR_DEV_CS1 = 0x3d,
+ CPU_ATTR_DEV_CS2 = 0x3b,
+ CPU_ATTR_DEV_CS3 = 0x37,
+};
+
+enum {
+ MVEBU_SOC_AXP,
+ MVEBU_SOC_A38X,
+ MVEBU_SOC_UNKNOWN,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DEFADR_PCI_MEM 0x90000000
+#define DEFADR_PCI_IO 0xC0000000
+#define DEFADR_SPIF 0xF4000000
+#define DEFADR_BOOTROM 0xF8000000
+
+struct mbus_win {
+ u32 base;
+ u32 size;
+ u8 target;
+ u8 attr;
+};
+
+/*
+ * System registers
+ * Ref: Datasheet sec:A.28
+ */
+struct mvebu_system_registers {
+ u8 pad1[0x60];
+ u32 rstoutn_mask; /* 0x60 */
+ u32 sys_soft_rst; /* 0x64 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct kwgpio_registers {
+ u32 dout;
+ u32 oe;
+ u32 blink_en;
+ u32 din_pol;
+ u32 din;
+ u32 irq_cause;
+ u32 irq_mask;
+ u32 irq_level;
+};
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+/*
+ * functions
+ */
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
+int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
+
+/*
+ * Highspeed SERDES PHY config init, ported from bin_hdr
+ * to mainline U-Boot
+ */
+int serdes_phy_config(void);
+
+/*
+ * DDR3 init / training code ported from Marvell bin_hdr. Now
+ * available in mainline U-Boot in:
+ * drivers/ddr/mvebu/
+ */
+int ddr3_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _MVEBU_CPU_H */
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
new file mode 100644
index 0000000..0a9307c
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for the Marvell's Feroceon CPU core.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MVEBU_SOC_H
+#define _MVEBU_SOC_H
+
+#define SOC_MV78460_ID 0x7846
+#define SOC_88F6810_ID 0x6810
+#define SOC_88F6820_ID 0x6820
+#define SOC_88F6828_ID 0x6828
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID 0x0
+#define MV_88F68XX_A0_ID 0x4
+
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#endif
+
+/* SOC specific definations */
+#define INTREG_BASE 0xd0000000
+#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
+#define SOC_REGS_PHY_BASE 0xf1000000
+#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
+
+#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
+#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
+#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
+#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
+#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
+#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
+#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
+#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
+#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
+#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
+#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
+#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
+#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
+#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
+#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
+#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
+#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
+#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
+#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
+#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
+
+#define SDRAM_MAX_CS 4
+#define SDRAM_ADDR_MASK 0xFF000000
+
+/* MVEBU CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
+
+#endif /* _MVEBU_SOC_H */
diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S b/arch/arm/mach-mvebu/lowlevel_spl.S
new file mode 100644
index 0000000..69da7fe
--- /dev/null
+++ b/arch/arm/mach-mvebu/lowlevel_spl.S
@@ -0,0 +1,61 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+/*
+ * cache_inv - invalidate Cache line
+ * r0 - dest
+ */
+ .global cache_inv
+ .type cache_inv, %function
+ cache_inv:
+
+ stmfd sp!, {r1-r12}
+
+ mcr p15, 0, r0, c7, c6, 1
+
+ ldmfd sp!, {r1-r12}
+ bx lr
+
+
+/*
+ * flush_l1_v6 - l1 cache clean invalidate
+ * r0 - dest
+ */
+ .global flush_l1_v6
+ .type flush_l1_v6, %function
+ flush_l1_v6:
+
+ stmfd sp!, {r1-r12}
+
+ mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
+ mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
+ mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
+
+ ldmfd sp!, {r1-r12}
+ bx lr
+
+
+/*
+ * flush_l1_v7 - l1 cache clean invalidate
+ * r0 - dest
+ */
+ .global flush_l1_v7
+ .type flush_l1_v7, %function
+ flush_l1_v7:
+
+ stmfd sp!, {r1-r12}
+
+ dmb /* @data memory barrier */
+ mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
+ dsb /* @data sync barrier */
+
+ ldmfd sp!, {r1-r12}
+ bx lr
diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
new file mode 100644
index 0000000..9b76bce
--- /dev/null
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -0,0 +1,468 @@
+/*
+ * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
+ * 370/XP, Dove, Orion5x and MV78xx0)
+ *
+ * Ported from the Barebox version to U-Boot by:
+ * Stefan Roese <sr@denx.de>
+ *
+ * The Barebox version is:
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on mbus driver from Linux
+ * (C) Copyright 2008 Marvell Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * The Marvell EBU SoCs have a configurable physical address space:
+ * the physical address at which certain devices (PCIe, NOR, NAND,
+ * etc.) sit can be configured. The configuration takes place through
+ * two sets of registers:
+ *
+ * - One to configure the access of the CPU to the devices. Depending
+ * on the families, there are between 8 and 20 configurable windows,
+ * each can be use to create a physical memory window that maps to a
+ * specific device. Devices are identified by a tuple (target,
+ * attribute).
+ *
+ * - One to configure the access to the CPU to the SDRAM. There are
+ * either 2 (for Dove) or 4 (for other families) windows to map the
+ * SDRAM into the physical address space.
+ *
+ * This driver:
+ *
+ * - Reads out the SDRAM address decoding windows at initialization
+ * time, and fills the mbus_dram_info structure with these
+ * informations. The exported function mv_mbus_dram_info() allow
+ * device drivers to get those informations related to the SDRAM
+ * address decoding windows. This is because devices also have their
+ * own windows (configured through registers that are part of each
+ * device register space), and therefore the drivers for Marvell
+ * devices have to configure those device -> SDRAM windows to ensure
+ * that DMA works properly.
+ *
+ * - Provides an API for platform code or device drivers to
+ * dynamically add or remove address decoding windows for the CPU ->
+ * device accesses. This API is mvebu_mbus_add_window_by_id(),
+ * mvebu_mbus_add_window_remap_by_id() and
+ * mvebu_mbus_del_window().
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#define BIT(nr) (1UL << (nr))
+
+/* DDR target is the same on all platforms */
+#define TARGET_DDR 0
+
+/* CPU Address Decode Windows registers */
+#define WIN_CTRL_OFF 0x0000
+#define WIN_CTRL_ENABLE BIT(0)
+#define WIN_CTRL_TGT_MASK 0xf0
+#define WIN_CTRL_TGT_SHIFT 4
+#define WIN_CTRL_ATTR_MASK 0xff00
+#define WIN_CTRL_ATTR_SHIFT 8
+#define WIN_CTRL_SIZE_MASK 0xffff0000
+#define WIN_CTRL_SIZE_SHIFT 16
+#define WIN_BASE_OFF 0x0004
+#define WIN_BASE_LOW 0xffff0000
+#define WIN_BASE_HIGH 0xf
+#define WIN_REMAP_LO_OFF 0x0008
+#define WIN_REMAP_LOW 0xffff0000
+#define WIN_REMAP_HI_OFF 0x000c
+
+#define ATTR_HW_COHERENCY (0x1 << 4)
+
+#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
+#define DDR_BASE_CS_HIGH_MASK 0xf
+#define DDR_BASE_CS_LOW_MASK 0xff000000
+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
+#define DDR_SIZE_ENABLED BIT(0)
+#define DDR_SIZE_CS_MASK 0x1c
+#define DDR_SIZE_CS_SHIFT 2
+#define DDR_SIZE_MASK 0xff000000
+
+#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
+
+struct mvebu_mbus_state;
+
+struct mvebu_mbus_soc_data {
+ unsigned int num_wins;
+ unsigned int num_remappable_wins;
+ unsigned int (*win_cfg_offset)(const int win);
+ void (*setup_cpu_target)(struct mvebu_mbus_state *s);
+};
+
+struct mvebu_mbus_state mbus_state
+ __attribute__ ((section(".data")));
+static struct mbus_dram_target_info mbus_dram_info
+ __attribute__ ((section(".data")));
+
+/*
+ * Functions to manipulate the address decoding windows
+ */
+
+static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
+ int win, int *enabled, u64 *base,
+ u32 *size, u8 *target, u8 *attr,
+ u64 *remap)
+{
+ void __iomem *addr = mbus->mbuswins_base +
+ mbus->soc->win_cfg_offset(win);
+ u32 basereg = readl(addr + WIN_BASE_OFF);
+ u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
+
+ if (!(ctrlreg & WIN_CTRL_ENABLE)) {
+ *enabled = 0;
+ return;
+ }
+
+ *enabled = 1;
+ *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
+ *base |= (basereg & WIN_BASE_LOW);
+ *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
+
+ if (target)
+ *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
+
+ if (attr)
+ *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
+
+ if (remap) {
+ if (win < mbus->soc->num_remappable_wins) {
+ u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
+ u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
+ *remap = ((u64)remap_hi << 32) | remap_low;
+ } else {
+ *remap = 0;
+ }
+ }
+}
+
+static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
+ int win)
+{
+ void __iomem *addr;
+
+ addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
+
+ writel(0, addr + WIN_BASE_OFF);
+ writel(0, addr + WIN_CTRL_OFF);
+ if (win < mbus->soc->num_remappable_wins) {
+ writel(0, addr + WIN_REMAP_LO_OFF);
+ writel(0, addr + WIN_REMAP_HI_OFF);
+ }
+}
+
+/* Checks whether the given window number is available */
+static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
+ const int win)
+{
+ void __iomem *addr = mbus->mbuswins_base +
+ mbus->soc->win_cfg_offset(win);
+ u32 ctrl = readl(addr + WIN_CTRL_OFF);
+ return !(ctrl & WIN_CTRL_ENABLE);
+}
+
+/*
+ * Checks whether the given (base, base+size) area doesn't overlap an
+ * existing region
+ */
+static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
+ phys_addr_t base, size_t size,
+ u8 target, u8 attr)
+{
+ u64 end = (u64)base + size;
+ int win;
+
+ for (win = 0; win < mbus->soc->num_wins; win++) {
+ u64 wbase, wend;
+ u32 wsize;
+ u8 wtarget, wattr;
+ int enabled;
+
+ mvebu_mbus_read_window(mbus, win,
+ &enabled, &wbase, &wsize,
+ &wtarget, &wattr, NULL);
+
+ if (!enabled)
+ continue;
+
+ wend = wbase + wsize;
+
+ /*
+ * Check if the current window overlaps with the
+ * proposed physical range
+ */
+ if ((u64)base < wend && end > wbase)
+ return 0;
+
+ /*
+ * Check if target/attribute conflicts
+ */
+ if (target == wtarget && attr == wattr)
+ return 0;
+ }
+
+ return 1;
+}
+
+static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
+ phys_addr_t base, size_t size)
+{
+ int win;
+
+ for (win = 0; win < mbus->soc->num_wins; win++) {
+ u64 wbase;
+ u32 wsize;
+ int enabled;
+
+ mvebu_mbus_read_window(mbus, win,
+ &enabled, &wbase, &wsize,
+ NULL, NULL, NULL);
+
+ if (!enabled)
+ continue;
+
+ if (base == wbase && size == wsize)
+ return win;
+ }
+
+ return -ENODEV;
+}
+
+static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
+ int win, phys_addr_t base, size_t size,
+ phys_addr_t remap, u8 target,
+ u8 attr)
+{
+ void __iomem *addr = mbus->mbuswins_base +
+ mbus->soc->win_cfg_offset(win);
+ u32 ctrl, remap_addr;
+
+ ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
+ (attr << WIN_CTRL_ATTR_SHIFT) |
+ (target << WIN_CTRL_TGT_SHIFT) |
+ WIN_CTRL_ENABLE;
+
+ writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
+ writel(ctrl, addr + WIN_CTRL_OFF);
+ if (win < mbus->soc->num_remappable_wins) {
+ if (remap == MVEBU_MBUS_NO_REMAP)
+ remap_addr = base;
+ else
+ remap_addr = remap;
+ writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
+ writel(0, addr + WIN_REMAP_HI_OFF);
+ }
+
+ return 0;
+}
+
+static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap, u8 target,
+ u8 attr)
+{
+ int win;
+
+ if (remap == MVEBU_MBUS_NO_REMAP) {
+ for (win = mbus->soc->num_remappable_wins;
+ win < mbus->soc->num_wins; win++)
+ if (mvebu_mbus_window_is_free(mbus, win))
+ return mvebu_mbus_setup_window(mbus, win, base,
+ size, remap,
+ target, attr);
+ }
+
+
+ for (win = 0; win < mbus->soc->num_wins; win++)
+ if (mvebu_mbus_window_is_free(mbus, win))
+ return mvebu_mbus_setup_window(mbus, win, base, size,
+ remap, target, attr);
+
+ return -ENOMEM;
+}
+
+/*
+ * SoC-specific functions and definitions
+ */
+
+static unsigned int armada_370_xp_mbus_win_offset(int win)
+{
+ /* The register layout is a bit annoying and the below code
+ * tries to cope with it.
+ * - At offset 0x0, there are the registers for the first 8
+ * windows, with 4 registers of 32 bits per window (ctrl,
+ * base, remap low, remap high)
+ * - Then at offset 0x80, there is a hole of 0x10 bytes for
+ * the internal registers base address and internal units
+ * sync barrier register.
+ * - Then at offset 0x90, there the registers for 12
+ * windows, with only 2 registers of 32 bits per window
+ * (ctrl, base).
+ */
+ if (win < 8)
+ return win << 4;
+ else
+ return 0x90 + ((win - 8) << 3);
+}
+
+static unsigned int orion5x_mbus_win_offset(int win)
+{
+ return win << 4;
+}
+
+static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
+{
+ int i;
+ int cs;
+
+ mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+ for (i = 0, cs = 0; i < 4; i++) {
+ u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
+ u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
+
+ /*
+ * We only take care of entries for which the chip
+ * select is enabled, and that don't have high base
+ * address bits set (devices can only access the first
+ * 32 bits of the memory).
+ */
+ if ((size & DDR_SIZE_ENABLED) &&
+ !(base & DDR_BASE_CS_HIGH_MASK)) {
+ struct mbus_dram_window *w;
+
+ w = &mbus_dram_info.cs[cs++];
+ w->cs_index = i;
+ w->mbus_attr = 0xf & ~(1 << i);
+ w->base = base & DDR_BASE_CS_LOW_MASK;
+ w->size = (size | ~DDR_SIZE_MASK) + 1;
+ }
+ }
+ mbus_dram_info.num_cs = cs;
+}
+
+static const struct mvebu_mbus_soc_data
+armada_370_xp_mbus_data __maybe_unused = {
+ .num_wins = 20,
+ .num_remappable_wins = 8,
+ .win_cfg_offset = armada_370_xp_mbus_win_offset,
+ .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
+};
+
+static const struct mvebu_mbus_soc_data
+kirkwood_mbus_data __maybe_unused = {
+ .num_wins = 8,
+ .num_remappable_wins = 4,
+ .win_cfg_offset = orion5x_mbus_win_offset,
+ .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
+};
+
+/*
+ * Public API of the driver
+ */
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
+{
+ return &mbus_dram_info;
+}
+
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap)
+{
+ struct mvebu_mbus_state *s = &mbus_state;
+
+ if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
+ printf("Cannot add window '%x:%x', conflicts with another window\n",
+ target, attribute);
+ return -EINVAL;
+ }
+
+ return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
+}
+
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size)
+{
+ return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+ size, MVEBU_MBUS_NO_REMAP);
+}
+
+int mvebu_mbus_del_window(phys_addr_t base, size_t size)
+{
+ int win;
+
+ win = mvebu_mbus_find_window(&mbus_state, base, size);
+ if (win < 0)
+ return win;
+
+ mvebu_mbus_disable_window(&mbus_state, win);
+ return 0;
+}
+
+int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+ u32 base, u32 size, u8 target, u8 attr)
+{
+ if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
+ printf("Cannot add window '%04x:%04x', conflicts with another window\n",
+ target, attr);
+ return -EBUSY;
+ }
+
+ /*
+ * In U-Boot we first try to add the mbus window to the remap windows.
+ * If this fails, lets try to add the windows to the non-remap windows.
+ */
+ if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
+ if (mvebu_mbus_alloc_window(mbus, base, size,
+ MVEBU_MBUS_NO_REMAP, target, attr))
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+int mvebu_mbus_probe(struct mbus_win windows[], int count)
+{
+ int win;
+ int ret;
+ int i;
+
+#if defined(CONFIG_KIRKWOOD)
+ mbus_state.soc = &kirkwood_mbus_data;
+#endif
+#if defined(CONFIG_ARMADA_XP)
+ mbus_state.soc = &armada_370_xp_mbus_data;
+#endif
+
+ mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
+ mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
+
+ for (win = 0; win < mbus_state.soc->num_wins; win++)
+ mvebu_mbus_disable_window(&mbus_state, win);
+
+ mbus_state.soc->setup_cpu_target(&mbus_state);
+
+ /* Setup statically declared windows in the DT */
+ for (i = 0; i < count; i++) {
+ u32 base, size;
+ u8 target, attr;
+
+ target = windows[i].target;
+ attr = windows[i].attr;
+ base = windows[i].base;
+ size = windows[i].size;
+ ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-mvebu/serdes/Makefile b/arch/arm/mach-mvebu/serdes/Makefile
new file mode 100644
index 0000000..a380fee
--- /dev/null
+++ b/arch/arm/mach-mvebu/serdes/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o
+obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
diff --git a/arch/arm/mach-mvebu/serdes/board_env_spec.h b/arch/arm/mach-mvebu/serdes/board_env_spec.h
new file mode 100644
index 0000000..36e0ed8
--- /dev/null
+++ b/arch/arm/mach-mvebu/serdes/board_env_spec.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BOARD_ENV_SPEC
+#define __BOARD_ENV_SPEC
+
+/* Board specific configuration */
+
+/* KW40 */
+#define MV_6710_DEV_ID 0x6710
+
+#define MV_6710_Z1_REV 0x0
+#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV)
+#define MV_6710_Z1_NAME "MV6710 Z1"
+
+/* Armada XP Family */
+#define MV_78130_DEV_ID 0x7813
+#define MV_78160_DEV_ID 0x7816
+#define MV_78230_DEV_ID 0x7823
+#define MV_78260_DEV_ID 0x7826
+#define MV_78460_DEV_ID 0x7846
+#define MV_78000_DEV_ID 0x7888
+
+#define MV_FPGA_DEV_ID 0x2107
+
+#define MV_78XX0_Z1_REV 0x0
+
+/* boards ID numbers */
+#define BOARD_ID_BASE 0x0
+
+/* New board ID numbers */
+#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
+#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
+#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
+#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
+#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1)
+#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1)
+#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1)
+#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1)
+#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1)
+#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
+#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
+#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
+#define INVALID_BAORD_ID 0xFFFFFFFF
+
+/* Sample at Reset */
+#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
+
+/* BIOS Modes related defines */
+
+#define SAR0_BOOTWIDTH_OFFSET 3
+#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET)
+#define SAR0_BOOTSRC_OFFSET 5
+#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET)
+
+#define SAR0_L2_SIZE_OFFSET 19
+#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET)
+#define SAR0_CPU_FREQ_OFFSET 21
+#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET)
+#define SAR0_FABRIC_FREQ_OFFSET 24
+#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET)
+#define SAR0_CPU0CORE_OFFSET 31
+#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET)
+#define SAR1_CPU0CORE_OFFSET 0
+#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET)
+
+#define PEX_CLK_100MHZ_OFFSET 2
+#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET)
+
+#define SAR1_FABRIC_MODE_OFFSET 19
+#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET)
+#define SAR1_CPU_MODE_OFFSET 20
+#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET)
+
+#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
+
+
+#define CORE_AVS_CONTROL_0REG 0x18300
+#define CORE_AVS_CONTROL_2REG 0x18308
+#define CPU_AVS_CONTROL2_REG 0x20868
+#define CPU_AVS_CONTROL0_REG 0x20860
+#define GENERAL_PURPOSE_RESERVED0_REG 0x182E0
+
+#define MSAR_TCLK_OFFS 28
+#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
+
+
+/* Controler environment registers offsets */
+#define GEN_PURP_RES_1_REG 0x182F4
+#define GEN_PURP_RES_2_REG 0x182F8
+
+/* registers offsets */
+#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40))
+#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
+#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit))
+#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0)
+
+#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
+#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */
+#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
+#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08)
+#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C)
+#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
+#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14)
+#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18)
+#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C)
+#define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40))
+#define GPP_64_66_DATA_OUT_SET_REG 0x181A4
+#define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40))
+#define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0
+#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40)
+
+#define MV_GPP66 (1 << 2)
+
+/* Relevant for MV78XX0 */
+#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20)
+#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24)
+
+/* This define describes the maximum number of supported PEX Interfaces */
+#define MV_PEX_MAX_IF 10
+#define MV_PEX_MAX_UNIT 4
+
+#define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12)))
+
+#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \
+ ((unit)/2 * 0x2000) + 0x1B00)
+
+#define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000)
+
+#define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804)
+#define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C)
+#define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918)
+#define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920)
+#define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058)
+#define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C)
+#define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810)
+#define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834)
+#define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838)
+#define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C)
+#define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840)
+
+#define MV_ETH_BASE_ADDR (0x72000)
+#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \
+ 0x40000 + ((port) % 2) * 0x4000)
+#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
+
+
+#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
+#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
+#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
+#define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0)
+#define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4)
+#define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20)
+#define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38)
+#define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0)
+
+#define SERDES_LINE_MUX_REG_0_7 0x18270
+#define SERDES_LINE_MUX_REG_8_15 0x18274
+#define QSGMII_CONTROL_1_REG 0x18404
+
+/* SOC_CTRL_REG fields */
+#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3)
+#define SCR_PEX_ENA_MASK(pex) (1 << pex)
+
+#define PCIE0_QUADX1_EN (1<<7)
+#define PCIE1_QUADX1_EN (1<<8)
+
+#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7)
+#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex))
+
+#define PCIE1_CLK_OUT_EN_OFF 5
+#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF)
+
+#define PCIE0_CLK_OUT_EN_OFF 4
+#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF)
+
+#define SCR_PEX0_4BY1_OFFS 7
+#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS)
+
+#define SCR_PEX1_4BY1_OFFS 8
+#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
+
+
+#define MV_MISC_REGS_OFFSET (0x18200)
+#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
+#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
+
+/*
+ * PCI Express Control and Status Registers
+ */
+#define MAX_PEX_DEVICES 32
+#define MAX_PEX_FUNCS 8
+#define MAX_PEX_BUSSES 256
+
+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
+
+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
+
+#define PXSR_DL_DOWN 0x1 /* DL_Down indication. */
+#define PXCAR_CONFIG_EN (1 << 31)
+#define PEX_STATUS_AND_COMMAND 0x004
+#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */
+
+/* PCI Express Configuration Address Register */
+
+/* PEX_CFG_ADDR_REG (PXCAR) */
+#define PXCAR_REG_NUM_OFFS 2
+#define PXCAR_REG_NUM_MAX 0x3F
+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
+#define PXCAR_FUNC_NUM_OFFS 8
+#define PXCAR_FUNC_NUM_MAX 0x7
+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
+#define PXCAR_DEVICE_NUM_OFFS 11
+#define PXCAR_DEVICE_NUM_MAX 0x1F
+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
+#define PXCAR_BUS_NUM_OFFS 16
+#define PXCAR_BUS_NUM_MAX 0xFF
+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
+#define PXCAR_EXT_REG_NUM_OFFS 24
+#define PXCAR_EXT_REG_NUM_MAX 0xF
+
+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
+
+
+#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
+#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
+#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
+#define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90)
+#define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00)
+#define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04)
+#define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10)
+#define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18)
+#define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20)
+#define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30)
+#define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C)
+#define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50)
+#define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60)
+#define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64)
+
+#define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */
+#define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS)
+#define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS)
+#define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS)
+
+#define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8)
+#define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC)
+#define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900)
+
+#define PEX_CAPABILITY_REG 0x60
+#define PEX_DEV_CAPABILITY_REG 0x64
+#define PEX_DEV_CTRL_STAT_REG 0x68
+#define PEX_LINK_CAPABILITY_REG 0x6C
+#define PEX_LINK_CTRL_STAT_REG 0x70
+#define PEX_LINK_CTRL_STAT_2_REG 0x90
+
+#endif /* __BOARD_ENV_SPEC */
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
new file mode 100644
index 0000000..702273a
--- /dev/null
+++ b/arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
@@ -0,0 +1,1572 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "high_speed_env_spec.h"
+#include "board_env_spec.h"
+
+#define SERDES_VERION "2.1.5"
+#define ENDED_OK "High speed PHY - Ended Successfully\n"
+
+static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
+
+extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
+
+extern u8 rd78460gp_twsi_dev[];
+extern u8 db88f78xx0rev2_twsi_dev[];
+
+u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
+int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
+int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
+
+#define MV_BOARD_PEX_MODULE_ADDR 0x23
+#define MV_BOARD_PEX_MODULE_ID 1
+#define MV_BOARD_ETM_MODULE_ID 2
+
+#define PEX_MODULE_DETECT 1
+#define ETM_MODULE_DETECT 2
+
+#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
+#define PEX_CAPABILITY_GET(satr) (satr & 1)
+#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
+
+/* Static parametes */
+static int config_module;
+static int switch_module;
+
+/* Local function */
+static u32 board_id_get(void)
+{
+#if defined(CONFIG_DB_88F78X60)
+ return DB_88F78XX0_BP_ID;
+#elif defined(CONFIG_RD_88F78460_SERVER)
+ return RD_78460_SERVER_ID;
+#elif defined(CONFIG_RD_78460_SERVER_REV2)
+ return RD_78460_SERVER_REV2_ID;
+#elif defined(CONFIG_DB_78X60_PCAC)
+ return DB_78X60_PCAC_ID;
+#elif defined(CONFIG_DB_88F78X60_REV2)
+ return DB_88F78XX0_BP_REV2_ID;
+#elif defined(CONFIG_RD_78460_NAS)
+ return RD_78460_NAS_ID;
+#elif defined(CONFIG_DB_78X60_AMC)
+ return DB_78X60_AMC_ID;
+#elif defined(CONFIG_DB_78X60_PCAC_REV2)
+ return DB_78X60_PCAC_REV2_ID;
+#elif defined(CONFIG_DB_784MP_GP)
+ return DB_784MP_GP_ID;
+#elif defined(CONFIG_RD_78460_CUSTOMER)
+ return RD_78460_CUSTOMER_ID;
+#else
+ /*
+ * Return 0 here for custom board as this should not be used
+ * for custom boards.
+ */
+ return 0;
+#endif
+}
+
+static u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ u8 data;
+ u8 *dev;
+ u32 board_id = board_id_get();
+ int ret;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ switch (board_id) {
+ case DB_784MP_GP_ID:
+ dev = rd78460gp_twsi_dev;
+
+ break;
+ case DB_88F78XX0_BP_ID:
+ case DB_88F78XX0_BP_REV2_ID:
+ dev = db88f78xx0rev2_twsi_dev;
+ break;
+
+ case DB_78X60_PCAC_ID:
+ case FPGA_88F78XX0_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_SERVER_REV2_ID:
+ default:
+ return 0;
+ }
+
+ /* Read MPP module ID */
+ ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
+ if (ret)
+ return MV_ERROR;
+
+ return data;
+}
+
+static int board_modules_scan(void)
+{
+ u8 val;
+ u32 board_id = board_id_get();
+ int ret;
+
+ /* Perform scan only for DB board */
+ if ((board_id == DB_88F78XX0_BP_ID) ||
+ (board_id == DB_88F78XX0_BP_REV2_ID)) {
+ /* reset modules flags */
+ config_module = 0;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* SERDES module (only PEX model is supported now) */
+ ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
+ if (ret)
+ return MV_ERROR;
+
+ if (val == MV_BOARD_PEX_MODULE_ID)
+ config_module = PEX_MODULE_DETECT;
+ if (val == MV_BOARD_ETM_MODULE_ID)
+ config_module = ETM_MODULE_DETECT;
+ } else if (board_id == RD_78460_NAS_ID) {
+ switch_module = 0;
+ if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
+ switch_module = 1;
+ }
+
+ return MV_OK;
+}
+
+u32 pex_max_unit_get(void)
+{
+ /*
+ * TODO:
+ * Right now only MV78460 is supported. Other SoC's might need
+ * a different value here.
+ */
+ return MV_PEX_MAX_UNIT;
+}
+
+u32 pex_max_if_get(void)
+{
+ /*
+ * TODO:
+ * Right now only MV78460 is supported. Other SoC's might need
+ * a different value here.
+ */
+ return MV_PEX_MAX_IF;
+}
+
+u8 board_cpu_freq_get(void)
+{
+ u32 sar;
+ u32 sar_msb;
+
+ sar = reg_read(MPP_SAMPLE_AT_RESET(0));
+ sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
+ return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
+}
+
+__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ u32 board_id;
+ u32 serdes_cfg_val = 0; /* default */
+
+ board_id = board_id_get();
+
+ switch (board_id) {
+ case DB_784MP_GP_ID:
+ serdes_cfg_val = 0;
+ break;
+ }
+
+ return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
+}
+
+u16 ctrl_model_get(void)
+{
+ /* Right now only MV78460 supported */
+ return MV_78460_DEV_ID;
+}
+
+u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
+{
+ if (line_num < 8)
+ return (info->line0_7 >> (line_num << 2)) & 0xF;
+ else
+ return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
+}
+
+int serdes_phy_config(void)
+{
+ int status = MV_OK;
+ u32 line_cfg;
+ u8 line_num;
+ /* addr/value for each line @ every setup step */
+ u32 addr[16][11], val[16][11];
+ u8 pex_unit, pex_line_num;
+ u8 sgmii_port = 0;
+ u32 tmp;
+ u32 in_direct;
+ u8 max_serdes_lines;
+ MV_BIN_SERDES_CFG *info;
+ u8 satr11;
+ u8 sata_port;
+ u8 freq;
+ u8 device_rev;
+ u32 rx_high_imp_mode;
+ u16 ctrl_mode;
+ u32 board_id = board_id_get();
+ u32 pex_if;
+ u32 pex_if_num;
+
+ /*
+ * TODO:
+ * Right now we only support the MV78460 with 16 serdes lines
+ */
+ max_serdes_lines = 16;
+ if (max_serdes_lines == 0)
+ return MV_OK;
+
+ switch (board_id) {
+ case DB_78X60_AMC_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_CUSTOMER_ID:
+ case RD_78460_SERVER_ID:
+ case RD_78460_SERVER_REV2_ID:
+ case DB_78X60_PCAC_ID:
+ satr11 = (0x1 << 1) | 1;
+ break;
+ case FPGA_88F78XX0_ID:
+ case RD_78460_NAS_ID:
+ satr11 = (0x0 << 1) | 1;
+ break;
+ case DB_88F78XX0_BP_REV2_ID:
+ case DB_784MP_GP_ID:
+ case DB_88F78XX0_BP_ID:
+ satr11 = board_sat_r_get(1, 1);
+ if ((u8) MV_ERROR == (u8) satr11)
+ return MV_ERROR;
+ break;
+ }
+
+ board_modules_scan();
+ memset(addr, 0, sizeof(addr));
+ memset(val, 0, sizeof(val));
+
+ /* Check if DRAM is already initialized */
+ if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
+ (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
+ DEBUG_INIT_S("High speed PHY - Version: ");
+ DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(" - 2nd boot - Skip\n");
+ return MV_OK;
+ }
+ DEBUG_INIT_S("High speed PHY - Version: ");
+ DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(" (COM-PHY-V20)\n");
+
+ /*
+ * AVS : disable AVS for frequency less than 1333
+ */
+ freq = board_cpu_freq_get();
+ device_rev = mv_ctrl_rev_get();
+
+ if (device_rev == 2) { /* for B0 only */
+ u32 cpu_avs;
+ u8 fabric_freq;
+ cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
+ DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
+ cpu_avs &= ~(1 << 9);
+
+ if ((0x4 == freq) || (0xB == freq)) {
+ u32 tmp2;
+
+ tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
+ DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
+ /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
+ tmp2 |= 0x0FF;
+ reg_write(CPU_AVS_CONTROL0_REG, tmp2);
+ DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
+ cpu_avs |= (1 << 9); /* cpu avs enable */
+ cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
+ fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
+ SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
+ if ((0xB == freq) && (5 == fabric_freq)) {
+ u32 core_avs;
+
+ core_avs = reg_read(CORE_AVS_CONTROL_0REG);
+ DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
+
+ /*
+ * Set core lower limit = 0.9V &
+ * core upper limit = 0.9125V
+ */
+ core_avs &= ~(0xff);
+ core_avs |= 0x0E;
+ reg_write(CORE_AVS_CONTROL_0REG, core_avs);
+ DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
+
+ core_avs = reg_read(CORE_AVS_CONTROL_2REG);
+ DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
+ core_avs |= (1 << 9); /* core AVS enable */
+ reg_write(CORE_AVS_CONTROL_2REG, core_avs);
+ DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
+
+ tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
+ DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
+ tmp2);
+ tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
+ reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
+ DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
+ tmp2);
+ }
+ }
+ reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
+ DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
+ }
+
+ info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
+ DEBUG_INIT_FULL_S("info->line0_7= 0x");
+ DEBUG_INIT_FULL_D(info->line0_7, 8);
+ DEBUG_INIT_FULL_S(" info->line8_15= 0x");
+ DEBUG_INIT_FULL_D(info->line8_15, 8);
+ DEBUG_INIT_FULL_S("\n");
+
+ if (info == NULL) {
+ DEBUG_INIT_S("Hight speed PHY Error #1\n");
+ return MV_ERROR;
+ }
+
+ if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
+ DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
+ reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
+ info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
+ mdelay(100);
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
+ }
+
+ /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
+ DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /* 1. GLOB_CLK_CTRL Reset and Clock Control */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
+
+ /* 2. GLOB_TEST_CTRL Test Mode Control */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC2 << 16) | 0x200);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC2 << 16) | 0x200);
+ }
+
+ /* 3. GLOB_CLK_SRC_LO Clock Source Low */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC3 << 16) | 0x0F);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC3 << 16) | 0x0F);
+ }
+
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC5 << 16) | 0x11F);
+ }
+
+ /*
+ * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
+ * PU_RX,PU_TX. (bits[12:5])
+ */
+ DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ switch (line_num) {
+ case 4:
+ case 6:
+ sata_port = 0;
+ break;
+ case 5:
+ sata_port = 1;
+ break;
+ default:
+ DEBUG_INIT_C
+ ("SATA port error for serdes line: ",
+ line_num, 2);
+ return MV_ERROR;
+ }
+ tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
+ (0x11 << 5) : 0x0;
+
+ reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /*
+ * 4) Configure the desire PIN_PHY_GEN and do power
+ * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
+ */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= 0x660;
+ reg_write(SGMII_SERDES_CFG_REG(0), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
+ (0x88 << 5) : (0x66 << 5));
+ reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ }
+
+ /* Step 3 - QSGMII enable */
+ DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /* QSGMII Active bit set to true */
+ tmp = reg_read(QSGMII_CONTROL_1_REG);
+ DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
+ tmp |= (1 << 30);
+#ifdef ERRATA_GL_6572255
+ tmp |= (1 << 27);
+#endif
+ reg_write(QSGMII_CONTROL_1_REG, tmp);
+ DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
+ }
+ }
+
+ /* Step 4 - configure SERDES MUXes */
+ DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
+ if (config_module & ETM_MODULE_DETECT) {
+ reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
+ } else {
+ reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
+ }
+ reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
+
+ /* Step 5: Activate the RX High Impedance Mode */
+ DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
+ rx_high_imp_mode = 0x8080;
+ if (device_rev == 2) /* for B0 only */
+ rx_high_imp_mode |= 4;
+
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+ DEBUG_INIT_FULL_S("SERDES ");
+ DEBUG_INIT_FULL_D_10(line_num, 2);
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
+ DEBUG_INIT_FULL_S(" unconnected ***\n");
+ continue;
+ }
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ DEBUG_INIT_FULL_S(" - PEX unit ");
+ DEBUG_INIT_FULL_D_10(pex_unit, 1);
+ DEBUG_INIT_FULL_S(" line= ");
+ DEBUG_INIT_FULL_D_10(pex_line_num, 1);
+ DEBUG_INIT_FULL_S("\n");
+
+ /* Needed for PEX_PHY_ACCESS_REG macro */
+ if ((line_num > 7) &&
+ (info->pex_mode[3] == PEX_BUS_MODE_X8))
+ /* lines 8 - 15 are belong to PEX3 in x8 mode */
+ pex_unit = 3;
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /*
+ * 8) Activate the RX High Impedance Mode field
+ * (bit [2]) in register /PCIe_USB Control (Each MAC
+ * contain different Access to reach its
+ * Serdes-Regfile).
+ * [PEX-Only] Set bit[12]: The analog part latches idle
+ * if PU_TX = 1 and PU_PLL =1.
+ */
+
+ /* Termination enable */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
+ in_direct = (0x48 << 16) | (pex_line_num << 24) |
+ 0x1000 | rx_high_imp_mode; /* x1 */
+ } else if ((info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4) && (pex_line_num == 0))
+ in_direct = (0x48 << 16) | (pex_line_num << 24) |
+ 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
+ else
+ in_direct = 0;
+
+ if (in_direct) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ in_direct);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ in_direct);
+ }
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * port 0 for serdes lines 4,6, and port 1 for
+ * serdes lines 5
+ */
+ sata_port = line_num & 1;
+ DEBUG_INIT_FULL_S(" - SATA port ");
+ DEBUG_INIT_FULL_D_10(sata_port, 2);
+ DEBUG_INIT_FULL_S("\n");
+ reg_write(SATA_COMPHY_CTRL_REG(sata_port),
+ rx_high_imp_mode);
+ DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
+ rx_high_imp_mode);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ DEBUG_INIT_FULL_S(" - QSGMII\n");
+ reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
+ DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
+ rx_high_imp_mode);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+ DEBUG_INIT_FULL_S(" - SGMII port ");
+ DEBUG_INIT_FULL_D_10(sgmii_port, 2);
+ DEBUG_INIT_FULL_S("\n");
+ reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
+ DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
+ rx_high_imp_mode);
+ } /* for each serdes lane */
+
+ /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
+ DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
+ tmp = reg_read(SOC_CTRL_REG);
+ DEBUG_RD_REG(SOC_CTRL_REG, tmp);
+ tmp &= 0x200;
+ if (info->pex_mode[0] == PEX_BUS_MODE_X1)
+ tmp |= PCIE0_QUADX1_EN;
+ if (info->pex_mode[1] == PEX_BUS_MODE_X1)
+ tmp |= PCIE1_QUADX1_EN;
+ if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
+ PEX_CLK_100MHZ_OFFSET) == 0x1)
+ tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
+
+ reg_write(SOC_CTRL_REG, tmp);
+ DEBUG_WR_REG(SOC_CTRL_REG, tmp);
+
+ /* 6.2 PCI Express Link Capabilities */
+ DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
+
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ /*
+ * PCI Express Control
+ * 0xX1A00 [0]:
+ * 0x0 X4-Link.
+ * 0x1 X1-Link
+ */
+ pex_unit = line_num >> 2;
+ pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /* set Common Clock Configuration */
+ tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
+ DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+ tmp |= (1 << 6);
+ reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+ DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+
+ tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
+ DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+ tmp &= ~(0x3FF);
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
+ tmp |= (0x1 << 4);
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
+ tmp |= (0x4 << 4);
+ if (0 == PEX_CAPABILITY_GET(satr11))
+ tmp |= 0x1;
+ else
+ tmp |= 0x2;
+ DEBUG_INIT_FULL_S("Step 6.2: PEX ");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
+ reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+ DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+
+ /*
+ * If pex is X4, no need to pass thru the other
+ * 3X1 serdes lines
+ */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
+ line_num += 3;
+ }
+ }
+
+ /*
+ * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
+ * need to config the register SOC_Misc/General Purpose2
+ * (Address= 182F8)
+ */
+ DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
+ tmp = reg_read(GEN_PURP_RES_2_REG);
+ DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
+
+ tmp &= 0xFFFF0000;
+ if (info->pex_mode[0] == PEX_BUS_MODE_X4)
+ tmp |= 0x0000000F;
+
+ if (info->pex_mode[1] == PEX_BUS_MODE_X4)
+ tmp |= 0x000000F0;
+
+ if (info->pex_mode[2] == PEX_BUS_MODE_X4)
+ tmp |= 0x00000F00;
+
+ if (info->pex_mode[3] == PEX_BUS_MODE_X4)
+ tmp |= 0x0000F000;
+
+ reg_write(GEN_PURP_RES_2_REG, tmp);
+ DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
+
+ /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
+ DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
+
+ /* Prepare PHY parameters for each step according to MUX selection */
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5])
+ * and REF_FREF_SEL (bits[4:0]) in the register Power
+ * and PLL Control (Each MAC contain different Access
+ * to reach its Serdes-Regfile).
+ */
+ if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
+ (0 == pex_line_num))
+ || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x01 << 16) | (pex_line_num << 24) |
+ 0xFC60);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x01 << 16) | (pex_line_num << 24)
+ | 0xFC60);
+ /*
+ * Step 8.1: [PEX-Only] Configure Max PLL Rate
+ * (bit 8 in KVCO Calibration Control and
+ * bits[10:9] in
+ */
+ /* Use Maximum PLL Rate(Bit 8) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x02 << 16) | (1 << 31) |
+ (pex_line_num << 24)); /* read command */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x02 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ tmp &= ~(1 << 31);
+ tmp |= (1 << 8);
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+
+ /* Use Maximum PLL Rate(Bits [10:9]) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x81 << 16) | (1 << 31) |
+ (pex_line_num << 24)); /* read command */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x81 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ tmp &= ~(1 << 31);
+ tmp |= (3 << 9);
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ }
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * Port 0 for serdes lines 4,6, and port 1 for serdes
+ * lines 5
+ */
+ sata_port = line_num & 1;
+
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5]) and
+ * REF_FREF_SEL (bits[4:0]) in the register Power
+ * and PLL Control (Each MAC contain different Access
+ * to reach its Serdes-Regfile).
+ */
+ reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
+ DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
+
+ /* 9) Configure the desire SEL_BITS */
+ reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
+ DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
+
+ /* 10) Configure the desire REFCLK_SEL */
+
+ reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
+ DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ tmp |= 7;
+ reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5])
+ * and REF_FREF_SEL (bits[4:0]) in the register
+ */
+ reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
+ DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
+
+ /*
+ * 9) Configure the desire SEL_BITS (bits [11:0]
+ * in register
+ */
+ reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
+ DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
+
+ /*
+ * 10) Configure the desire REFCLK_SEL (bit [10])
+ * in register
+ */
+ reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
+ DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ tmp |= 7;
+ reg_write(SGMII_SERDES_CFG_REG(0), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5]) and
+ * REF_FREF_SEL (bits[4:0]) in the register
+ */
+ reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
+ DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
+
+ /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
+ reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
+ DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
+
+ /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
+ reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
+ DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ tmp |= 7;
+ reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+
+ } /* for each serdes lane */
+
+ /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
+ DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ if (0 == pex_line_num) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC1 << 16) | 0x24);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC1 << 16) | 0x24);
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------*/
+ /* Step 13: Wait 15ms before checking results */
+ DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
+ mdelay(15);
+ tmp = 20;
+ while (tmp) {
+ status = MV_OK;
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ u32 tmp;
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * Port 0 for serdes lines 4,6, and port 1
+ * for serdes lines 5
+ */
+ sata_port = line_num & 1;
+
+ tmp =
+ reg_read(SATA_LP_PHY_EXT_STAT_REG
+ (sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
+ (sata_port), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ continue;
+ }
+
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ tmp = reg_read(SGMII_SERDES_STAT_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ continue;
+ }
+
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ }
+
+ if (status == MV_OK)
+ break;
+ mdelay(5);
+ tmp--;
+ }
+
+ /*
+ * Step14 [PEX-Only] In order to configure RC/EP mode please write
+ * to register 0x0060 bits
+ */
+ DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ tmp =
+ reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
+ DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ tmp &= ~(0xf << 20);
+ if (info->pex_type == MV_PEX_ROOT_COMPLEX)
+ tmp |= (0x4 << 20);
+ else
+ tmp |= (0x1 << 20);
+ reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ }
+
+ /*
+ * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
+ * register 0x1a60
+ */
+ DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ if (info->pex_type == MV_PEX_END_POINT) {
+ tmp =
+ reg_read(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)));
+ DEBUG_RD_REG(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
+ tmp &= 0xfff6ffff;
+ reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ DEBUG_WR_REG(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
+ }
+ }
+
+ if (info->serdes_m_phy_change) {
+ MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
+ u32 bus_speed;
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+ serdes_m_phy_change = info->serdes_m_phy_change;
+ bus_speed = info->bus_speed & (1 << line_num);
+ while (serdes_m_phy_change->type !=
+ SERDES_UNIT_UNCONNECTED) {
+ switch (serdes_m_phy_change->type) {
+ case SERDES_UNIT_PEX:
+ if (line_cfg != SERDES_UNIT_PEX)
+ break;
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ if (info->pex_mode[pex_unit] ==
+ PEX_BUS_DISABLED)
+ break;
+ if ((info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4) && pex_line_num)
+ break;
+
+ if (bus_speed) {
+ reg_write(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num << 24) |
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num <<
+ 24) |
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num << 24) |
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num <<
+ 24) |
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_SATA:
+ if (line_cfg != SERDES_UNIT_SATA)
+ break;
+ /*
+ * Port 0 for serdes lines 4,6, and
+ * port 1 for serdes lines 5
+ */
+ sata_port = line_num & 1;
+ if (bus_speed) {
+ reg_write(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_SGMII0:
+ case SERDES_UNIT_SGMII1:
+ case SERDES_UNIT_SGMII2:
+ case SERDES_UNIT_SGMII3:
+ if (line_cfg == serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ break;
+ if (bus_speed) {
+ reg_write(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_QSGMII:
+ if (line_cfg != SERDES_UNIT_QSGMII)
+ break;
+ if (bus_speed) {
+ reg_write
+ (serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG
+ (serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write
+ (serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG
+ (serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ default:
+ break;
+ }
+ serdes_m_phy_change++;
+ }
+ }
+ }
+
+ /* Step 16 [PEX-Only] Training Enable */
+ DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
+ tmp = reg_read(SOC_CTRL_REG);
+ DEBUG_RD_REG(SOC_CTRL_REG, tmp);
+ tmp &= ~(0x0F);
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ reg_write(PEX_CAUSE_REG(pex_unit), 0);
+ DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
+ if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
+ tmp |= (0x1 << pex_unit);
+ }
+ reg_write(SOC_CTRL_REG, tmp);
+ DEBUG_WR_REG(SOC_CTRL_REG, tmp);
+
+ /* Step 17: Speed change to target speed and width */
+ {
+ u32 tmp_reg, tmp_pex_reg;
+ u32 addr;
+ u32 first_busno, next_busno;
+ u32 max_link_width = 0;
+ u32 neg_link_width = 0;
+ pex_if_num = pex_max_if_get();
+ mdelay(150);
+ DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
+ next_busno = 0;
+ for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
+ line_num = (pex_if <= 8) ? pex_if : 12;
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+ pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
+ DEBUG_INIT_FULL_S("step 17: PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
+ DEBUG_INIT_FULL_C("PEX disabled interface ",
+ pex_if, 1);
+ if (pex_if < 8)
+ pex_if += 3;
+ continue;
+ }
+ first_busno = next_busno;
+ if ((info->pex_type == MV_PEX_END_POINT) &&
+ (0 == pex_if)) {
+ if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4))
+ pex_if += 3;
+ continue;
+ }
+
+ tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
+ DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
+ if ((tmp & 0x7f) == 0x7e) {
+ next_busno++;
+ tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
+ max_link_width = tmp;
+ DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
+ (pex_if)), tmp);
+ max_link_width = ((max_link_width >> 4) & 0x3F);
+ neg_link_width =
+ reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
+ DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
+ neg_link_width);
+ neg_link_width = ((neg_link_width >> 20) & 0x3F);
+ if (max_link_width > neg_link_width) {
+ tmp &= ~(0x3F << 4);
+ tmp |= (neg_link_width << 4);
+ reg_write(PEX_LINK_CAPABILITIES_REG
+ (pex_if), tmp);
+ DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
+ (pex_if)), tmp);
+ mdelay(1); /* wait 1ms before reading capability for speed */
+ DEBUG_INIT_S("PEX");
+ DEBUG_INIT_D(pex_if, 1);
+ DEBUG_INIT_C(": change width to X",
+ neg_link_width, 1);
+ }
+ tmp_pex_reg =
+ reg_read((PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CAPABILITY_REG)));
+ DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CAPABILITY_REG)),
+ tmp_pex_reg);
+ tmp_pex_reg &= (0xF);
+ if (tmp_pex_reg == 0x2) {
+ tmp_reg =
+ (reg_read
+ (PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CTRL_STAT_REG)) &
+ 0xF0000) >> 16;
+ DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CTRL_STAT_REG),
+ tmp_pex_reg);
+ /* check if the link established is GEN1 */
+ if (tmp_reg == 0x1) {
+ pex_local_bus_num_set(pex_if,
+ first_busno);
+ pex_local_dev_num_set(pex_if,
+ 1);
+
+ DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
+ /* link is Gen1, check the EP capability */
+ addr =
+ pex_cfg_read(pex_if,
+ first_busno, 0,
+ 0,
+ 0x34) & 0xFF;
+ DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
+ addr, 4);
+ if (addr == 0xff) {
+ DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
+ pex_if, 1);
+ continue;
+ }
+ while ((pex_cfg_read
+ (pex_if, first_busno, 0,
+ 0,
+ addr) & 0xFF) !=
+ 0x10) {
+ addr =
+ (pex_cfg_read
+ (pex_if,
+ first_busno, 0, 0,
+ addr) & 0xFF00) >>
+ 8;
+ }
+ if ((pex_cfg_read
+ (pex_if, first_busno, 0, 0,
+ addr + 0xC) & 0xF) >=
+ 0x2) {
+ tmp =
+ reg_read
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if));
+ DEBUG_RD_REG
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+ tmp &= ~(0x1 | 1 << 1);
+ tmp |= (1 << 1);
+ reg_write
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+ DEBUG_WR_REG
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+
+ tmp =
+ reg_read
+ (PEX_CTRL_REG
+ (pex_if));
+ DEBUG_RD_REG
+ (PEX_CTRL_REG
+ (pex_if), tmp);
+ tmp |= (1 << 10);
+ reg_write(PEX_CTRL_REG
+ (pex_if),
+ tmp);
+ DEBUG_WR_REG
+ (PEX_CTRL_REG
+ (pex_if), tmp);
+ mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
+ DEBUG_INIT_FULL_S
+ ("Gen2 client!\n");
+ } else {
+ DEBUG_INIT_FULL_S
+ ("GEN1 client!\n");
+ }
+ }
+ }
+ } else {
+ DEBUG_INIT_FULL_S("PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
+ DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
+ 8);
+ DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
+ }
+
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ }
+ }
+
+ /* Step 18: update pex DEVICE ID */
+ {
+ u32 devId;
+ pex_if_num = pex_max_if_get();
+ ctrl_mode = ctrl_model_get();
+ for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
+ pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ continue;
+ }
+
+ devId = reg_read(PEX_CFG_DIRECT_ACCESS(
+ pex_if, PEX_DEVICE_AND_VENDOR_ID));
+ devId &= 0xFFFF;
+ devId |= ((ctrl_mode << 16) & 0xffff0000);
+ DEBUG_INIT_S("Update Device ID PEX");
+ DEBUG_INIT_D(pex_if, 1);
+ DEBUG_INIT_D(devId, 8);
+ DEBUG_INIT_S("\n");
+ reg_write(PEX_CFG_DIRECT_ACCESS
+ (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ }
+ DEBUG_INIT_S("Update PEX Device ID 0x");
+ DEBUG_INIT_D(ctrl_mode, 4);
+ DEBUG_INIT_S("0\n");
+ }
+ tmp = reg_read(PEX_DBG_STATUS_REG(0));
+ DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
+
+ DEBUG_INIT_S(ENDED_OK);
+ return MV_OK;
+}
+
+/* PEX configuration space read write */
+
+/*
+ * pex_cfg_read - Read from configuration space
+ *
+ * DESCRIPTION:
+ * This function performs a 32 bit read from PEX configuration space.
+ * It supports both type 0 and type 1 of Configuration Transactions
+ * (local and over bridge). In order to read from local bus segment, use
+ * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
+ * will result configuration transaction of type 1 (over bridge).
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * bus - PEX segment bus number.
+ * dev - PEX device number.
+ * func - Function number.
+ * offss - Register offset.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * 32bit register data, 0xffffffff on error
+ *
+ */
+u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
+{
+ u32 pex_data = 0;
+ u32 local_dev, local_bus;
+ u32 val;
+
+ if (pex_if >= MV_PEX_MAX_IF)
+ return 0xFFFFFFFF;
+
+ if (dev >= MAX_PEX_DEVICES) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
+ 1);
+ return 0xFFFFFFFF;
+ }
+
+ if (func >= MAX_PEX_FUNCS) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
+ 1);
+ return 0xFFFFFFFF;
+ }
+
+ if (bus >= MAX_PEX_BUSSES) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
+ return MV_ERROR;
+ }
+ val = reg_read(PEX_STATUS_REG(pex_if));
+
+ local_dev =
+ ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
+ local_bus =
+ ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
+
+ /* Speed up the process. In case on no link, return MV_ERROR */
+ if ((dev != local_dev) || (bus != local_bus)) {
+ pex_data = reg_read(PEX_STATUS_REG(pex_if));
+
+ if ((pex_data & PXSR_DL_DOWN))
+ return MV_ERROR;
+ }
+
+ /*
+ * In PCI Express we have only one device number
+ * and this number is the first number we encounter else that the
+ * local_dev spec pex define return on config read/write on any device
+ */
+ if (bus == local_bus) {
+ if (local_dev == 0) {
+ /*
+ * If local dev is 0 then the first number we encounter
+ * after 0 is 1
+ */
+ if ((dev != 1) && (dev != local_dev))
+ return MV_ERROR;
+ } else {
+ /*
+ * If local dev is not 0 then the first number we
+ * encounter is 0
+ */
+ if ((dev != 0) && (dev != local_dev))
+ return MV_ERROR;
+ }
+ }
+
+ /* Creating PEX address to be passed */
+ pex_data = (bus << PXCAR_BUS_NUM_OFFS);
+ pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
+ pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
+ pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
+ /* extended register space */
+ pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
+
+ pex_data |= PXCAR_CONFIG_EN;
+
+ /* Write the address to the PEX configuration address register */
+ reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
+
+ /*
+ * In order to let the PEX controller absorbed the address of the read
+ * transaction we perform a validity check that the address was written
+ */
+ if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
+ return MV_ERROR;
+
+ /* cleaning Master Abort */
+ reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
+ PXSAC_MABORT);
+ /* Read the Data returned in the PEX Data register */
+ pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
+
+ DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
+
+ return pex_data;
+}
+
+/*
+ * pex_local_bus_num_set - Set PEX interface local bus number.
+ *
+ * DESCRIPTION:
+ * This function sets given PEX interface its local bus number.
+ * Note: In case the PEX interface is PEX-X, the information is read-only.
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * bus_num - Bus number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * MV_NOT_ALLOWED in case PEX interface is PEX-X.
+ * MV_BAD_PARAM on bad parameters ,
+ * otherwise MV_OK
+ *
+ */
+int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
+{
+ u32 val;
+
+ if (bus_num >= MAX_PEX_BUSSES) {
+ DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
+ bus_num, 4);
+ return MV_ERROR;
+ }
+
+ val = reg_read(PEX_STATUS_REG(pex_if));
+ val &= ~PXSR_PEX_BUS_NUM_MASK;
+ val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
+ reg_write(PEX_STATUS_REG(pex_if), val);
+
+ return MV_OK;
+}
+
+/*
+ * pex_local_dev_num_set - Set PEX interface local device number.
+ *
+ * DESCRIPTION:
+ * This function sets given PEX interface its local device number.
+ * Note: In case the PEX interface is PEX-X, the information is read-only.
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * dev_num - Device number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * MV_NOT_ALLOWED in case PEX interface is PEX-X.
+ * MV_BAD_PARAM on bad parameters ,
+ * otherwise MV_OK
+ *
+ */
+int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
+{
+ u32 val;
+
+ if (pex_if >= MV_PEX_MAX_IF)
+ return MV_BAD_PARAM;
+
+ val = reg_read(PEX_STATUS_REG(pex_if));
+ val &= ~PXSR_PEX_DEV_NUM_MASK;
+ val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
+ reg_write(PEX_STATUS_REG(pex_if), val);
+
+ return MV_OK;
+}
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
new file mode 100644
index 0000000..115ec2c
--- /dev/null
+++ b/arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "high_speed_env_spec.h"
+
+MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
+ /* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
+ {
+ /* PEX: Change of Slew Rate port0 */
+ SERDES_UNIT_PEX, 0x0,
+ (0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
+ }, {
+ /* PEX: Change PLL BW port0 */
+ SERDES_UNIT_PEX, 0x0,
+ (0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
+ }, {
+ /* SGMII: FFE setting Port0 */
+ SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
+ }, {
+ /* SGMII: SELMUP and SELMUF Port0 */
+ SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
+ }, {
+ /* SGMII: Amplitude new setting gen2 Port3 */
+ SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
+ }, {
+ /* QSGMII: Amplitude and slew rate change */
+ SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
+ }, {
+ /* QSGMII: SELMUP and SELMUF */
+ SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
+ }, {
+ /* QSGMII: 0x72e18 */
+ SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
+ }, {
+ /* Null terminated */
+ SERDES_UNIT_UNCONNECTED, 0, 0
+ }
+};
+
+MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
+ /* Z1B */
+ {MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* PEX module */
+ /* Z1A */
+ {MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
+ PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
+ {MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0030, serdes_change_m_phy} /* PEX module - Z1A */
+};
+
+MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
+ /* A0 */
+ {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
+ {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
+ {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
+ {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
+ {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
+ {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
+};
+
+MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00f4, serdes_change_m_phy}, /* Switch module */
+};
+
+MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy}, /* CPU0 */
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* CPU1-3 */
+};
+
+MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy}, /* CPU0 */
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* CPU1-3 */
+};
+
+MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
+ {MV_PEX_END_POINT, 0x22321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
+ {MV_PEX_END_POINT, 0x23321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0000, serdes_change_m_phy} /* No PEX in FPGA */
+};
+
+MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
+ 0x0030, serdes_change_m_phy} /* Default */
+};
+
+/*
+ * ARMADA-XP CUSTOMER BOARD
+ */
+MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00000030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00000030, serdes_change_m_phy}, /* Switch module */
+};
+
+MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
+ db88f78xx0_serdes_cfg,
+ rd78460_serdes_cfg,
+ db78X60pcac_serdes_cfg,
+ fpga88f78xx0_serdes_cfg,
+ db88f78xx0rev2_serdes_cfg,
+ rd78460nas_serdes_cfg,
+ db78X60amc_serdes_cfg,
+ db78X60pcacrev2_serdes_cfg,
+ rd78460server_rev2_serdes_cfg,
+ rd78460AXP_GP_serdes_cfg,
+ rd78460customer_serdes_cfg
+};
+
+u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
+u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_spec.h b/arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
new file mode 100644
index 0000000..e5aa1b0
--- /dev/null
+++ b/arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __HIGHSPEED_ENV_SPEC_H
+#define __HIGHSPEED_ENV_SPEC_H
+
+#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+
+typedef enum {
+ SERDES_UNIT_UNCONNECTED = 0x0,
+ SERDES_UNIT_PEX = 0x1,
+ SERDES_UNIT_SATA = 0x2,
+ SERDES_UNIT_SGMII0 = 0x3,
+ SERDES_UNIT_SGMII1 = 0x4,
+ SERDES_UNIT_SGMII2 = 0x5,
+ SERDES_UNIT_SGMII3 = 0x6,
+ SERDES_UNIT_QSGMII = 0x7,
+ SERDES_UNIT_SETM = 0x8,
+ SERDES_LAST_UNIT
+} MV_BIN_SERDES_UNIT_INDX;
+
+
+typedef enum {
+ PEX_BUS_DISABLED = 0,
+ PEX_BUS_MODE_X1 = 1,
+ PEX_BUS_MODE_X4 = 2,
+ PEX_BUS_MODE_X8 = 3
+} MV_PEX_UNIT_CFG;
+
+typedef enum pex_type {
+ MV_PEX_ROOT_COMPLEX, /* root complex device */
+ MV_PEX_END_POINT /* end point device */
+} MV_PEX_TYPE;
+
+typedef struct serdes_change_m_phy {
+ MV_BIN_SERDES_UNIT_INDX type;
+ u32 reg_low_speed;
+ u32 val_low_speed;
+ u32 reg_hi_speed;
+ u32 val_hi_speed;
+} MV_SERDES_CHANGE_M_PHY;
+
+/*
+ * Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
+ */
+typedef struct board_serdes_conf {
+ MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
+ u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
+ u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
+ MV_PEX_UNIT_CFG pex_mode[4];
+
+ /*
+ * Bus speed - one bit per SERDES line:
+ * Low speed (0) High speed (1)
+ * PEX 2.5 G (10 bit) 5 G (20 bit)
+ * SATA 1.5 G 3 G
+ * SGMII 1.25 Gbps 3.125 Gbps
+ */
+ u32 bus_speed;
+
+ MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
+} MV_BIN_SERDES_CFG;
+
+
+#define BIN_SERDES_CFG { \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
+ {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
+ {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
+ {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
+ {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
+ {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
+ {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */ \
+}
+
+#endif /* __HIGHSPEED_ENV_SPEC_H */
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
new file mode 100644
index 0000000..402e520
--- /dev/null
+++ b/arch/arm/mach-mvebu/spl.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ /* Right now only booting via SPI NOR flash is supported */
+ return BOOT_DEVICE_SPI;
+}
+
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ arch_cpu_init();
+
+ preloader_console_init();
+
+ /* First init the serdes PHY's */
+ serdes_phy_config();
+
+ /* Setup DDR */
+ ddr3_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c
new file mode 100644
index 0000000..40c4bc2
--- /dev/null
+++ b/arch/arm/mach-mvebu/timer.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/soc.h>
+
+#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG &tmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
+#if defined(CONFIG_ARMADA_XP)
+#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
+#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
+#else
+#define CTCR_ARM_TIMER_25MHZ(cntr) 0
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+/* Timer reload and current value registers */
+struct kwtmr_val {
+ u32 reload; /* Timer reload reg */
+ u32 val; /* Timer value reg */
+};
+
+/* Timer registers */
+struct kwtmr_registers {
+ u32 ctrl; /* Timer control reg */
+ u32 pad[3];
+ struct kwtmr_val tmr[4];
+ u32 wdt_reload;
+ u32 wdt_val;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct kwtmr_registers *tmr_regs =
+ (struct kwtmr_registers *)MVEBU_TIMER_BASE;
+
+static inline ulong read_timer(void)
+{
+ return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = read_timer();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec +
+ (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ uint current;
+ ulong delayticks;
+
+ current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+ delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+ if (current < delayticks) {
+ delayticks -= current;
+ while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
+ while ((TIMER_LOAD_VAL - delayticks) <
+ readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
+ } else {
+ while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+ (current - delayticks)) ;
+ }
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+ /* load value into timer */
+ writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+ /* enable timer in auto reload mode */
+ clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
+ CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
+ CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
+
+ /* init the timestamp and lastdec value */
+ lastdec = read_timer();
+ timestamp = 0;
+
+ return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/mach-mvebu/u-boot-spl.lds b/arch/arm/mach-mvebu/u-boot-spl.lds
new file mode 100644
index 0000000..eee1db4
--- /dev/null
+++ b/arch/arm/mach-mvebu/u-boot-spl.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text*)
+ *(.text*)
+ *(.vectors)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*_i2c_*)));
+ } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sdram
+}
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