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-rw-r--r--arch/arm/include/asm/arch-tnetv107x/clock.h53
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/hardware.h160
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/mux.h291
3 files changed, 0 insertions, 504 deletions
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
deleted file mode 100644
index dfc3b1b..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/clock.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
-#define PSC_MDCTL_NEXT_SYNCRST 0x1
-#define PSC_MDCTL_NEXT_DISABLE 0x2
-#define PSC_MDCTL_NEXT_ENABLE 0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ 24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
- SYS_PLL,
- TDM_PLL,
- ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
- int pll;
- int internal_osc;
- unsigned long pll_freq;
- unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
deleted file mode 100644
index d458e0b..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * TNETV107X: Hardware information
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS 4
-#define ASYNC_EMIF_MODE_NOR 0
-#define ASYNC_EMIF_MODE_NAND 1
-#define ASYNC_EMIF_MODE_ONENAND 2
-#define ASYNC_EMIF_PRESERVE -1
-
-struct async_emif_config {
- unsigned mode;
- unsigned select_strobe;
- unsigned extend_wait;
- unsigned wr_setup;
- unsigned wr_strobe;
- unsigned wr_hold;
- unsigned rd_setup;
- unsigned rd_strobe;
- unsigned rd_hold;
- unsigned turn_around;
- enum {
- ASYNC_EMIF_8 = 0,
- ASYNC_EMIF_16 = 1,
- ASYNC_EMIF_32 = 2,
- } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC 0x83e70b13
-#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE 0x01C00000
-#define TNETV107X_TPTC0_BASE 0x01C10000
-#define TNETV107X_TPTC1_BASE 0x01C10400
-#define TNETV107X_INTC_BASE 0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
-#define TNETV107X_INTD_BASE 0x08038000
-#define TNETV107X_INTD_IPC_BASE 0x08038000
-#define TNETV107X_INTD_FAST_BASE 0x08039000
-#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
-#define TNETV107X_INTD_SLOW_BASE 0x0803B000
-#define TNETV107X_PKA_BASE 0x08040000
-#define TNETV107X_RNG_BASE 0x08044000
-#define TNETV107X_TIMER0_BASE 0x08086500
-#define TNETV107X_TIMER1_BASE 0x08086600
-#define TNETV107X_WDT0_ARM_BASE 0x08086700
-#define TNETV107X_WDT1_DSP_BASE 0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
-#define TNETV107X_GPIO_BASE 0x08088000
-#define TNETV107X_UART1_BASE 0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
-#define TNETV107X_SDIO0_BASE 0x08088700
-#define TNETV107X_SDIO1_BASE 0x08088800
-#define TNETV107X_MDIO_BASE 0x08088900
-#define TNETV107X_KEYPAD_BASE 0x08088A00
-#define TNETV107X_SSP_BASE 0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
-#define TNETV107X_PSC_BASE 0x0808B000
-#define TNETV107X_TDM0_BASE 0x08100000
-#define TNETV107X_TDM1_BASE 0x08100100
-#define TNETV107X_MCDMA_BASE 0x08108000
-#define TNETV107X_UART0_DMA_BASE 0x08108200
-#define TNETV107X_USBSS_BASE 0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
-#define TNETV107X_IMCOP_BASE 0x01CC0000
-#define TNETV107X_MBX_LITE_BASE 0x07000000
-#define TNETV107X_ETHSS_BASE 0x0803C000
-#define TNETV107X_CPSW_BASE 0x0803C000
-#define TNETV107X_SPF_BASE 0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
-#define TNETV107X_VTP_CNTRL_0 0x0803D800
-#define TNETV107X_VTP_CNTRL_1 0x0803D900
-#define TNETV107X_UART2_DMA_BASE 0x08108400
-#define TNETV107X_INTERNAL_MEMORY 0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM 0
-#define TNETV107X_LPSC_GEM 1
-#define TNETV107X_LPSC_DDR2_PHY 2
-#define TNETV107X_LPSC_TPCC 3
-#define TNETV107X_LPSC_TPTC0 4
-#define TNETV107X_LPSC_TPTC1 5
-#define TNETV107X_LPSC_RAM 6
-#define TNETV107X_LPSC_MBX_LITE 7
-#define TNETV107X_LPSC_LCD 8
-#define TNETV107X_LPSC_ETHSS 9
-#define TNETV107X_LPSC_AEMIF 10
-#define TNETV107X_LPSC_CHIP_CFG 11
-#define TNETV107X_LPSC_TSC 12
-#define TNETV107X_LPSC_ROM 13
-#define TNETV107X_LPSC_UART2 14
-#define TNETV107X_LPSC_PKTSEC 15
-#define TNETV107X_LPSC_SECCTL 16
-#define TNETV107X_LPSC_KEYMGR 17
-#define TNETV107X_LPSC_KEYPAD 18
-#define TNETV107X_LPSC_GPIO 19
-#define TNETV107X_LPSC_MDIO 20
-#define TNETV107X_LPSC_SDIO0 21
-#define TNETV107X_LPSC_UART0 22
-#define TNETV107X_LPSC_UART1 23
-#define TNETV107X_LPSC_TIMER0 24
-#define TNETV107X_LPSC_TIMER1 25
-#define TNETV107X_LPSC_WDT_ARM 26
-#define TNETV107X_LPSC_WDT_DSP 27
-#define TNETV107X_LPSC_SSP 28
-#define TNETV107X_LPSC_TDM0 29
-#define TNETV107X_LPSC_VLYNQ 30
-#define TNETV107X_LPSC_MCDMA 31
-#define TNETV107X_LPSC_USB0 32
-#define TNETV107X_LPSC_TDM1 33
-#define TNETV107X_LPSC_DEBUGSS 34
-#define TNETV107X_LPSC_ETHSS_RGMII 35
-#define TNETV107X_LPSC_SYSTEM 36
-#define TNETV107X_LPSC_IMCOP 37
-#define TNETV107X_LPSC_SPARE 38
-#define TNETV107X_LPSC_SDIO1 39
-#define TNETV107X_LPSC_USB1 40
-#define TNETV107X_LPSC_USBSS 41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
-#define TNETV107X_LPSC_MAX 44
-
-/* Interrupt controller */
-#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
deleted file mode 100644
index 3f832c4..0000000
--- a/arch/arm/include/asm/arch-tnetv107x/mux.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * TNETV107X: Pinmux APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
- unsigned char reg_index;
- unsigned char mask_offset;
- unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
- { reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
- TNETV107X_PIN_ASR_A00,
- TNETV107X_PIN_GPIO32,
- TNETV107X_PIN_ASR_A01,
- TNETV107X_PIN_GPIO33,
- TNETV107X_PIN_ASR_A02,
- TNETV107X_PIN_GPIO34,
- TNETV107X_PIN_ASR_A03,
- TNETV107X_PIN_GPIO35,
- TNETV107X_PIN_ASR_A04,
- TNETV107X_PIN_GPIO36,
- TNETV107X_PIN_ASR_A05,
- TNETV107X_PIN_GPIO37,
- TNETV107X_PIN_ASR_A06,
- TNETV107X_PIN_GPIO38,
- TNETV107X_PIN_ASR_A07,
- TNETV107X_PIN_GPIO39,
- TNETV107X_PIN_ASR_A08,
- TNETV107X_PIN_GPIO40,
- TNETV107X_PIN_ASR_A09,
- TNETV107X_PIN_GPIO41,
- TNETV107X_PIN_ASR_A10,
- TNETV107X_PIN_GPIO42,
- TNETV107X_PIN_ASR_A11,
- TNETV107X_PIN_BOOT_STRP_0,
- TNETV107X_PIN_ASR_A12,
- TNETV107X_PIN_BOOT_STRP_1,
- TNETV107X_PIN_ASR_A13,
- TNETV107X_PIN_GPIO43,
- TNETV107X_PIN_ASR_A14,
- TNETV107X_PIN_GPIO44,
- TNETV107X_PIN_ASR_A15,
- TNETV107X_PIN_GPIO45,
- TNETV107X_PIN_ASR_A16,
- TNETV107X_PIN_GPIO46,
- TNETV107X_PIN_ASR_A17,
- TNETV107X_PIN_GPIO47,
- TNETV107X_PIN_ASR_A18,
- TNETV107X_PIN_GPIO48,
- TNETV107X_PIN_SDIO1_DATA3_0,
- TNETV107X_PIN_ASR_A19,
- TNETV107X_PIN_GPIO49,
- TNETV107X_PIN_SDIO1_DATA2_0,
- TNETV107X_PIN_ASR_A20,
- TNETV107X_PIN_GPIO50,
- TNETV107X_PIN_SDIO1_DATA1_0,
- TNETV107X_PIN_ASR_A21,
- TNETV107X_PIN_GPIO51,
- TNETV107X_PIN_SDIO1_DATA0_0,
- TNETV107X_PIN_ASR_A22,
- TNETV107X_PIN_GPIO52,
- TNETV107X_PIN_SDIO1_CMD_0,
- TNETV107X_PIN_ASR_A23,
- TNETV107X_PIN_GPIO53,
- TNETV107X_PIN_SDIO1_CLK_0,
- TNETV107X_PIN_ASR_BA_1,
- TNETV107X_PIN_GPIO54,
- TNETV107X_PIN_SYS_PLL_CLK,
- TNETV107X_PIN_ASR_CS0,
- TNETV107X_PIN_ASR_CS1,
- TNETV107X_PIN_ASR_CS2,
- TNETV107X_PIN_TDM_PLL_CLK,
- TNETV107X_PIN_ASR_CS3,
- TNETV107X_PIN_ETH_PHY_CLK,
- TNETV107X_PIN_ASR_D00,
- TNETV107X_PIN_GPIO55,
- TNETV107X_PIN_ASR_D01,
- TNETV107X_PIN_GPIO56,
- TNETV107X_PIN_ASR_D02,
- TNETV107X_PIN_GPIO57,
- TNETV107X_PIN_ASR_D03,
- TNETV107X_PIN_GPIO58,
- TNETV107X_PIN_ASR_D04,
- TNETV107X_PIN_GPIO59_0,
- TNETV107X_PIN_ASR_D05,
- TNETV107X_PIN_GPIO60_0,
- TNETV107X_PIN_ASR_D06,
- TNETV107X_PIN_GPIO61_0,
- TNETV107X_PIN_ASR_D07,
- TNETV107X_PIN_GPIO62_0,
- TNETV107X_PIN_ASR_D08,
- TNETV107X_PIN_GPIO63_0,
- TNETV107X_PIN_ASR_D09,
- TNETV107X_PIN_GPIO64_0,
- TNETV107X_PIN_ASR_D10,
- TNETV107X_PIN_SDIO1_DATA3_1,
- TNETV107X_PIN_ASR_D11,
- TNETV107X_PIN_SDIO1_DATA2_1,
- TNETV107X_PIN_ASR_D12,
- TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_ASR_D13,
- TNETV107X_PIN_SDIO1_DATA0_1,
- TNETV107X_PIN_ASR_D14,
- TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_ASR_D15,
- TNETV107X_PIN_SDIO1_CLK_1,
- TNETV107X_PIN_ASR_OE,
- TNETV107X_PIN_BOOT_STRP_2,
- TNETV107X_PIN_ASR_RNW,
- TNETV107X_PIN_GPIO29_0,
- TNETV107X_PIN_ASR_WAIT,
- TNETV107X_PIN_GPIO30_0,
- TNETV107X_PIN_ASR_WE,
- TNETV107X_PIN_BOOT_STRP_3,
- TNETV107X_PIN_ASR_WE_DQM0,
- TNETV107X_PIN_GPIO31,
- TNETV107X_PIN_LCD_PD17_0,
- TNETV107X_PIN_ASR_WE_DQM1,
- TNETV107X_PIN_ASR_BA0_0,
- TNETV107X_PIN_VLYNQ_CLK,
- TNETV107X_PIN_GPIO14,
- TNETV107X_PIN_LCD_PD19_0,
- TNETV107X_PIN_VLYNQ_RXD0,
- TNETV107X_PIN_GPIO15,
- TNETV107X_PIN_LCD_PD20_0,
- TNETV107X_PIN_VLYNQ_RXD1,
- TNETV107X_PIN_GPIO16,
- TNETV107X_PIN_LCD_PD21_0,
- TNETV107X_PIN_VLYNQ_TXD0,
- TNETV107X_PIN_GPIO17,
- TNETV107X_PIN_LCD_PD22_0,
- TNETV107X_PIN_VLYNQ_TXD1,
- TNETV107X_PIN_GPIO18,
- TNETV107X_PIN_LCD_PD23_0,
- TNETV107X_PIN_SDIO0_CLK,
- TNETV107X_PIN_GPIO19,
- TNETV107X_PIN_SDIO0_CMD,
- TNETV107X_PIN_GPIO20,
- TNETV107X_PIN_SDIO0_DATA0,
- TNETV107X_PIN_GPIO21,
- TNETV107X_PIN_SDIO0_DATA1,
- TNETV107X_PIN_GPIO22,
- TNETV107X_PIN_SDIO0_DATA2,
- TNETV107X_PIN_GPIO23,
- TNETV107X_PIN_SDIO0_DATA3,
- TNETV107X_PIN_GPIO24,
- TNETV107X_PIN_EMU0,
- TNETV107X_PIN_EMU1,
- TNETV107X_PIN_RTCK,
- TNETV107X_PIN_TRST_N,
- TNETV107X_PIN_TCK,
- TNETV107X_PIN_TDI,
- TNETV107X_PIN_TDO,
- TNETV107X_PIN_TMS,
- TNETV107X_PIN_TDM1_CLK,
- TNETV107X_PIN_TDM1_RX,
- TNETV107X_PIN_TDM1_TX,
- TNETV107X_PIN_TDM1_FS,
- TNETV107X_PIN_KEYPAD_R0,
- TNETV107X_PIN_KEYPAD_R1,
- TNETV107X_PIN_KEYPAD_R2,
- TNETV107X_PIN_KEYPAD_R3,
- TNETV107X_PIN_KEYPAD_R4,
- TNETV107X_PIN_KEYPAD_R5,
- TNETV107X_PIN_KEYPAD_R6,
- TNETV107X_PIN_GPIO12,
- TNETV107X_PIN_KEYPAD_R7,
- TNETV107X_PIN_GPIO10,
- TNETV107X_PIN_KEYPAD_C0,
- TNETV107X_PIN_KEYPAD_C1,
- TNETV107X_PIN_KEYPAD_C2,
- TNETV107X_PIN_KEYPAD_C3,
- TNETV107X_PIN_KEYPAD_C4,
- TNETV107X_PIN_KEYPAD_C5,
- TNETV107X_PIN_KEYPAD_C6,
- TNETV107X_PIN_GPIO13,
- TNETV107X_PIN_TEST_CLK_IN,
- TNETV107X_PIN_KEYPAD_C7,
- TNETV107X_PIN_GPIO11,
- TNETV107X_PIN_SSP0_0,
- TNETV107X_PIN_SCC_DCLK,
- TNETV107X_PIN_LCD_PD20_1,
- TNETV107X_PIN_SSP0_1,
- TNETV107X_PIN_SCC_CS_N,
- TNETV107X_PIN_LCD_PD21_1,
- TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SCC_D,
- TNETV107X_PIN_LCD_PD22_1,
- TNETV107X_PIN_SSP0_3,
- TNETV107X_PIN_SCC_RESETN,
- TNETV107X_PIN_LCD_PD23_1,
- TNETV107X_PIN_SSP1_0,
- TNETV107X_PIN_GPIO25,
- TNETV107X_PIN_UART2_CTS,
- TNETV107X_PIN_SSP1_1,
- TNETV107X_PIN_GPIO26,
- TNETV107X_PIN_UART2_RD,
- TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_GPIO27,
- TNETV107X_PIN_UART2_RTS,
- TNETV107X_PIN_SSP1_3,
- TNETV107X_PIN_GPIO28,
- TNETV107X_PIN_UART2_TD,
- TNETV107X_PIN_UART0_CTS,
- TNETV107X_PIN_UART0_RD,
- TNETV107X_PIN_UART0_RTS,
- TNETV107X_PIN_UART0_TD,
- TNETV107X_PIN_UART1_RD,
- TNETV107X_PIN_UART1_TD,
- TNETV107X_PIN_LCD_AC_NCS,
- TNETV107X_PIN_LCD_HSYNC_RNW,
- TNETV107X_PIN_LCD_VSYNC_A0,
- TNETV107X_PIN_LCD_MCLK,
- TNETV107X_PIN_LCD_PD16_0,
- TNETV107X_PIN_LCD_PCLK_E,
- TNETV107X_PIN_LCD_PD00,
- TNETV107X_PIN_LCD_PD01,
- TNETV107X_PIN_LCD_PD02,
- TNETV107X_PIN_LCD_PD03,
- TNETV107X_PIN_LCD_PD04,
- TNETV107X_PIN_LCD_PD05,
- TNETV107X_PIN_LCD_PD06,
- TNETV107X_PIN_LCD_PD07,
- TNETV107X_PIN_LCD_PD08,
- TNETV107X_PIN_GPIO59_1,
- TNETV107X_PIN_LCD_PD09,
- TNETV107X_PIN_GPIO60_1,
- TNETV107X_PIN_LCD_PD10,
- TNETV107X_PIN_ASR_BA0_1,
- TNETV107X_PIN_GPIO61_1,
- TNETV107X_PIN_LCD_PD11,
- TNETV107X_PIN_GPIO62_1,
- TNETV107X_PIN_LCD_PD12,
- TNETV107X_PIN_GPIO63_1,
- TNETV107X_PIN_LCD_PD13,
- TNETV107X_PIN_GPIO64_1,
- TNETV107X_PIN_LCD_PD14,
- TNETV107X_PIN_GPIO29_1,
- TNETV107X_PIN_LCD_PD15,
- TNETV107X_PIN_GPIO30_1,
- TNETV107X_PIN_EINT0,
- TNETV107X_PIN_GPIO08,
- TNETV107X_PIN_EINT1,
- TNETV107X_PIN_GPIO09,
- TNETV107X_PIN_GPIO00,
- TNETV107X_PIN_LCD_PD20_2,
- TNETV107X_PIN_TDM_CLK_IN_2,
- TNETV107X_PIN_GPIO01,
- TNETV107X_PIN_LCD_PD21_2,
- TNETV107X_PIN_24M_CLK_OUT_1,
- TNETV107X_PIN_GPIO02,
- TNETV107X_PIN_LCD_PD22_2,
- TNETV107X_PIN_GPIO03,
- TNETV107X_PIN_LCD_PD23_2,
- TNETV107X_PIN_GPIO04,
- TNETV107X_PIN_LCD_PD16_1,
- TNETV107X_PIN_USB0_RXERR,
- TNETV107X_PIN_GPIO05,
- TNETV107X_PIN_LCD_PD17_1,
- TNETV107X_PIN_TDM_CLK_IN_1,
- TNETV107X_PIN_GPIO06,
- TNETV107X_PIN_LCD_PD18,
- TNETV107X_PIN_24M_CLK_OUT_2,
- TNETV107X_PIN_GPIO07,
- TNETV107X_PIN_LCD_PD19_1,
- TNETV107X_PIN_USB1_RXERR,
- TNETV107X_PIN_ETH_PLL_CLK,
- TNETV107X_PIN_MDIO,
- TNETV107X_PIN_MDC,
- TNETV107X_PIN_AIC_MUTE_STAT_N,
- TNETV107X_PIN_TDM0_CLK,
- TNETV107X_PIN_AIC_HNS_EN_N,
- TNETV107X_PIN_TDM0_FS,
- TNETV107X_PIN_AIC_HDS_EN_STAT_N,
- TNETV107X_PIN_TDM0_TX,
- TNETV107X_PIN_AIC_HNF_EN_STAT_N,
- TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
generated by cgit v1.1 at 2024-11-18 09:16:40 +0000