diff options
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 98 |
1 files changed, 67 insertions, 31 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 7d9fe73..fe75da4 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -110,6 +110,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_RBC_EN (1 << 27) #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 +/* CCR_WB does not exist on i.MX6SX/UL */ #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) @@ -150,12 +151,11 @@ struct mxc_ccm_reg { /* Define the bits in register CBCDR */ #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) +#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) -#ifndef CONFIG_MX6SX +/* MMDC_CH0 not exists on i.MX6SX */ #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 -#endif #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) @@ -178,7 +178,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) +#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 #ifndef CONFIG_MX6SX @@ -203,18 +203,19 @@ struct mxc_ccm_reg { /* Define the bits in register CSCMR1 */ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 -#ifdef CONFIG_MX6SX +/* QSPI1 exist on i.MX6SX/UL */ #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 -#else #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 -#endif #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 +/* CSCMR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) @@ -225,10 +226,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 -#ifdef CONFIG_MX6SX +/* QSPI1 exist on i.MX6SX/UL */ #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 -#endif /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 @@ -256,6 +256,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 #endif +/* CSCDR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 +#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 + #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) @@ -290,7 +296,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 /* Define the bits in register CS2CDR */ -#ifdef CONFIG_MX6SX +/* QSPI2 on i.MX6SX */ #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) @@ -300,7 +306,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) -#else + #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) @@ -308,14 +314,26 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ - (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16)) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ - (is_mx6dqp() ? 15 : 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ - (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16)) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) -#endif #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) @@ -543,10 +561,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) -#ifndef CONFIG_MX6SX -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) -#endif +/* CCGR1_ENET does not exist on i.MX6SX/UL */ +#define MXC_CCM_CCGR1_ENET_OFFSET 10 +#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 @@ -617,21 +634,21 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) #endif -#ifdef CONFIG_MX6SX +/* Exist on i.MX6SX */ #define MXC_CCM_CCGR3_M4_OFFSET 2 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) #define MXC_CCM_CCGR3_ENET_OFFSET 4 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) #define MXC_CCM_CCGR3_QSPI_OFFSET 14 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) -#else + #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) -#endif + #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 @@ -640,15 +657,22 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) -#ifdef CONFIG_MX6SX + +/* QSPI1 exists on i.MX6SX/UL */ #define MXC_CCM_CCGR3_QSPI1_OFFSET 14 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) -#else + #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) -#endif + +/* A7_CLKDIV/WDOG1 on i.MX6UL */ +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) + #define MXC_CCM_CCGR3_MLB_OFFSET 18 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 @@ -661,8 +685,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) +/* AXI on i.MX6UL */ +#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 +#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) + +/* GPIO4 on i.MX6UL */ +#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 +#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) + #ifndef CONFIG_MX6SX #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) @@ -670,13 +702,11 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR4_PCIE_OFFSET 0 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) -#ifdef CONFIG_MX6SX +/* QSPI2 on i.MX6SX */ #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) -#else #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) -#endif #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 @@ -736,6 +766,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) +/* GPMI/BCH on i.MX6UL */ +#define MXC_CCM_CCGR6_BCH_OFFSET 6 +#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) +#define MXC_CCM_CCGR6_GPMI_OFFSET 8 +#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) + #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 |