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-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h12
-rw-r--r--arch/arm/include/asm/arch-mx25/imx-regs.h4
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h11
-rw-r--r--arch/arm/include/asm/arch-mx6/clock.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h34
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h57
-rw-r--r--arch/arm/include/asm/arch-mx7/imx-regs.h99
-rw-r--r--arch/arm/include/asm/arch-mxs/clock.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/imx-regs.h2
-rw-r--r--arch/arm/include/asm/imx-common/hab.h (renamed from arch/arm/include/asm/arch-mx6/hab.h)11
-rw-r--r--arch/arm/include/asm/imx-common/regs-common.h2
-rw-r--r--arch/arm/include/asm/imx-common/regs-lcdif.h (renamed from arch/arm/include/asm/arch-mxs/regs-lcdif.h)30
-rw-r--r--arch/arm/include/asm/imx-common/sys_proto.h2
13 files changed, 133 insertions, 135 deletions
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 7e681e9..8a75902 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -27,6 +27,18 @@
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x25
+#define CHIP_REV_3_0 0x30
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+#define BOARD_VER_OFFSET 0x8
+
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 78c4e9b..1b00ed7 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -526,8 +526,4 @@ struct cspi_regs {
IMX_CSPI2_BASE, \
IMX_CSPI3_BASE
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_1_2 0x12
-
#endif /* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 5f0e1e6..e73cc07 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -291,17 +291,6 @@
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_5 0x25
-#define CHIP_REV_3_0 0x30
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#define BOARD_VER_OFFSET 0x8
-
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 2b220d6..1450523 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -66,6 +66,8 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
+int enable_lcdif_clock(u32 base_addr);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 10306cd..13e0a3d 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -174,6 +174,9 @@ struct mxc_ccm_reg {
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
+/* LCDIF on i.MX6SX/UL */
+#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
@@ -210,7 +213,10 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
-/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
+/* LCFIF2_PODF on i.MX6SX */
+#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
+/* ACLK_EMI on i.MX6DQ/SDL/DQP */
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
/* CSCMR1_GPMI/BCH exist on i.MX6UL */
@@ -400,6 +406,20 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
+/* LCDIF1 on i.MX6SX/UL */
+#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15
+#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12)
+#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12
+#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9
+/* LCDIF2 on i.MX6SX */
+#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6
+#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3
+#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
+#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
/* All IPU2_DI1 are LCDIF1 on MX6SX */
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
@@ -622,17 +642,16 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#ifdef CONFIG_MX6SX
+/* i.MX6SX/UL LCD and PXP */
#define MXC_CCM_CCGR2_LCD_OFFSET 28
#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
#define MXC_CCM_CCGR2_PXP_OFFSET 30
#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
-#else
+
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
-#endif
/* Exist on i.MX6SX */
#define MXC_CCM_CCGR3_M4_OFFSET 2
@@ -685,6 +704,13 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+
+#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6
+#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8
+#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10
+#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
/* AXI on i.MX6UL */
#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 74512ac..2f068e5 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -264,6 +264,7 @@
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#ifdef CONFIG_MX6SX
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#else
@@ -300,8 +301,6 @@
#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
@@ -319,16 +318,11 @@
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
#endif
+/* Only for i.MX6SX */
+#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
-/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
- MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
-
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_2 0x12
-#define CHIP_REV_1_5 0x15
-#define CHIP_REV_2_0 0x20
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else
@@ -336,9 +330,17 @@
#endif
#define FEC_QUIRK_ENET_MAC
+#include <asm/imx-common/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
+#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR
+
+
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14
@@ -413,10 +415,37 @@ struct src {
};
/* GPR1 bitfields */
+#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
+#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
+#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
+#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
+#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
+#define IOMUXC_GPR1_DPI_OFF BIT(24)
+#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
+#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
+#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
+#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
+#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
+#define IOMUXC_GPR1_PCIE_INT BIT(14)
#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+#define IOMUXC_GPR1_GINT BIT(12)
+#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
+#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
+#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
+#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
+#define IOMUXC_GPR1_ACT_CS3 BIT(9)
+#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
+#define IOMUXC_GPR1_ACT_CS2 BIT(6)
+#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
+#define IOMUXC_GPR1_ACT_CS1 BIT(3)
+#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
+#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
+#define IOMUXC_GPR1_ACT_CS0 BIT(0)
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
@@ -465,6 +494,14 @@ struct src {
#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+/* gpr12 bitfields */
+#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
+#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
+#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
+#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
+#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
+#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
struct iomuxc {
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 4dc11ee..e28a807 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -217,6 +217,7 @@
#define SNVS_LPGPR 0x68
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/imx-common/regs-lcdif.h>
#include <asm/types.h>
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -866,6 +867,9 @@ struct cspi_regs {
ECSPI3_BASE_ADDR, \
ECSPI4_BASE_ADDR
+#define CSU_INIT_SEC_LEVEL0 0x00FF00FF
+#define CSU_NUM_REGS 64
+
struct ocotp_regs {
u32 ctrl;
u32 ctrl_set;
@@ -1029,101 +1033,6 @@ struct rdc_sema_regs {
u16 rstgt; /* Reset Gate */
};
-/* eLCDIF controller registers */
-struct mxs_lcdif_regs {
- u32 hw_lcdif_ctrl; /* 0x00 */
- u32 hw_lcdif_ctrl_set;
- u32 hw_lcdif_ctrl_clr;
- u32 hw_lcdif_ctrl_tog;
- u32 hw_lcdif_ctrl1; /* 0x10 */
- u32 hw_lcdif_ctrl1_set;
- u32 hw_lcdif_ctrl1_clr;
- u32 hw_lcdif_ctrl1_tog;
- u32 hw_lcdif_ctrl2; /* 0x20 */
- u32 hw_lcdif_ctrl2_set;
- u32 hw_lcdif_ctrl2_clr;
- u32 hw_lcdif_ctrl2_tog;
- u32 hw_lcdif_transfer_count; /* 0x30 */
- u32 reserved1[3];
- u32 hw_lcdif_cur_buf; /* 0x40 */
- u32 reserved2[3];
- u32 hw_lcdif_next_buf; /* 0x50 */
- u32 reserved3[3];
- u32 hw_lcdif_timing; /* 0x60 */
- u32 reserved4[3];
- u32 hw_lcdif_vdctrl0; /* 0x70 */
- u32 hw_lcdif_vdctrl0_set;
- u32 hw_lcdif_vdctrl0_clr;
- u32 hw_lcdif_vdctrl0_tog;
- u32 hw_lcdif_vdctrl1; /* 0x80 */
- u32 reserved5[3];
- u32 hw_lcdif_vdctrl2; /* 0x90 */
- u32 reserved6[3];
- u32 hw_lcdif_vdctrl3; /* 0xa0 */
- u32 reserved7[3];
- u32 hw_lcdif_vdctrl4; /* 0xb0 */
- u32 reserved8[3];
- u32 hw_lcdif_dvictrl0; /* 0xc0 */
- u32 reserved9[3];
- u32 hw_lcdif_dvictrl1; /* 0xd0 */
- u32 reserved10[3];
- u32 hw_lcdif_dvictrl2; /* 0xe0 */
- u32 reserved11[3];
- u32 hw_lcdif_dvictrl3; /* 0xf0 */
- u32 reserved12[3];
- u32 hw_lcdif_dvictrl4; /* 0x100 */
- u32 reserved13[3];
- u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */
- u32 reserved14[3];
- u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */
- u32 reserved15[3];
- u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */
- u32 reserved16[3];
- u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */
- u32 reserved17[3];
- u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */
- u32 reserved18[3];
- u32 hw_lcdif_csc_offset; /* 0x160 */
- u32 reserved19[3];
- u32 hw_lcdif_csc_limit; /* 0x170 */
- u32 reserved20[3];
- u32 hw_lcdif_data; /* 0x180 */
- u32 reserved21[3];
- u32 hw_lcdif_bm_error_stat; /* 0x190 */
- u32 reserved22[3];
- u32 hw_lcdif_crc_stat; /* 0x1a0 */
- u32 reserved23[3];
- u32 hw_lcdif_lcdif_stat; /* 0x1b0 */
- u32 reserved24[3];
- u32 hw_lcdif_version; /* 0x1c0 */
- u32 reserved25[3];
- u32 hw_lcdif_debug0; /* 0x1d0 */
- u32 reserved26[3];
- u32 hw_lcdif_debug1; /* 0x1e0 */
- u32 reserved27[3];
- u32 hw_lcdif_debug2; /* 0x1f0 */
- u32 reserved28[3];
- u32 hw_lcdif_thres; /* 0x200 */
- u32 reserved29[3];
- u32 hw_lcdif_as_ctrl; /* 0x210 */
- u32 reserved30[3];
- u32 hw_lcdif_as_buf; /* 0x220 */
- u32 reserved31[3];
- u32 hw_lcdif_as_next_buf; /* 0x230 */
- u32 reserved32[3];
- u32 hw_lcdif_as_clrkeylow; /* 0x240 */
- u32 reserved33[3];
- u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */
- u32 reserved34[3];
- u32 hw_lcdif_as_sync_delay; /* 0x260 */
- u32 reserved35[3];
- u32 hw_lcdif_as_debug3; /* 0x270 */
- u32 reserved36[3];
- u32 hw_lcdif_as_debug4; /* 0x280 */
- u32 reserved37[3];
- u32 hw_lcdif_as_debug5; /* 0x290 */
-};
-
#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
#define LCDIF_CTRL_SFTRST (1 << 31)
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index fc9d75b..fdc5395 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -46,7 +46,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk);
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
-void mxs_set_lcdclk(uint32_t freq);
+void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
/* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 86914ef..8872438 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -15,8 +15,8 @@
#include <asm/imx-common/regs-bch.h>
#include <asm/arch/regs-digctl.h>
#include <asm/imx-common/regs-gpmi.h>
+#include <asm/imx-common/regs-lcdif.h>
#include <asm/arch/regs-i2c.h>
-#include <asm/arch/regs-lcdif.h>
#include <asm/arch/regs-lradc.h>
#include <asm/arch/regs-ocotp.h>
#include <asm/arch/regs-pinctrl.h>
diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/imx-common/hab.h
index d0eaa67..dab6789 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/imx-common/hab.h
@@ -85,6 +85,15 @@ enum hab_context {
HAB_CTX_MAX
};
+struct imx_sec_config_fuse_t {
+ int bank;
+ int word;
+};
+
+#if defined(CONFIG_SECURE_BOOT)
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#endif
+
/*Function prototype description*/
typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
uint8_t* , size_t*);
@@ -113,7 +122,7 @@ typedef void hapi_clock_init_t(void);
#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
#define HAB_ENG_SW 0xff /* Software engine */
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
#define HAB_RVT_BASE 0x00000100
#else
#define HAB_RVT_BASE 0x00000094
diff --git a/arch/arm/include/asm/imx-common/regs-common.h b/arch/arm/include/asm/imx-common/regs-common.h
index e54a220..7382674 100644
--- a/arch/arm/include/asm/imx-common/regs-common.h
+++ b/arch/arm/include/asm/imx-common/regs-common.h
@@ -10,6 +10,8 @@
#ifndef __MXS_REGS_COMMON_H__
#define __MXS_REGS_COMMON_H__
+#include <linux/types.h>
+
/*
* The i.MXS has interesting feature when it comes to register access. There
* are four kinds of access to one particular register. Those are:
diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h
index 8915d84..5a4f61f 100644
--- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h
+++ b/arch/arm/include/asm/imx-common/regs-lcdif.h
@@ -1,5 +1,5 @@
/*
- * Freescale i.MX28 LCDIF Register Definitions
+ * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@@ -10,16 +10,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __MX28_REGS_LCDIF_H__
-#define __MX28_REGS_LCDIF_H__
+#ifndef __IMX_REGS_LCDIF_H__
+#define __IMX_REGS_LCDIF_H__
+#ifndef __ASSEMBLY__
#include <asm/imx-common/regs-common.h>
-#ifndef __ASSEMBLY__
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
-#if defined(CONFIG_MX28)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -54,7 +55,8 @@ struct mxs_lcdif_regs {
#endif
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
-#if defined(CONFIG_MX28)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX7)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -62,6 +64,18 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
+ mxs_reg_32(hw_lcdif_thres)
+ mxs_reg_32(hw_lcdif_as_ctrl)
+ mxs_reg_32(hw_lcdif_as_buf)
+ mxs_reg_32(hw_lcdif_as_next_buf)
+ mxs_reg_32(hw_lcdif_as_clrkeylow)
+ mxs_reg_32(hw_lcdif_as_clrkeyhigh)
+ mxs_reg_32(hw_lcdif_as_sync_delay)
+ mxs_reg_32(hw_lcdif_as_debug3)
+ mxs_reg_32(hw_lcdif_as_debug4)
+ mxs_reg_32(hw_lcdif_as_debug5)
+#endif
};
#endif
@@ -194,7 +208,7 @@ struct mxs_lcdif_regs {
#if defined(CONFIG_MX23)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
-#elif defined(CONFIG_MX28)
+#else
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
#endif
@@ -214,4 +228,4 @@ struct mxs_lcdif_regs {
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
-#endif /* __MX28_REGS_LCDIF_H__ */
+#endif /* __IMX_REGS_LCDIF_H__ */
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 5673fb4..386c2dc 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -47,6 +47,8 @@ int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
+void lcdif_power_down(void);
+
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
generated by cgit v1.1 at 2024-11-11 15:05:10 +0000