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-rw-r--r--arch/arm/include/asm/arch-am33xx/clocks_am33xx.h12
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h12
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h4
-rw-r--r--arch/arm/include/asm/arch-mx27/imx-regs.h6
-rw-r--r--arch/arm/include/asm/arch-mx6/clock.h1
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/iomux.h5
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6dl_pins.h6
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6q_pins.h1
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h12
-rw-r--r--arch/arm/include/asm/arch-mxs/sys_proto.h5
-rw-r--r--arch/arm/include/asm/arch-s3c44b0/hardware.h281
-rw-r--r--arch/arm/include/asm/dma-mapping.h2
-rw-r--r--arch/arm/include/asm/global_data.h2
-rw-r--r--arch/arm/include/asm/omap_common.h6
15 files changed, 60 insertions, 297 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 140379f..02ed595 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -11,9 +11,17 @@
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000 1000
+#define MPUPLL_M_800 800
+#define MPUPLL_M_720 720
+#define MPUPLL_M_600 600
+#define MPUPLL_M_550 550
+#define MPUPLL_M_300 300
+
/* MAIN PLL Fdll = 550 MHz, by default */
#ifndef CONFIG_SYS_MPUCLK
-#define CONFIG_SYS_MPUCLK 550
+#define CONFIG_SYS_MPUCLK MPUPLL_M_550
#endif
#define UART_RESET (0x1 << 1)
@@ -21,5 +29,7 @@
#define UART_SMART_IDLE_EN (0x1 << 0x3)
extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
#endif /* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 73e6db8..52fa128 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -38,6 +38,16 @@
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300 0x1FEF
+#define AM335X_ZCZ_600 0x1FAF
+#define AM335X_ZCZ_720 0x1F2F
+#define AM335X_ZCZ_800 0x1E2F
+#define AM335X_ZCZ_1000 0x1C2F
+#define AM335X_ZCE_300 0x1FDF
+#define AM335X_ZCE_600 0x1F9F
/* This gives the status of the boot mode pins on the evm */
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
@@ -509,6 +519,8 @@ struct ctrl_dev {
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
+ unsigned int resv5[106];
+ unsigned int efuse_sma; /* offset 0x1FC */
};
/* gmii_sel register defines */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index c6070a3..87b7d36 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -10,6 +10,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <asm/arch/cpu.h>
#define BOARD_REV_ID 0x0
@@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32);
#ifdef CONFIG_NOR_BOOT
void enable_norboot_pin_mux(void);
#endif
+void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
#endif
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index a27145b..92c847e 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -169,7 +169,7 @@ struct iim_regs {
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
- } bank[1];
+ } bank[2];
};
struct fuse_bank0_regs {
@@ -209,9 +209,13 @@ struct fuse_bank0_regs {
#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
+#define IMX_NFC_BASE (0xD8000000)
#define IMX_ESD_BASE (0xD8001000)
#define IMX_WEIM_BASE (0xD8002000)
+#define NFC_BASE_ADDR IMX_NFC_BASE
+
+
/* FMCR System Control bit definition*/
#define UART4_RXD_CTL (1 << 25)
#define UART4_RTS_CTL (1 << 24)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index c493687..93f29a7 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -50,4 +50,5 @@ void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_ipu_clock(void);
+int enable_fec_anatop_clock(void);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 74aefe6..2813593 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -892,7 +892,7 @@ struct mxc_ccm_reg {
#define PLL2_PFD0_FREQ 352000000
#define PLL2_PFD1_FREQ 594000000
-#define PLL2_PFD2_FREQ 400000000
+#define PLL2_PFD2_FREQ 396000000
#define PLL2_PFD2_DIV_FREQ 200000000
#define PLL3_PFD0_FREQ 720000000
#define PLL3_PFD1_FREQ 540000000
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f4cfd4f..ff13a1e 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -27,6 +27,11 @@
#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
+#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
+ | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)
#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index c3d0b70..b5df68a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -235,7 +235,7 @@ enum {
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
@@ -309,7 +309,7 @@ enum {
MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
@@ -1043,7 +1043,7 @@ enum {
MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0),
MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0),
- MX6_PAD_GPIO_1__USBOTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
+ MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 94df007..fe9a8c3 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -984,6 +984,7 @@ enum {
MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
+ MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index b39a354..5f9c90a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -18,5 +18,17 @@ enum {
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+
+ MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
+ MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
+ MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
+ MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
+ MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
+ MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
+ MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
+ MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
+ MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
+ MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 1038592..43c7dd6 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -28,8 +28,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
#include <asm/arch/iomux-mx28.h>
#endif
-void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
- const unsigned int iomux_size);
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+ const iomux_cfg_t *iomux_setup,
+ const unsigned int iomux_size);
#endif
struct mxs_pair {
diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h
deleted file mode 100644
index 146e265..0000000
--- a/arch/arm/include/asm/arch-s3c44b0/hardware.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/********************************************************/
-/* */
-/* Samsung S3C44B0 */
-/* tpu <tapu@371.net> */
-/* */
-/********************************************************/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define REGBASE 0x01c00000
-#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr))
-#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr))
-#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr))
-
-
-/*****************************/
-/* CPU Wrapper Registers */
-/*****************************/
-
-#define SYSCFG REGL(0x000000)
-#define NCACHBE0 REGL(0x000004)
-#define NCACHBE1 REGL(0x000008)
-#define SBUSCON REGL(0x040000)
-
-/************************************/
-/* Memory Controller Registers */
-/************************************/
-
-#define BWSCON REGL(0x080000)
-#define BANKCON0 REGL(0x080004)
-#define BANKCON1 REGL(0x080008)
-#define BANKCON2 REGL(0x08000c)
-#define BANKCON3 REGL(0x080010)
-#define BANKCON4 REGL(0x080014)
-#define BANKCON5 REGL(0x080018)
-#define BANKCON6 REGL(0x08001c)
-#define BANKCON7 REGL(0x080020)
-#define REFRESH REGL(0x080024)
-#define BANKSIZE REGL(0x080028)
-#define MRSRB6 REGL(0x08002c)
-#define MRSRB7 REGL(0x080030)
-
-/*********************/
-/* UART Registers */
-/*********************/
-
-#define ULCON0 REGL(0x100000)
-#define ULCON1 REGL(0x104000)
-#define UCON0 REGL(0x100004)
-#define UCON1 REGL(0x104004)
-#define UFCON0 REGL(0x100008)
-#define UFCON1 REGL(0x104008)
-#define UMCON0 REGL(0x10000c)
-#define UMCON1 REGL(0x10400c)
-#define UTRSTAT0 REGL(0x100010)
-#define UTRSTAT1 REGL(0x104010)
-#define UERSTAT0 REGL(0x100014)
-#define UERSTAT1 REGL(0x104014)
-#define UFSTAT0 REGL(0x100018)
-#define UFSTAT1 REGL(0x104018)
-#define UMSTAT0 REGL(0x10001c)
-#define UMSTAT1 REGL(0x10401c)
-#define UTXH0 REGB(0x100020)
-#define UTXH1 REGB(0x104020)
-#define URXH0 REGB(0x100024)
-#define URXH1 REGB(0x104024)
-#define UBRDIV0 REGL(0x100028)
-#define UBRDIV1 REGL(0x104028)
-
-/*******************/
-/* SIO Registers */
-/*******************/
-
-#define SIOCON REGL(0x114000)
-#define SIODAT REGL(0x114004)
-#define SBRDR REGL(0x114008)
-#define ITVCNT REGL(0x11400c)
-#define DCNTZ REGL(0x114010)
-
-/********************/
-/* IIS Registers */
-/********************/
-
-#define IISCON REGL(0x118000)
-#define IISMOD REGL(0x118004)
-#define IISPSR REGL(0x118008)
-#define IISFIFCON REGL(0x11800c)
-#define IISFIF REGW(0x118010)
-
-/**************************/
-/* I/O Ports Registers */
-/**************************/
-
-#define PCONA REGL(0x120000)
-#define PDATA REGL(0x120004)
-#define PCONB REGL(0x120008)
-#define PDATB REGL(0x12000c)
-#define PCONC REGL(0x120010)
-#define PDATC REGL(0x120014)
-#define PUPC REGL(0x120018)
-#define PCOND REGL(0x12001c)
-#define PDATD REGL(0x120020)
-#define PUPD REGL(0x120024)
-#define PCONE REGL(0x120028)
-#define PDATE REGL(0x12002c)
-#define PUPE REGL(0x120030)
-#define PCONF REGL(0x120034)
-#define PDATF REGL(0x120038)
-#define PUPF REGL(0x12003c)
-#define PCONG REGL(0x120040)
-#define PDATG REGL(0x120044)
-#define PUPG REGL(0x120048)
-#define SPUCR REGL(0x12004c)
-#define EXTINT REGL(0x120050)
-#define EXTINTPND REGL(0x120054)
-
-/*********************************/
-/* WatchDog Timers Registers */
-/*********************************/
-
-#define WTCON REGL(0x130000)
-#define WTDAT REGL(0x130004)
-#define WTCNT REGL(0x130008)
-
-/*********************************/
-/* A/D Converter Registers */
-/*********************************/
-
-#define ADCCON REGL(0x140000)
-#define ADCPSR REGL(0x140004)
-#define ADCDAT REGL(0x140008)
-
-/***************************/
-/* PWM Timer Registers */
-/***************************/
-
-#define TCFG0 REGL(0x150000)
-#define TCFG1 REGL(0x150004)
-#define TCON REGL(0x150008)
-#define TCNTB0 REGL(0x15000c)
-#define TCMPB0 REGL(0x150010)
-#define TCNTO0 REGL(0x150014)
-#define TCNTB1 REGL(0x150018)
-#define TCMPB1 REGL(0x15001c)
-#define TCNTO1 REGL(0x150020)
-#define TCNTB2 REGL(0x150024)
-#define TCMPB2 REGL(0x150028)
-#define TCNTO2 REGL(0x15002c)
-#define TCNTB3 REGL(0x150030)
-#define TCMPB3 REGL(0x150034)
-#define TCNTO3 REGL(0x150038)
-#define TCNTB4 REGL(0x15003c)
-#define TCMPB4 REGL(0x150040)
-#define TCNTO4 REGL(0x150044)
-#define TCNTB5 REGL(0x150048)
-#define TCNTO5 REGL(0x15004c)
-
-/*********************/
-/* IIC Registers */
-/*********************/
-
-#define IICCON REGL(0x160000)
-#define IICSTAT REGL(0x160004)
-#define IICADD REGL(0x160008)
-#define IICDS REGL(0x16000c)
-
-/*********************/
-/* RTC Registers */
-/*********************/
-
-#define RTCCON REGB(0x170040)
-#define RTCALM REGB(0x170050)
-#define ALMSEC REGB(0x170054)
-#define ALMMIN REGB(0x170058)
-#define ALMHOUR REGB(0x17005c)
-#define ALMDAY REGB(0x170060)
-#define ALMMON REGB(0x170064)
-#define ALMYEAR REGB(0x170068)
-#define RTCRST REGB(0x17006c)
-#define BCDSEC REGB(0x170070)
-#define BCDMIN REGB(0x170074)
-#define BCDHOUR REGB(0x170078)
-#define BCDDAY REGB(0x17007c)
-#define BCDDATE REGB(0x170080)
-#define BCDMON REGB(0x170084)
-#define BCDYEAR REGB(0x170088)
-#define TICINT REGB(0x17008c)
-
-/*********************************/
-/* Clock & Power Registers */
-/*********************************/
-
-#define PLLCON REGL(0x180000)
-#define CLKCON REGL(0x180004)
-#define CLKSLOW REGL(0x180008)
-#define LOCKTIME REGL(0x18000c)
-
-/**************************************/
-/* Interrupt Controller Registers */
-/**************************************/
-
-#define INTCON REGL(0x200000)
-#define INTPND REGL(0x200004)
-#define INTMOD REGL(0x200008)
-#define INTMSK REGL(0x20000c)
-#define I_PSLV REGL(0x200010)
-#define I_PMST REGL(0x200014)
-#define I_CSLV REGL(0x200018)
-#define I_CMST REGL(0x20001c)
-#define I_ISPR REGL(0x200020)
-#define I_ISPC REGL(0x200024)
-#define F_ISPR REGL(0x200038)
-#define F_ISPC REGL(0x20003c)
-
-/********************************/
-/* LCD Controller Registers */
-/********************************/
-
-#define LCDCON1 REGL(0x300000)
-#define LCDCON2 REGL(0x300004)
-#define LCDSADDR1 REGL(0x300008)
-#define LCDSADDR2 REGL(0x30000c)
-#define LCDSADDR3 REGL(0x300010)
-#define REDLUT REGL(0x300014)
-#define GREENLUT REGL(0x300018)
-#define BLUELUT REGL(0x30001c)
-#define DP1_2 REGL(0x300020)
-#define DP4_7 REGL(0x300024)
-#define DP3_5 REGL(0x300028)
-#define DP2_3 REGL(0x30002c)
-#define DP5_7 REGL(0x300030)
-#define DP3_4 REGL(0x300034)
-#define DP4_5 REGL(0x300038)
-#define DP6_7 REGL(0x30003c)
-#define LCDCON3 REGL(0x300040)
-#define DITHMODE REGL(0x300044)
-
-/*********************/
-/* DMA Registers */
-/*********************/
-
-#define ZDCON0 REGL(0x280000)
-#define ZDISRC0 REGL(0x280004)
-#define ZDIDES0 REGL(0x280008)
-#define ZDICNT0 REGL(0x28000c)
-#define ZDCSRC0 REGL(0x280010)
-#define ZDCDES0 REGL(0x280014)
-#define ZDCCNT0 REGL(0x280018)
-
-#define ZDCON1 REGL(0x280020)
-#define ZDISRC1 REGL(0x280024)
-#define ZDIDES1 REGL(0x280028)
-#define ZDICNT1 REGL(0x28002c)
-#define ZDCSRC1 REGL(0x280030)
-#define ZDCDES1 REGL(0x280034)
-#define ZDCCNT1 REGL(0x280038)
-
-#define BDCON0 REGL(0x380000)
-#define BDISRC0 REGL(0x380004)
-#define BDIDES0 REGL(0x380008)
-#define BDICNT0 REGL(0x38000c)
-#define BDCSRC0 REGL(0x380010)
-#define BDCDES0 REGL(0x380014)
-#define BDCCNT0 REGL(0x380018)
-
-#define BDCON1 REGL(0x380020)
-#define BDISRC1 REGL(0x380024)
-#define BDIDES1 REGL(0x380028)
-#define BDICNT1 REGL(0x38002c)
-#define BDCSRC1 REGL(0x380030)
-#define BDCDES1 REGL(0x380034)
-#define BDCCNT1 REGL(0x380038)
-
-
-#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n))
-#define INT_ENABLE(n) INTMSK &= ~(1<<(n))
-#define INT_DISABLE(n) INTMSK |= (1<<(n))
-
-#define HARD_RESET_NOW()
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 009863b..55a4e26 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -16,7 +16,7 @@ enum dma_data_direction {
static void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
- *handle = (unsigned long)malloc(len);
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
return (void *)*handle;
}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 79a9597..e126436 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -47,6 +47,6 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 5e2f027..61fee9f 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -310,12 +310,6 @@ struct prcm_regs {
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
- u32 prm_sldo_core_setup;
- u32 prm_sldo_core_ctrl;
- u32 prm_sldo_mpu_setup;
- u32 prm_sldo_mpu_ctrl;
- u32 prm_sldo_mm_setup;
- u32 prm_sldo_mm_ctrl;
u32 prm_abbldo_mpu_setup;
u32 prm_abbldo_mpu_ctrl;
generated by cgit v1.1 at 2024-11-01 03:43:45 +0000