diff options
Diffstat (limited to 'arch/arm/include/asm/arch-pxa')
| -rw-r--r-- | arch/arm/include/asm/arch-pxa/pxa-regs.h | 48 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-pxa/pxa.h | 29 |
2 files changed, 53 insertions, 24 deletions
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 52c79a9..8527c68 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -109,7 +109,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ @@ -126,7 +126,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define DCSR(x) (0x40000000 | ((x) << 2)) @@ -134,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ -#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ @@ -438,7 +438,7 @@ typedef void (*ExcpHndlr) (void) ; /* * USB Device Controller */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define UDCCR 0x40600000 /* UDC Control Register */ #define UDCCR_UDE (1 << 0) /* UDC enable */ @@ -797,9 +797,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) #define UDC_BCR_MASK (0x3ff) -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) /******************************************************************************/ /* @@ -870,7 +870,7 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR_CPVPE (1<<1) #define UP2OCR_CPVEN (1<<0) -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ; #define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ #define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ #define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ #define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ @@ -951,7 +951,7 @@ typedef void (*ExcpHndlr) (void) ; #define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ #define OMCR11 0x40A000DC /* OS Match Control Register 11 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ @@ -1052,7 +1052,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #endif #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ @@ -1071,7 +1071,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ #endif @@ -1087,7 +1087,7 @@ typedef void (*ExcpHndlr) (void) ; #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ -#if !defined(CONFIG_PXA27X) +#if !defined(CONFIG_CPU_PXA27X) #define CCCR_L09 (0x1F) #define CCCR_L27 (0x1) #define CCCR_L32 (0x2) @@ -1120,7 +1120,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ #define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ #define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ #define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ @@ -1128,7 +1128,7 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ #define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ #define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /* * Interrupt Controller @@ -1140,14 +1140,14 @@ typedef void (*ExcpHndlr) (void) ; #define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ #define ICCR 0x40D00014 /* Interrupt Controller Control Register */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ #define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ #define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ #define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ #define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ /******************************************************************************/ /* @@ -1188,7 +1188,7 @@ typedef void (*ExcpHndlr) (void) ; #define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ #define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ #define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ #define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ @@ -1198,7 +1198,7 @@ typedef void (*ExcpHndlr) (void) ; #define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ #define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ #define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_CPU_MONAHANS #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ @@ -1244,7 +1244,7 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) #define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) #define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) #define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) #define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) @@ -2123,7 +2123,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR0_PDD_S 12 #define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ @@ -2249,7 +2249,7 @@ typedef void (*ExcpHndlr) (void) ; #define LCSR1_IU6 (1 << 29) #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define LDCMD_SOFINT (1 << 22) #define LDCMD_EOFINT (1 << 21) #endif @@ -2480,7 +2480,7 @@ typedef void (*ExcpHndlr) (void) ; #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_CPU_PXA27X) #define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ @@ -2494,7 +2494,7 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ /* LCD registers */ #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ @@ -2628,6 +2628,6 @@ typedef void (*ExcpHndlr) (void) ; #define OSCR4 0x40A00040 /* OS Timer Counter Register */ #define OMCR4 0x40A000C0 /* */ -#endif /* CONFIG_PXA27X */ +#endif /* CONFIG_CPU_PXA27X */ #endif /* _PXA_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h new file mode 100644 index 0000000..49c6552 --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/pxa.h @@ -0,0 +1,29 @@ +/* + * PXA common functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PXA_H__ +#define __PXA_H__ + +int cpu_is_pxa25x(void); +int cpu_is_pxa27x(void); +void pxa2xx_dram_init(void); + +#endif /* __PXA_H__ */ |