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-rw-r--r--arch/arm/cpu/arm926ejs/Makefile11
-rw-r--r--arch/arm/cpu/arm926ejs/cache.c5
-rw-r--r--arch/arm/cpu/armv7m/stm32f4/flash.c5
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c2
4 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 63fa159..fe78922 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
+
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e5c1a6a..2839c86 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -82,4 +82,9 @@ void flush_dcache_all(void)
/*
* Stub implementations for l2 cache operations
*/
+
__weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c
index e5c6111..dd058bd 100644
--- a/arch/arm/cpu/armv7m/stm32f4/flash.c
+++ b/arch/arm/cpu/armv7m/stm32f4/flash.c
@@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
;
+ /* clear old sector number before writing a new one */
+ clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
+
if (bank == 0) {
setbits_le32(&STM32_FLASH->cr,
(i << STM32_FLASH_CR_SNB_OFFSET));
@@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last)
;
clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
- stm32f4_flash_lock(1);
}
+ stm32f4_flash_lock(1);
return 0;
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index b1ea822..1ece6a2 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
}
/* to activate the MMU we need to set up virtual memory */
-static void mmu_setup(void)
+__weak void mmu_setup(void)
{
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;