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-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c33
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c52
-rw-r--r--arch/arm/cpu/armv7/imx-common/Makefile4
-rw-r--r--arch/arm/cpu/armv7/imx-common/i2c.c99
-rw-r--r--arch/arm/cpu/armv7/imx-common/iomux-v3.c (renamed from arch/arm/cpu/armv7/mx6/iomux-v3.c)3
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c20
-rw-r--r--arch/arm/cpu/armv7/mx6/Makefile2
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c20
8 files changed, 229 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..f7829b2 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void)
writel(cfg, &clk->div_lcd0);
}
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long aclk_66, aclk_66_pre, sclk;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(MPLL);
+
+ ratio = (readl(&clk->div_top1)) >> 24;
+ ratio &= 0x7;
+ aclk_66_pre = sclk / (ratio + 1);
+ ratio = readl(&clk->div_top0);
+ ratio &= 0x7;
+ aclk_66 = aclk_66_pre / (ratio + 1);
+ return aclk_66;
+}
+
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@@ -594,6 +617,16 @@ unsigned long get_arm_clk(void)
return exynos4_get_arm_clk();
}
+unsigned long get_i2c_clk(void)
+{
+ if (cpu_is_exynos5()) {
+ return exynos5_get_i2c_clk();
+ } else {
+ debug("I2C clock is not set for this CPU\n");
+ return 0;
+ }
+}
+
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index d2b7d2c..d28f055 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -184,6 +184,48 @@ static void exynos5_sromc_config(int flags)
}
}
+static void exynos5_i2c_config(int peripheral, int flags)
+{
+
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -201,6 +243,16 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SROMC:
exynos5_sromc_config(flags);
break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos5_i2c_config(peripheral, flags);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/cpu/armv7/imx-common/Makefile
index e5ff375..bf36be5 100644
--- a/arch/arm/cpu/armv7/imx-common/Makefile
+++ b/arch/arm/cpu/armv7/imx-common/Makefile
@@ -27,7 +27,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
-COBJS = timer.o cpu.o speed.o
+COBJS-y = iomux-v3.o timer.o cpu.o speed.o
+COBJS-$(CONFIG_I2C_MXC) += i2c.o
+COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c b/arch/arm/cpu/armv7/imx-common/i2c.c
new file mode 100644
index 0000000..da2b26f
--- /dev/null
+++ b/arch/arm/cpu/armv7/imx-common/i2c.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <watchdog.h>
+
+static int force_idle_bus(void *priv)
+{
+ int i;
+ int sda, scl;
+ ulong elapsed, start_time;
+ struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
+ int ret = 0;
+
+ gpio_direction_input(p->sda.gp);
+ gpio_direction_input(p->scl.gp);
+
+ imx_iomux_v3_setup_pad(p->sda.gpio_mode);
+ imx_iomux_v3_setup_pad(p->scl.gpio_mode);
+
+ sda = gpio_get_value(p->sda.gp);
+ scl = gpio_get_value(p->scl.gp);
+ if ((sda & scl) == 1)
+ goto exit; /* Bus is idle already */
+
+ printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
+ sda, scl, p->sda.gp, p->scl.gp);
+ /* Send high and low on the SCL line */
+ for (i = 0; i < 9; i++) {
+ gpio_direction_output(p->scl.gp, 0);
+ udelay(50);
+ gpio_direction_input(p->scl.gp);
+ udelay(50);
+ }
+ start_time = get_timer(0);
+ for (;;) {
+ sda = gpio_get_value(p->sda.gp);
+ scl = gpio_get_value(p->scl.gp);
+ if ((sda & scl) == 1)
+ break;
+ WATCHDOG_RESET();
+ elapsed = get_timer(start_time);
+ if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
+ ret = -EBUSY;
+ printf("%s: failed to clear bus, sda=%d scl=%d\n",
+ __func__, sda, scl);
+ break;
+ }
+ }
+exit:
+ imx_iomux_v3_setup_pad(p->sda.i2c_mode);
+ imx_iomux_v3_setup_pad(p->scl.i2c_mode);
+ return ret;
+}
+
+static void * const i2c_bases[] = {
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+#ifdef I2C3_BASE_ADDR
+ (void *)I2C3_BASE_ADDR,
+#endif
+};
+
+/* i2c_index can be from 0 - 2 */
+void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+ struct i2c_pads_info *p)
+{
+ if (i2c_index >= ARRAY_SIZE(i2c_bases))
+ return;
+ /* Enable i2c clock */
+ enable_i2c_clk(1, i2c_index);
+ /* Make sure bus is idle */
+ force_idle_bus(p);
+ bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
+ force_idle_bus, p);
+}
diff --git a/arch/arm/cpu/armv7/mx6/iomux-v3.c b/arch/arm/cpu/armv7/imx-common/iomux-v3.c
index 8785532..da093fb 100644
--- a/arch/arm/cpu/armv7/mx6/iomux-v3.c
+++ b/arch/arm/cpu/armv7/imx-common/iomux-v3.c
@@ -23,8 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx6x_pins.h>
-#include <asm/arch/iomux-v3.h>
+#include <asm/imx-common/iomux-v3.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 64862b3..c67c3cf 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -117,6 +117,26 @@ void enable_usboh3_clk(unsigned char enable)
writel(reg, &mxc_ccm->CCGR2);
}
+#ifdef CONFIG_I2C_MXC
+/* i2c_num can be from 0 - 2 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 reg;
+ u32 mask;
+
+ if (i2c_num > 2)
+ return -EINVAL;
+ mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
+ reg = __raw_readl(&mxc_ccm->CCGR1);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &mxc_ccm->CCGR1);
+ return 0;
+}
+#endif
+
void set_usb_phy1_clk(void)
{
unsigned int reg;
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index b0da028..cbce411 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS = soc.o clock.o iomux-v3.o
+COBJS = soc.o clock.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 52d5dc4..fddb373 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -50,6 +50,26 @@ void enable_usboh3_clk(unsigned char enable)
}
+#ifdef CONFIG_I2C_MXC
+/* i2c_num can be from 0 - 2 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 reg;
+ u32 mask;
+
+ if (i2c_num > 2)
+ return -EINVAL;
+ mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+ return 0;
+}
+#endif
+
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;