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Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r--arch/arm/cpu/armv8/cache.S2
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c6
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index d846236..ab8c089 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -112,7 +112,7 @@ ENDPROC(__asm_flush_dcache_all)
ENTRY(__asm_invalidate_dcache_all)
mov x16, lr
- mov x0, #0xffff
+ mov x0, #0x1
bl __asm_dcache_all
mov lr, x16
ret
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6bde1cf..b1ea822 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -59,15 +59,15 @@ static void mmu_setup(void)
el = current_el();
if (el == 1) {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL1_IPS_BITS,
+ TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
MEMORY_ATTRIBUTES);
} else if (el == 2) {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL2_IPS_BITS,
+ TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
MEMORY_ATTRIBUTES);
} else {
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL3_IPS_BITS,
+ TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
MEMORY_ATTRIBUTES);
}
/* enable the mmu */