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-rw-r--r--arch/arm/cpu/armv7/mx5/Makefile (renamed from arch/arm/cpu/armv7/mx51/Makefile)0
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c (renamed from arch/arm/cpu/armv7/mx51/clock.c)42
-rw-r--r--arch/arm/cpu/armv7/mx5/iomux.c (renamed from arch/arm/cpu/armv7/mx51/iomux.c)2
-rw-r--r--arch/arm/cpu/armv7/mx5/lowlevel_init.S (renamed from arch/arm/cpu/armv7/mx51/lowlevel_init.S)14
-rw-r--r--arch/arm/cpu/armv7/mx5/soc.c (renamed from arch/arm/cpu/armv7/mx51/soc.c)28
-rw-r--r--arch/arm/cpu/armv7/mx5/speed.c (renamed from arch/arm/cpu/armv7/mx51/speed.c)0
-rw-r--r--arch/arm/cpu/armv7/mx5/timer.c (renamed from arch/arm/cpu/armv7/mx51/timer.c)8
-rw-r--r--arch/arm/cpu/armv7/mx5/u-boot.lds (renamed from arch/arm/cpu/armv7/mx51/u-boot.lds)0
-rw-r--r--arch/arm/cpu/armv7/start.S131
-rw-r--r--arch/arm/cpu/armv7/u-boot.lds7
10 files changed, 128 insertions, 104 deletions
diff --git a/arch/arm/cpu/armv7/mx51/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index 7cfaa2c..7cfaa2c 100644
--- a/arch/arm/cpu/armv7/mx51/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
diff --git a/arch/arm/cpu/armv7/mx51/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index a27227d..00f649c 100644
--- a/arch/arm/cpu/armv7/mx51/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
return freq / (reg + 1);
}
@@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
reg = __raw_readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
reg = __raw_readl(&mxc_ccm->cbcmr);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
default:
return 0;
}
@@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
case 0x0:
freq = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
default:
return 66500000;
@@ -181,7 +181,7 @@ u32 get_lp_apm(void)
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_MX51_HCLK_FREQ;
+ ret_val = CONFIG_SYS_MX5_HCLK;
else
ret_val = ((32768 * 1024));
@@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
switch (clk_sel) {
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
@@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return imx_get_cspiclk();
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
default:
break;
}
@@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
/*
* Dump some core clockes.
*/
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u32 freq;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll1: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll2: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll3: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll1: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll2: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll3: %dMHz\n", freq / 1000000);
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
@@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
/***************************************************/
U_BOOT_CMD(
- clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
- "display mx51 clocks\n",
+ clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
+ "display clocks\n",
""
);
diff --git a/arch/arm/cpu/armv7/mx51/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
index 62b2954..e8928d5 100644
--- a/arch/arm/cpu/armv7/mx51/iomux.c
+++ b/arch/arm/cpu/armv7/mx5/iomux.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/cpu/armv7/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 783c81f..e984870 100644
--- a/arch/arm/cpu/armv7/mx51/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -257,20 +257,6 @@ lowlevel_init:
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
init_l2cc
init_aips
diff --git a/arch/arm/cpu/armv7/mx51/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index f22ebe9..7c7a565 100644
--- a/arch/arm/cpu/armv7/mx51/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -33,28 +33,33 @@
#include <fsl_esdhc.h>
#endif
+#if defined(CONFIG_MX51)
+#define CPU_TYPE 0x51000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
u32 get_cpu_rev(void)
{
- int reg;
- int system_rev;
+ int system_rev = CPU_TYPE;
+ int reg = __raw_readl(ROM_SI_REV);
- reg = __raw_readl(ROM_SI_REV);
switch (reg) {
case 0x02:
- system_rev = 0x51000 | CHIP_REV_1_1;
+ system_rev |= CHIP_REV_1_1;
break;
case 0x10:
if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev = 0x51000 | CHIP_REV_2_5;
+ system_rev |= CHIP_REV_2_5;
else
- system_rev = 0x51000 | CHIP_REV_2_0;
+ system_rev |= CHIP_REV_2_0;
break;
case 0x20:
- system_rev = 0x51000 | CHIP_REV_3_0;
+ system_rev |= CHIP_REV_3_0;
break;
return system_rev;
default:
- system_rev = 0x51000 | CHIP_REV_1_0;
+ system_rev |= CHIP_REV_1_0;
break;
}
return system_rev;
@@ -67,9 +72,10 @@ int print_cpuinfo(void)
u32 cpurev;
cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
- (cpurev & 0xF0) >> 4,
- (cpurev & 0x0F) >> 4,
+ printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
return 0;
}
diff --git a/arch/arm/cpu/armv7/mx51/speed.c b/arch/arm/cpu/armv7/mx5/speed.c
index a444def..a444def 100644
--- a/arch/arm/cpu/armv7/mx51/speed.c
+++ b/arch/arm/cpu/armv7/mx5/speed.c
diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx5/timer.c
index 110edbf..3044fcf 100644
--- a/arch/arm/cpu/armv7/mx51/timer.c
+++ b/arch/arm/cpu/armv7/mx5/timer.c
@@ -75,18 +75,18 @@ void reset_timer(void)
void reset_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+ lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
- val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+ val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
if (val >= lastinc)
timestamp += (val - lastinc);
else
- timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
+ timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
return timestamp;
@@ -106,7 +106,7 @@ void set_timer(ulong t)
void __udelay(unsigned long usec)
{
unsigned long now, start, tmo;
- tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
+ tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
if (!tmo)
tmo = 1;
diff --git a/arch/arm/cpu/armv7/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx5/u-boot.lds
index 55d6599..55d6599 100644
--- a/arch/arm/cpu/armv7/mx51/u-boot.lds
+++ b/arch/arm/cpu/armv7/mx5/u-boot.lds
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 26f335a..64c86e9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -78,13 +78,13 @@ _armboot_start:
/*
* These are defined in the board-specific linker script.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@@ -104,29 +104,29 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
+.globl _datarel_start_ofs
+_datarel_start_ofs:
+ .word __datarel_start - _start
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
+.globl _datarelrolocal_start_ofs
+_datarelrolocal_start_ofs:
+ .word __datarelrolocal_start - _start
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
+.globl _datarellocal_start_ofs
+_datarellocal_start_ofs:
+ .word __datarellocal_start - _start
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
+.globl _datarelro_start_ofs
+_datarelro_start_ofs:
+ .word __datarelro_start - _start
-.globl _got_start
-_got_start:
- .word __got_start
+.globl _got_start_ofs
+_got_start_ofs:
+ .word __got_start - _start
-.globl _got_end
-_got_end:
- .word __got_end
+.globl _got_end_Ofs
+_got_end_ofs:
+ .word __got_end - _start
/*
* the actual reset code
@@ -198,9 +198,8 @@ stack_setup:
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
adr r0, _start
ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
#ifndef CONFIG_PRELOADER
beq jump_2_ram
@@ -213,33 +212,51 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r7, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r8, r1, #0xff
+ cmp r8, #23 /* relative fixup? */
+ beq fixrel
+ cmp r8, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
clear_bss:
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
- sub r0, r0, r3
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@@ -255,18 +272,26 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
jump_2_ram:
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add r0, r0, r1
+ add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
+
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
+
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index d4fd3fc..88a0fec 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -53,6 +53,13 @@ SECTIONS
__datarelro_start = .;
*(.data.rel.ro)
}
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rel.dyn : { *(.rel.dyn) }
+ __rel_dyn_end = .;
+
+ __dynsym_start = .;
+ .dynsym : { *(.dynsym) }
__got_start = .;
. = ALIGN(4);
generated by cgit v1.1 at 2024-08-24 18:50:02 +0000