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Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c43
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c25
2 files changed, 64 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index e3ca4f6..effe457 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -362,10 +362,34 @@ void enable_qspi_clk(int qspi_num)
}
}
+
+void enable_enet_clock(void)
+{
+ u32 reg = 0;
+
+ /* set enet ahb clock 200Mhz
+ * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
+ */
+ reg = __raw_readl(&imx_ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
+ | MXC_CCM_CHSCCDR_ENET_PODF_MASK | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
+ /* PLL2 PFD2 */
+ reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
+ /* Div = 2*/
+ reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
+ reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
+ writel(reg, &imx_ccm->chsccdr);
+
+ /* Enable enet system clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_ENET_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+}
+
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
@@ -378,7 +402,14 @@ int enable_fec_anatop_clock(enum enet_freq freq)
reg = readl(&anatop->pll_enet);
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= freq;
+
+ if (0 == fec_id) {
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+ } else {
+ reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+ }
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
@@ -393,8 +424,14 @@ int enable_fec_anatop_clock(enum enet_freq freq)
}
/* Enable FEC clock */
- reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ if (0 == fec_id)
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ else
+ reg |= BM_ANADIG_PLL_ENET2_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+#endif
writel(reg, &anatop->pll_enet);
return 0;
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 88cb2bb..b31ad04 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -480,6 +480,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
+#ifdef CONFIG_MX6SX
+ if (0 == dev_id) {
+ u32 value = readl(&fuse->mac_addr1);
+ mac[0] = (value >> 8);
+ mac[1] = value ;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24 ;
+ mac[3] = value >> 16 ;
+ mac[4] = value >> 8 ;
+ mac[5] = value ;
+ } else {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24 ;
+ mac[1] = value >> 16 ;
+ mac[2] = value >> 8 ;
+ mac[3] = value ;
+
+ value = readl(&fuse->mac_addr1);
+ mac[4] = value >> 24 ;
+ mac[5] = value >> 16 ;
+ }
+#else
u32 value = readl(&fuse->mac_addr_high);
mac[0] = (value >> 8);
mac[1] = value ;
@@ -489,7 +512,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
mac[3] = value >> 16 ;
mac[4] = value >> 8 ;
mac[5] = value ;
-
+#endif
}
#endif