diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/flash_header.S | 71 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/lowlevel_init.S | 67 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/mx53_evk.c | 6 | ||||
| -rw-r--r-- | include/configs/mx53_arm2.h | 238 | ||||
| -rw-r--r-- | include/configs/mx53_evk.h | 8 |
6 files changed, 354 insertions, 37 deletions
@@ -3255,6 +3255,7 @@ mx51_3stack_android_config \ mx51_3stack_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51 +mx53_arm2_config \ mx53_evk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53 diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S index 459c01e..38497c8 100644 --- a/board/freescale/mx53_evk/flash_header.S +++ b/board/freescale/mx53_evk/flash_header.S @@ -52,6 +52,7 @@ boot_data: .word 0x77800000 image_len: .word 256 * 1024 plugin: .word 0x0 +#ifdef CONFIG_MX53_EVK dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */ @@ -120,4 +121,74 @@ MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x01c, 0x00468039) MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x020, 0x00005800) MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x058, 0x00033337) MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) + +#else /*ARM2 board*/ +dcd_hdr: .word 0x400002D2 /* Tag=0xD2, Len=63*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04FC01CC /* Tag=0xCC, Len=63*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00380000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00380000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x02000000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000) +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2d313331) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x020c0211) +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x014c0155) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4110000) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2) +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e) +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031) +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00468031) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039) +MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138) +MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038) +MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039) +MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00468039) +MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033337) +MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) +#endif #endif diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S index c67c584..d5e9f66 100644 --- a/board/freescale/mx53_evk/lowlevel_init.S +++ b/board/freescale/mx53_evk/lowlevel_init.S @@ -58,24 +58,27 @@ .endm /* init_aips */ .macro setup_pll pll, freq - ldr r2, =\pll + ldr r0, =\pll ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + str r1, [r0, #PLL_DP_CTL] mov r1, #0x2 - str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + str r1, [r0, #PLL_DP_CONFIG] - str r3, [r2, #PLL_DP_OP] - str r3, [r2, #PLL_DP_HFS_OP] + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] - str r4, [r2, #PLL_DP_MFD] - str r4, [r2, #PLL_DP_HFS_MFD] + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] - str r5, [r2, #PLL_DP_MFN] - str r5, [r2, #PLL_DP_HFS_MFN] + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] -1: ldr r1, [r2, #PLL_DP_CTL] + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b .endm @@ -87,14 +90,8 @@ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] - mov r3, #DP_OP_800 - mov r4, #DP_MFD_800 - mov r5, #DP_MFN_800 setup_pll PLL1_BASE_ADDR, 800 - mov r3, #DP_OP_400 - mov r4, #DP_MFD_400 - mov r5, #DP_MFN_400 setup_pll PLL3_BASE_ADDR, 400 /* Switch peripheral to PLL3 */ @@ -102,36 +99,31 @@ ldr r1, CCM_VAL_0x00015154 str r1, [r0, #CLKCTL_CBCMR] ldr r1, CCM_VAL_0x02888945 - orr r1, r1, #(1 << 16) /* Set DDR divider to run at 200MHz */ + orr r1, r1, #(1 << 16) str r1, [r0, #CLKCTL_CBCDR] - /* make sure mux & divider change is effective */ + /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b - mov r3, #DP_OP_600 - mov r4, #DP_MFD_600 - mov r5, #DP_MFN_600 - setup_pll PLL2_BASE_ADDR, 600 + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ /* Switch peripheral to PLL2 */ ldr r0, CCM_BASE_ADDR_W - ldr r1, CCM_VAL_0x00809145 /* AHB is 120MHz, from PLL2 */ - orr r1, r1, #(1 << 16) /* Set DDR divider to run at 300MHz */ - orr r1, r1, #(2 << 19) /* Set AXI_B divider to run at 200MHz */ + ldr r1, CCM_VAL_0x00808145 + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10) + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16) + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19) str r1, [r0, #CLKCTL_CBCDR] ldr r1, CCM_VAL_0x00016154 str r1, [r0, #CLKCTL_CBCMR] - /* make sure mux change is effective */ + /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b - mov r3, #DP_OP_216 - mov r4, #DP_MFD_216 - mov r5, #DP_MFN_216 setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ @@ -139,7 +131,6 @@ ldr r1, PLATFORM_CLOCK_DIV_W str r1, [r0, #PLATFORM_ICGC] - /* CPU 400M hz */ ldr r0, CCM_BASE_ADDR_W mov r1, #1 str r1, [r0, #CLKCTL_CACRR] @@ -209,8 +200,20 @@ lowlevel_init: /* Board level setting value */ CCM_BASE_ADDR_W: .word CCM_BASE_ADDR CCM_VAL_0x00016154: .word 0x00016154 -CCM_VAL_0x00809145: .word 0x00809145 +CCM_VAL_0x00808145: .word 0x00808145 CCM_VAL_0x00015154: .word 0x00015154 CCM_VAL_0x02888945: .word 0x02888945 +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_600: .word DP_OP_600 +W_DP_MFD_600: .word DP_MFD_600 +W_DP_MFN_600: .word DP_MFN_600 +W_DP_OP_400: .word DP_OP_400 +W_DP_MFD_400: .word DP_MFD_400 +W_DP_MFN_400: .word DP_MFN_400 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR PLATFORM_CLOCK_DIV_W: .word 0x00000124 diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c index 9661df6..9526b2d 100644 --- a/board/freescale/mx53_evk/mx53_evk.c +++ b/board/freescale/mx53_evk/mx53_evk.c @@ -107,7 +107,7 @@ static inline void setup_soc_rev(void) system_rev = 0x53000 | CHIP_REV_1_0; } -static inline void set_board_rev(int rev) +static inline void setup_board_rev(int rev) { system_rev |= (rev & 0xF) << 8; } @@ -495,7 +495,9 @@ int board_init(void) { setup_boot_device(); setup_soc_rev(); - +#ifdef CONFIG_MX53_ARM2 + setup_board_rev(1); +#endif gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */ /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; diff --git a/include/configs/mx53_arm2.h b/include/configs/mx53_arm2.h new file mode 100644 index 0000000..5517459 --- /dev/null +++ b/include/configs/mx53_arm2.h @@ -0,0 +1,238 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-ARM2 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx53.h> + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX53 +#define CONFIG_MX53_ARM2 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MX53_UART 1 +#define CONFIG_MX53_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "ARM2 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR -1 +#define CONFIG_FEC0_MIIBASE -1 + +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 +#endif +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h index b327a92..85bd02f 100644 --- a/include/configs/mx53_evk.h +++ b/include/configs/mx53_evk.h @@ -26,8 +26,6 @@ /* High Level Configuration Options */ #define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ -#define CONFIG_SYS_APCS_GNU - #define CONFIG_MXC #define CONFIG_MX53 #define CONFIG_MX53_EVK @@ -39,7 +37,11 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MMU -#define CONFIG_MX53_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 600 +#define CONFIG_SYS_AHB_PODF 4 +#define CONFIG_SYS_AXIA_PODF 1 +#define CONFIG_SYS_AXIB_PODF 2 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO |