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-rw-r--r--arch/arm/include/asm/system.h4
-rw-r--r--arch/arm/lib/cache-cp15.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 67cbbc2..ab73821 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -259,7 +259,7 @@ static inline void set_dacr(unsigned int val)
isb();
}
-#ifdef CONFIG_ARMV7
+#ifdef CONFIG_CPU_V7
/* Short-Descriptor Translation Table Level 1 Bits */
#define TTB_SECT_NS_MASK (1 << 19)
#define TTB_SECT_NG_MASK (1 << 17)
@@ -296,7 +296,7 @@ enum {
MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
};
-#ifdef CONFIG_ARMV7
+#ifdef CONFIG_CPU_V7
/* TTBR0 bits */
#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
#define TTBR0_RGN_NC (0 << 3)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index c65e068..8e18538 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -96,7 +96,7 @@ static inline void mmu_setup(void)
dram_bank_mmu_setup(i);
}
-#ifdef CONFIG_ARMV7
+#ifdef CONFIG_CPU_V7
/* Set TTBR0 */
reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)