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-rw-r--r--board/freescale/mpc8548cds/law.c5
-rw-r--r--board/freescale/mpc8548cds/tlb.c9
-rw-r--r--include/configs/MPC8548CDS.h15
3 files changed, 13 insertions, 16 deletions
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index e59fee8..5b6943d 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -57,9 +57,6 @@ struct law_entry law_table[] = {
#endif
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 2267ad7..b2c1b31 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
-#endif
+
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4c5b998..ececa38 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007, 2010 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -40,10 +40,12 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
@@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
-#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
-#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
-#endif
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17