diff options
| -rw-r--r-- | CHANGELOG | 15 | ||||
| -rw-r--r-- | README | 2 | ||||
| -rw-r--r-- | board/incaip/memsetup.S | 183 | ||||
| -rw-r--r-- | common/cmd_pcmcia.c | 12 | ||||
| -rw-r--r-- | cpu/mips/incaip_clock.c | 15 | ||||
| -rw-r--r-- | cpu/mpc5xxx/speed.c | 10 | ||||
| -rw-r--r-- | include/common.h | 3 | ||||
| -rw-r--r-- | include/configs/Sandpoint8240.h | 2 | ||||
| -rw-r--r-- | include/configs/incaip.h | 9 | ||||
| -rw-r--r-- | lib_mips/board.c | 5 |
10 files changed, 191 insertions, 65 deletions
@@ -2,6 +2,21 @@ Changes since U-Boot 1.0.0: ====================================================================== +* Make CPU clock on ICA-IP board controllable by a "cpuclk" + environment variable which can set to "100", "133", or "150". The + CPU clock will be configured accordingly upon next reboot. Other + values are ignored. In case of an invalid or undefined "cpuclk" + value, the compile-time default CPU clock speed will be used. + +* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory + window that is used to access the UART registers by the Linux driver) + +* Patch by Reinhard Meyer, 20 Dec 2003: + Fix clock calculation for the MPC5200 for higher clock frequencies + (above 2**32 / 10 = 429.5 MHz). + +* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration + * Fix IceCube CLKIN configuration (it's 33.000000MHz) * Add new configuration for IceCube board with DDR memory @@ -3110,7 +3110,7 @@ int main (int argc, char *argv[]) while (learning) { Read the README file in the top level directory; - Read http://www.denx.de/re/DPLG.html + Read http://www.denx.de/twiki/bin/view/DULG/Manual ; Read the source, Luke; } diff --git a/board/incaip/memsetup.S b/board/incaip/memsetup.S index 245ab72..70d2885 100644 --- a/board/incaip/memsetup.S +++ b/board/incaip/memsetup.S @@ -55,63 +55,142 @@ #define CGU_MUXCR(value) 0x0014(value) #define CGU_PLL1SR(value) 0x000C(value) - .globl memsetup -memsetup: + .set noreorder - /* EBU Initialization for the Flash CS0 and CS2. - */ - li t0, EBU_MODUL_BASE - li t1, 0xA0000041 - sw t1, EBU_ADDSEL0(t0) +/* + * void ebu_init(long) + * + * a0 has the clock value we are going to run at + */ + .globl ebu_init + .ent ebu_init +ebu_init: + + li t1, EBU_MODUL_BASE + li t2, 0xA0000041 + sw t2, EBU_ADDSEL0(t1) + li t2, 0xA0800041 + sw t2, EBU_ADDSEL2(t1) + li t2, 0xBE0000F1 + sw t2, EBU_ADDSEL1(t1) + + li t3, 100000000 + beq a0, t3, 1f + nop + li t3, 133000000 + beq a0, t3, 2f + nop + li t3, 150000000 + beq a0, t3, 2f + nop + b 3f + nop -#if CPU_CLOCK_RATE==100000000 /* 100 MHz clock for the MIPS core */ - lw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */ - sw t1, EBU_BUSCON2(t0) -#else /* 150 MHz or 133 MHz */ - li t1, 0x8841417E - sw t1, EBU_BUSCON0(t0) - sw t1, EBU_BUSCON2(t0) -#endif + /* 100 MHz */ +1: + li t2, 0x8841417D + sw t2, EBU_BUSCON0(t1) + sw t2, EBU_BUSCON2(t1) + li t2, 0x684142BD + b 3f + sw t2, EBU_BUSCON1(t1) /* delay slot */ + + /* 133 or 150 MHz */ +2: + li t2, 0x8841417E + sw t2, EBU_BUSCON0(t1) + sw t2, EBU_BUSCON2(t1) + li t2, 0x684143FD + sw t2, EBU_BUSCON1(t1) +3: + j ra + nop + + .end ebu_init - li t1, 0xA0800041 - sw t1, EBU_ADDSEL2(t0) - /* Need to initialize CS1 too, so as to to prevent overlapping with - * Flash bank 1. +/* + * void cgu_init(long) + * + * a0 has the clock value + */ + .globl cgu_init + .ent cgu_init +cgu_init: + + li t1, CGU_MODUL_BASE + + li t3, 100000000 + beq a0, t3, 1f + nop + li t3, 133000000 + beq a0, t3, 2f + nop + li t3, 150000000 + beq a0, t3, 3f + nop + b 5f + nop + + /* 100 MHz clock */ +1: + li t2, 0x80000014 + sw t2, CGU_DIVCR(t1) + li t2, 0x80000000 + sw t2, CGU_MUXCR(t1) + li t2, 0x800B0001 + b 5f + sw t2, CGU_PLL1CR(t1) /* delay slot */ + + /* 133 MHz clock */ +2: + li t2, 0x80000054 + sw t2, CGU_DIVCR(t1) + li t2, 0x80000000 + sw t2, CGU_MUXCR(t1) + li t2, 0x800B0001 + b 5f + sw t2, CGU_PLL1CR(t1) /* delay slot */ + + /* 150 MHz clock */ +3: + li t2, 0x80000017 + sw t2, CGU_DIVCR(t1) + li t2, 0xC00B0001 + sw t2, CGU_PLL1CR(t1) + li t3, 0x80000000 +4: + lw t2, CGU_PLL1SR(t1) + and t2, t2, t3 + beq t2, zero, 4b + nop + li t2, 0x80000001 + sw t2, CGU_MUXCR(t1) +5: + j ra + nop + + .end cgu_init + + + .globl memsetup + .ent memsetup +memsetup: + + /* EBU and CGU Initialization. */ - li t1, 0xBE0000F1 - sw t1, EBU_ADDSEL1(t0) - -#if CPU_CLOCK_RATE==100000000 /* 100 MHz clock for the MIPS core */ - li t1, 0x684142BD -#else /* 150 MHz or 133 MHz */ - li t1, 0x684143FD -#endif - sw t1, EBU_BUSCON1(t0) - -#if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */ - li t0, CGU_MODUL_BASE - li t1, 0x80000017 - sw t1, CGU_DIVCR(t0) - li t1, 0xC00B0001 - sw t1, CGU_PLL1CR(t0) - lui t2, 0x8000 -b1: - lw t1, CGU_PLL1SR(t0) - and t1, t1, t2 - beq t1, zero, b1 - li t1, 0x80000001 - sw t1, CGU_MUXCR(t0) -#elif CPU_CLOCK_RATE==133000000 /* 133 MHz clock for the MIPS core */ - li t0, CGU_MODUL_BASE - li t1, 0x80000054 - sw t1, CGU_DIVCR(t0) - li t1, 0x80000000 - sw t1, CGU_MUXCR(t0) - li t1, 0x800B0001 - sw t1, CGU_PLL1CR(t0) -#endif + li a0, CPU_CLOCK_RATE + move t0, ra + + /* We rely on the fact that neither ebu_init() nor cgu_init() + * modify t0 and a0. + */ + bal ebu_init + nop + bal cgu_init + nop + move ra, t0 /* SDRAM Initialization. */ @@ -154,3 +233,5 @@ b1: j ra nop + .end memsetup + diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index 3d38d5c..1bd4bc5 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -227,6 +227,18 @@ int pcmcia_on (void) break; } #endif /* CONFIG_IDE_8xx_PCCARD */ +#ifdef CONFIG_BMS2003 + case 3: { /* map I/O window for 4xUART data/ctrl */ + win->br += 0x140000; + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_BMS2003 */ default: /* set to not valid */ win->or = 0; break; diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c index 27f0609..4ae06b7 100644 --- a/cpu/mips/incaip_clock.c +++ b/cpu/mips/incaip_clock.c @@ -102,3 +102,18 @@ uint incaip_get_fpiclk(void) break; } } + +int incaip_set_cpuclk(void) +{ + uchar tmp[64]; + ulong cpuclk; + + if (getenv_r("cpuclk", tmp, sizeof(tmp)) > 0) + { + cpuclk = simple_strtoul(tmp, NULL, 10) * 1000000; + ebu_init(cpuclk); + cgu_init(cpuclk); + } + + return 0; +} diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c index cb27779..4f4e814 100644 --- a/cpu/mpc5xxx/speed.c +++ b/cpu/mpc5xxx/speed.c @@ -30,10 +30,10 @@ /* Bus-to-Core Multipliers */ static int bus2core[] = { - 0, 0, 0, 10, 20, 20, 25, 45, - 30, 55, 40, 50, 0, 60, 35, 0, - 30, 25, 65, 10, 70, 20, 75, 45, - 0, 55, 40, 50, 80, 60, 35, 0 + 3, 2, 2, 2, 4, 4, 5, 9, + 6, 11, 8, 10, 3, 12, 7, 0, + 6, 5, 13, 2, 14, 4, 15, 9, + 0, 11, 8, 10, 16, 12, 7, 0 }; /* ------------------------------------------------------------------------- */ @@ -62,7 +62,7 @@ int get_clocks (void) } else { gd->bus_clk = vco / 4; } - gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 10; + gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2; val = *(vu_long *)MPC5XXX_CDM_CFG; if (val & (1 << 8)) { diff --git a/include/common.h b/include/common.h index 39c232a..ece5d64 100644 --- a/include/common.h +++ b/include/common.h @@ -362,6 +362,9 @@ ulong get_HCLK (void); ulong get_PCLK (void); ulong get_UCLK (void); #endif +#if defined CONFIG_INCA_IP +uint incaip_get_cpuclk (void); +#endif ulong get_bus_freq (ulong); #if defined(CONFIG_MPC85xx) diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index 5bf184e..1c37f63 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -269,7 +269,7 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 #define CFG_ROMNAL 7 /*rom/flash next access time */ #define CFG_ROMFAL 11 /*rom/flash access time */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 15d5c2e..e6fa193 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -36,12 +36,7 @@ #define CPU_CLOCK_RATE 133000000 /* 133 MHz clock for the MIPS core */ #endif -#if CPU_CLOCK_RATE == 100000000 -#define INFINEON_EBU_BOOTCFG 0x20C4 /* CMULT = 4 for 100 MHz */ -#else -#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 for 150 MHz */ -#endif - +#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -106,7 +101,7 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_HZ (incaip_get_cpuclk() / 2) #define CFG_SDRAM_BASE 0x80000000 diff --git a/lib_mips/board.c b/lib_mips/board.c index 3c8a2d2..0727095 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -41,6 +41,8 @@ extern int timer_init(void); +extern int incaip_set_cpuclk(void); + extern ulong uboot_end_data; extern ulong uboot_end; @@ -163,6 +165,9 @@ typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = { timer_init, env_init, /* initialize environment */ +#ifdef CONFIG_INCA_IP + incaip_set_cpuclk, /* set cpu clock according to environment variable */ +#endif init_baudrate, /* initialze baudrate settings */ serial_init, /* serial communications setup */ console_init_f, |