diff options
| -rw-r--r-- | arch/arm/mach-socfpga/spl.c | 3 | ||||
| -rw-r--r-- | configs/socfpga_arria5_defconfig | 3 | ||||
| -rw-r--r-- | configs/socfpga_cyclone5_defconfig | 3 | ||||
| -rw-r--r-- | configs/socfpga_socrates_defconfig | 3 | ||||
| -rw-r--r-- | include/configs/socfpga_common.h | 14 |
5 files changed, 20 insertions, 6 deletions
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 82570f8..13ec24b 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -178,5 +178,8 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); + /* Configure simple malloc base pointer into RAM. */ + gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); + board_init_r(NULL, 0); } diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index ee03156..4d1cd21 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -14,3 +14,6 @@ CONFIG_SPL_SIMPLE_BUS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 75ed347..ae3a1de 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -17,3 +17,6 @@ CONFIG_SPL_SIMPLE_BUS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 2e50ce9..71d4711 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -17,3 +17,6 @@ CONFIG_SPL_SIMPLE_BUS=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index bed8600..60a6025 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -39,10 +39,11 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET @@ -290,9 +291,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) #define CONFIG_SPL_MAX_SIZE (64 * 1024) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ #define CONFIG_CRC32_VERIFY |