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-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index febf96e..0375996 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -985,7 +985,7 @@ void v7_outer_cache_enable(void)
/* Turn on the L2 I/D prefetch, double linefill */
/* Set prefetch offset with any value except 23 as per errata 765569 */
- val |= 0x7000000f;
+ val |= 0x70000000;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0