summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--CHANGELOG6
-rw-r--r--board/csb472/init.S2
-rw-r--r--lib_m68k/time.c22
3 files changed, 29 insertions, 1 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 239c82a..73fb943 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,12 @@
Changes for U-Boot 1.1.3:
======================================================================
+* Patch by Mathias Küster, 23 Nov 2004:
+ add udelay support for the mcf5282 cpu
+
+* Patch by Tolunay Orkun, 16 November 2004:
+ fix incorrect onboard Xilinx CPLD base address
+
* Patch by Jerry Van Baren, 08 Nov 2004:
- Add low-boot option for MPC8260ADS board (if lowboot is selected,
the jumper for the HRCW source should select flash. If lowboot is
diff --git a/board/csb472/init.S b/board/csb472/init.S
index ca0241b..aec42a1 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -129,7 +129,7 @@ ext_bus_cntlr_init:
*******************************************************************/
/*WDCR_EBC(pb3ap, 0x07869200)*/
WDCR_EBC(pb3ap, 0x04055200)
- WDCR_EBC(pb3cr, 0xff01c000)
+ WDCR_EBC(pb3cr, 0xf081c000)
/********************************************************************
* Memory Bank 1,2,4-7 (Unused) initialization
*******************************************************************/
diff --git a/lib_m68k/time.c b/lib_m68k/time.c
index fb997b5..e2c1b06 100644
--- a/lib_m68k/time.c
+++ b/lib_m68k/time.c
@@ -131,6 +131,28 @@ void set_timer (ulong t)
void udelay(unsigned long usec)
{
+ volatile unsigned short *timerp;
+ uint tmp;
+
+ timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
+
+ while (usec > 0) {
+ if (usec > 65000)
+ tmp = 65000;
+ else
+ tmp = usec;
+ usec = usec - tmp;
+
+ /* Set up TIMER 3 as timebase clock */
+ timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
+ timerp[MCFTIMER_PMR] = 0;
+ /* set period to 1 us */
+ timerp[MCFTIMER_PCSR] =
+ (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
+
+ timerp[MCFTIMER_PMR] = tmp;
+ while (timerp[MCFTIMER_PCNTR] > 0);
+ }
}
void timer_init (void)