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-rw-r--r--drivers/mmc/fsl_esdhc.c17
-rw-r--r--include/fsl_esdhc.h1
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 85354e8..999b581 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -344,6 +344,20 @@ static int esdhc_init(struct mmc *mmc)
return ret;
}
+static void esdhc_reset(struct fsl_esdhc *regs)
+{
+ unsigned long timeout = 100; /* wait max 100 ms */
+
+ /* reset the controller */
+ esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+
+ /* hardware clears the bit when it is done */
+ while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
+ udelay(1000);
+ if (!timeout)
+ printf("MMC/SD: Reset never completed.\n");
+}
+
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc *regs;
@@ -358,6 +372,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
sprintf(mmc->name, "FSL_ESDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ /* First reset the eSDHC controller */
+ esdhc_reset(regs);
+
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 57a08cd..5f02018 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -39,6 +39,7 @@
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
+#define SYSCTL_RSTA 0x01000000
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)