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-rw-r--r--doc/device-tree-bindings/serial/sh.txt6
-rw-r--r--drivers/serial/serial_sh.c28
2 files changed, 34 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/serial/sh.txt b/doc/device-tree-bindings/serial/sh.txt
new file mode 100644
index 0000000..b23b135
--- /dev/null
+++ b/doc/device-tree-bindings/serial/sh.txt
@@ -0,0 +1,6 @@
+* Renesas SCI serial interface
+
+Required properties:
+- compatible: must be "renesas,scif" or "renesas,scifa"
+- reg: exactly one register range with length
+- clock: input clock frequency for the SCI unit
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 8693c1e..32b2bf0 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -17,6 +17,8 @@
#include <dm/platform_data/serial_sh.h>
#include "serial_sh.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
@@ -201,9 +203,35 @@ static const struct dm_serial_ops sh_serial_ops = {
.setbrg = sh_serial_setbrg,
};
+#ifdef CONFIG_OF_CONTROL
+static const struct udevice_id sh_serial_id[] ={
+ {.compatible = "renesas,scif", .data = PORT_SCIF},
+ {.compatible = "renesas,scifa", .data = PORT_SCIFA},
+ {}
+};
+
+static int sh_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sh_serial_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->base = addr;
+ plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+ plat->type = dev_get_driver_data(dev);
+ return 0;
+}
+#endif
+
U_BOOT_DRIVER(serial_sh) = {
.name = "serial_sh",
.id = UCLASS_SERIAL,
+ .of_match = of_match_ptr(sh_serial_id),
+ .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
+ .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
.probe = sh_serial_probe,
.ops = &sh_serial_ops,
.flags = DM_FLAG_PRE_RELOC,