diff options
| -rw-r--r-- | drivers/usb/host/xhci-omap.c | 60 | ||||
| -rw-r--r-- | drivers/usb/phy/omap_usb_phy.c | 18 | ||||
| -rw-r--r-- | include/configs/am43xx_evm.h | 1 | ||||
| -rw-r--r-- | include/configs/beagle_x15.h | 1 | ||||
| -rw-r--r-- | include/configs/dra7xx_evm.h | 1 |
5 files changed, 3 insertions, 78 deletions
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index 912b2bd..3a55208 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -34,66 +34,6 @@ inline int __board_usb_init(int index, enum usb_init_type init) int board_usb_init(int index, enum usb_init_type init) __attribute__((weak, alias("__board_usb_init"))); -static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) -{ - clrsetbits_le32(&dwc3_reg->g_ctl, - DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), - DWC3_GCTL_PRTCAPDIR(mode)); -} - -static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) -{ - /* Before Resetting PHY, put Core in Reset */ - setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); - - omap_reset_usb_phy(dwc3_reg); - - /* After PHYs are stable we can take Core out of reset state */ - clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); -} - -static int dwc3_core_init(struct dwc3 *dwc3_reg) -{ - u32 reg; - u32 revision; - unsigned int dwc3_hwparams1; - - revision = readl(&dwc3_reg->g_snpsid); - /* This should read as U3 followed by revision number */ - if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { - puts("this is not a DesignWare USB3 DRD Core\n"); - return -1; - } - - dwc3_core_soft_reset(dwc3_reg); - - dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); - - reg = readl(&dwc3_reg->g_ctl); - reg &= ~DWC3_GCTL_SCALEDOWN_MASK; - reg &= ~DWC3_GCTL_DISSCRAMBLE; - switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { - case DWC3_GHWPARAMS1_EN_PWROPT_CLK: - reg &= ~DWC3_GCTL_DSBLCLKGTNG; - break; - default: - debug("No power optimization available\n"); - } - - /* - * WORKAROUND: DWC3 revisions <1.90a have a bug - * where the device can fail to connect at SuperSpeed - * and falls back to high-speed mode which causes - * the device to enter a Connect/Disconnect loop - */ - if ((revision & DWC3_REVISION_MASK) < 0x190a) - reg |= DWC3_GCTL_U2RSTECN; - - writel(reg, &dwc3_reg->g_ctl); - - return 0; -} - static int omap_xhci_core_init(struct omap_xhci *omap) { int ret = 0; diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c index 63d9301..f9069c7 100644 --- a/drivers/usb/phy/omap_usb_phy.c +++ b/drivers/usb/phy/omap_usb_phy.c @@ -223,24 +223,6 @@ void usb_phy_power(int on) } #endif /* CONFIG_AM437X_USB2PHY2_HOST */ -void omap_reset_usb_phy(struct dwc3 *dwc3_reg) -{ - /* Assert USB3 PHY reset */ - setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Assert USB2 PHY reset */ - setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); - - mdelay(100); - - /* Clear USB3 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); - - /* Clear USB2 PHY reset */ - clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); - -} - void omap_enable_phy(struct omap_xhci *omap) { #ifdef CONFIG_OMAP_USB2PHY2_HOST diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 33e534a..ccdfb9c 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -110,6 +110,7 @@ #define CONFIG_CMD_USB #define CONFIG_USB_HOST #define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h index 17fdded..d38b7b5 100644 --- a/include/configs/beagle_x15.h +++ b/include/configs/beagle_x15.h @@ -68,6 +68,7 @@ /* USB xHCI HOST */ #define CONFIG_CMD_USB #define CONFIG_USB_HOST +#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index d84427d..0323c72 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -175,6 +175,7 @@ #define CONFIG_CMD_USB #define CONFIG_USB_HOST #define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_OMAP #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |