diff options
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f7/rcc.h | 26 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-stm32/stm32f7/clock.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-stm32/stm32f7/timer.c | 4 | ||||
| -rw-r--r-- | board/st/stm32f746-disco/stm32f746-disco.c | 3 |
5 files changed, 15 insertions, 30 deletions
diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h index 184c366..23eec5e 100644 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -8,32 +8,6 @@ #ifndef _STM32_RCC_H #define _STM32_RCC_H -#define RCC_CR 0x00 /* clock control */ -#define RCC_PLLCFGR 0x04 /* PLL configuration */ -#define RCC_CFGR 0x08 /* clock configuration */ -#define RCC_CIR 0x0C /* clock interrupt */ -#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */ -#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */ -#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */ -#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */ -#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */ -#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */ -#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */ -#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */ -#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */ -#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */ -#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */ -#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */ -#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */ -#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */ -#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */ -#define RCC_BDCR 0x70 /* Backup domain control */ -#define RCC_CSR 0x74 /* clock control & status */ -#define RCC_SSCGR 0x80 /* spread spectrum clock generation */ -#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */ -#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */ -#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */ -#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */ /* * RCC AHB1ENR specific definitions */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index 38adc4e..9b315a8 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -33,6 +33,9 @@ enum periph_clock { GPIO_I_CLOCK_CFG, GPIO_J_CLOCK_CFG, GPIO_K_CLOCK_CFG, + SYSCFG_CLOCK_CFG, + TIMER2_CLOCK_CFG, + FMC_CLOCK_CFG, }; #endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c index 8091c74..4faf174 100644 --- a/arch/arm/mach-stm32/stm32f7/clock.c +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -252,6 +252,15 @@ void clock_setup(int peripheral) case GPIO_K_CLOCK_CFG: setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN); break; + case SYSCFG_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); + break; + case TIMER2_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); + break; + case FMC_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN); + break; default: break; } diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c index a7dee10..c15f8bb 100644 --- a/arch/arm/mach-stm32/stm32f7/timer.c +++ b/arch/arm/mach-stm32/stm32f7/timer.c @@ -8,8 +8,8 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <asm/arch/stm32_defs.h> #include <asm/arch/gpt.h> -#include <asm/arch/rcc.h> #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) #define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ) @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { /* Timer2 clock configuration */ - setbits_le32(RCC_BASE + RCC_APB1ENR, RCC_APB1ENR_TIM2EN); + clock_setup(TIMER2_CLOCK_CFG); /* Stop the timer */ writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index c769da0..929ccb4 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -10,7 +10,6 @@ #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/rcc.h> #include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32x7.h> @@ -171,7 +170,7 @@ int dram_init(void) if (rv) return rv; - setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN); + clock_setup(FMC_CLOCK_CFG); /* * Get frequency for NS2CLK calculation. |