diff options
234 files changed, 7572 insertions, 1372 deletions
@@ -36,7 +36,7 @@ endef generic-offsets-file := include/generated/generic-asm-offsets.h always := $(generic-offsets-file) -targets := $(generic-offsets-file) lib/asm-offsets.s +targets := lib/asm-offsets.s # We use internal kbuild rules to avoid the "is up to date" message from make lib/asm-offsets.s: lib/asm-offsets.c FORCE @@ -55,7 +55,6 @@ offsets-file := include/generated/asm-offsets.h endif always += $(offsets-file) -targets += $(offsets-file) targets += arch/$(ARCH)/lib/asm-offsets.s CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY @@ -178,7 +178,7 @@ config SYS_EXTRA_OPTIONS new boards should not use this option. config SYS_TEXT_BASE - depends on SPARC || ARC || X86 || ARCH_UNIPHIER + depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP hex "Text Base" help TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture @@ -10,9 +10,10 @@ NAME = # Comments in this file are targeted only to the developer, do not # expect to learn how to build the kernel reading this file. -# Do not use make's built-in rules and variables -# (this increases performance and avoids hard-to-debug behaviour); -MAKEFLAGS += -rR +# o Do not use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +# o Look for make include files relative to root of kernel src +MAKEFLAGS += -rR --include-dir=$(CURDIR) # Avoid funny character set dependencies unexport LC_ALL @@ -319,12 +320,9 @@ endif export KBUILD_MODULES KBUILD_BUILTIN export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD -# Look for make include files relative to root of kernel src -MAKEFLAGS += --include-dir=$(srctree) - # We need some generic definitions (do not try to remake the file). -$(srctree)/scripts/Kbuild.include: ; -include $(srctree)/scripts/Kbuild.include +scripts/Kbuild.include: ; +include scripts/Kbuild.include # Make variables (CC, etc...) @@ -437,7 +435,7 @@ endif ifeq ($(KBUILD_EXTMOD),) ifneq ($(filter config %config,$(MAKECMDGOALS)),) config-targets := 1 - ifneq ($(filter-out config %config,$(MAKECMDGOALS)),) + ifneq ($(words $(MAKECMDGOALS)),1) mixed-targets := 1 endif endif @@ -518,8 +516,8 @@ ifneq ($(wildcard include/config/auto.conf),) autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \ include/config/auto.conf) ifeq ($(autoconf_is_old),) -include $(srctree)/config.mk -include $(srctree)/arch/$(ARCH)/Makefile +include config.mk +include arch/$(ARCH)/Makefile endif endif endif @@ -595,7 +593,7 @@ endif export CONFIG_SYS_TEXT_BASE -include $(srctree)/scripts/Makefile.extrawarn +include scripts/Makefile.extrawarn # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments KBUILD_CPPFLAGS += $(KCPPFLAGS) @@ -1236,9 +1234,10 @@ define filechk_version.h endef define filechk_timestamp.h - (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ - LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ - LC_ALL=C date +'#define U_BOOT_TZ "%z"') + (SOURCE_DATE="$${SOURCE_DATE_EPOCH:+@$$SOURCE_DATE_EPOCH}"; \ + LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_DATE "%b %d %C%y"'; \ + LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_TIME "%T"'; \ + LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_TZ "%z"' ) endef $(version_h): include/config/uboot.release FORCE @@ -1248,12 +1247,6 @@ $(timestamp_h): $(srctree)/Makefile FORCE $(call filechk,timestamp.h) # --------------------------------------------------------------------------- - -PHONY += depend dep -depend dep: - @echo '*** Warning: make $@ is unnecessary now.' - -# --------------------------------------------------------------------------- quiet_cmd_cpp_lds = LDS $@ cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< @@ -1553,11 +1546,6 @@ ifneq ($(cmd_files),) include $(cmd_files) endif -# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir -# Usage: -# $(Q)$(MAKE) $(clean)=dir -clean := -f $(srctree)/scripts/Makefile.clean obj - endif # skip-makefile PHONY += FORCE @@ -5081,6 +5081,18 @@ This firmware often needs to be loaded during U-Boot booting. - CONFIG_SYS_MEM_TOP_HIDE_MIN Define minimum DDR size to be hided from top of the DDR memory +Reproducible builds +------------------- + +In order to achieve reproducible builds, timestamps used in the U-Boot build +process have to be set to a fixed value. + +This is done using the SOURCE_DATE_EPOCH environment variable. +SOURCE_DATE_EPOCH is to be set on the build host's shell, not as a configuration +option for U-Boot or an environment variable in U-Boot. + +SOURCE_DATE_EPOCH should be set to a number of seconds since the epoch, in UTC. + Building the Software: ====================== diff --git a/arch/Kconfig b/arch/Kconfig index afa1d6c..e952bb1 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1,3 +1,6 @@ +config CREATE_ARCH_SYMLINK + bool + config HAVE_GENERIC_BOARD bool @@ -18,12 +21,14 @@ config ARC config ARM bool "ARM architecture" + select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC if !ARM64 select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL config AVR32 bool "AVR32 architecture" + select CREATE_ARCH_SYMLINK select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD @@ -84,9 +89,11 @@ config SH config SPARC bool "SPARC architecture" + select CREATE_ARCH_SYMLINK config X86 bool "x86 architecture" + select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3355b3b..9127ace 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -681,23 +681,12 @@ config ARCH_ZYNQ select DM_SPI select DM_SPI_FLASH -config TARGET_XILINX_ZYNQMP +config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" select ARM64 config TEGRA bool "NVIDIA Tegra" - select SUPPORT_SPL - select SPL - select OF_CONTROL - select SPL_DISABLE_OF_CONTROL - select CPU_V7 - select DM - select DM_SPI_FLASH - select DM_SERIAL - select DM_I2C - select DM_SPI - select DM_GPIO config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" @@ -874,6 +863,8 @@ source "arch/arm/mach-zynq/Kconfig" source "arch/arm/cpu/armv7/Kconfig" +source "arch/arm/cpu/armv8/zynqmp/Kconfig" + source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" @@ -991,7 +982,6 @@ source "board/warp/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" -source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 781d83f..52a6824 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -51,15 +51,6 @@ u32 get_cpu_type(void) } /** - * get_board_rev() - setup to pass kernel board revision information - * returns: 0 for the ATAG REVISION tag value. - */ -u32 __weak get_board_rev(void) -{ - return 0; -} - -/** * get_device_type(): tell if GP/HS/EMU/TST */ u32 get_device_type(void) diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index f3725b2..464a5d1 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -26,9 +26,7 @@ ifeq ($(CONFIG_SYS_DCACHE_OFF),) obj-y += omap-cache.o endif -ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o -endif obj-y += lowlevel_init.o obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 7fc0a56..5ec46fa 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -17,27 +17,34 @@ #include <asm/arch/sys_proto.h> #include <watchdog.h> #include <scsi.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; +__weak u32 omap_sys_boot_device(void) +{ + return BOOT_DEVICE_NONE; +} + void save_omap_boot_params(void) { - u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); - u8 boot_device; - u32 dev_desc, dev_data; + u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + struct omap_boot_parameters *omap_boot_params; + u32 boot_device; + u32 boot_mode; - if ((rom_params < NON_SECURE_SRAM_START) || - (rom_params > NON_SECURE_SRAM_END)) + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) return; - /* - * rom_params can be type casted to omap_boot_parameters and - * used. But it not correct to assume that romcode structure - * encoding would be same as u-boot. So use the defined offsets. - */ - boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + omap_boot_params = (struct omap_boot_parameters *)boot_params; + + boot_device = omap_boot_params->boot_device; + boot_mode = MMCSD_MODE_UNDEFINED; + + /* Boot device */ -#if defined(BOOT_DEVICE_NAND_I2C) +#ifdef BOOT_DEVICE_NAND_I2C /* * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. * Otherwise the SPL boot IF can't handle this device correctly. @@ -47,61 +54,109 @@ void save_omap_boot_params(void) if (boot_device == BOOT_DEVICE_NAND_I2C) boot_device = BOOT_DEVICE_NAND; #endif - gd->arch.omap_boot_params.omap_bootdevice = boot_device; +#ifdef BOOT_DEVICE_QSPI_4 + /* + * We get different values for QSPI_1 and QSPI_4 being used, but + * don't actually care about this difference. Rather than + * mangle the later code, if we're coming in as QSPI_4 just + * change to the QSPI_1 value. + */ + if (boot_device == BOOT_DEVICE_QSPI_4) + boot_device = BOOT_DEVICE_SPI; +#endif +#if (defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)) || \ + (defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)) || \ + (defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT)) + /* + * When booting from peripheral booting, the boot device is not usable + * as-is (unless there is support for it), so the boot device is instead + * figured out using the SYS_BOOT pins. + */ + switch (boot_device) { +#ifdef BOOT_DEVICE_UART + case BOOT_DEVICE_UART: +#endif +#ifdef BOOT_DEVICE_USB + case BOOT_DEVICE_USB: +#endif + boot_device = omap_sys_boot_device(); + + /* MMC raw mode will fallback to FS mode. */ + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) + boot_mode = MMCSD_MODE_RAW; - gd->arch.omap_boot_params.ch_flags = - *((u8 *)(rom_params + CH_FLAGS_OFFSET)); + break; + } +#endif + gd->arch.omap_boot_device = boot_device; + + /* Boot mode */ + +#ifdef CONFIG_OMAP34XX if ((boot_device >= MMC_BOOT_DEVICES_START) && (boot_device <= MMC_BOOT_DEVICES_END)) { -#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \ - !defined(CONFIG_AM43XX) - if ((omap_hw_init_context() == - OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { - gd->arch.omap_boot_params.omap_bootmode = - *((u8 *)(rom_params + BOOT_MODE_OFFSET)); - } else -#endif - { - dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); - dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); - gd->arch.omap_boot_params.omap_bootmode = - *((u32 *)(dev_data + BOOT_MODE_OFFSET)); + switch (boot_device) { + case BOOT_DEVICE_MMC1: + boot_mode = MMCSD_MODE_FS; + break; + case BOOT_DEVICE_MMC2: + boot_mode = MMCSD_MODE_RAW; + break; } } - -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#else /* - * We get different values for QSPI_1 and QSPI_4 being used, but - * don't actually care about this difference. Rather than - * mangle the later code, if we're coming in as QSPI_4 just - * change to the QSPI_1 value. + * If the boot device was dynamically changed and doesn't match what + * the bootrom initially booted, we cannot use the boot device + * descriptor to figure out the boot mode. */ - if (gd->arch.omap_boot_params.omap_bootdevice == 11) - gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI; + if ((boot_device == omap_boot_params->boot_device) && + (boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + boot_params = omap_boot_params->boot_device_descriptor; + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET)); + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET)); + + if (boot_mode != MMCSD_MODE_FS && + boot_mode != MMCSD_MODE_RAW) +#ifdef CONFIG_SUPPORT_EMMC_BOOT + boot_mode = MMCSD_MODE_EMMCBOOT; +#else + boot_mode = MMCSD_MODE_UNDEFINED; +#endif + } +#endif + + gd->arch.omap_boot_mode = boot_mode; + +#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ + !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) + + /* CH flags */ + + gd->arch.omap_ch_flags = omap_boot_params->ch_flags; #endif } #ifdef CONFIG_SPL_BUILD u32 spl_boot_device(void) { - return (u32) (gd->arch.omap_boot_params.omap_bootdevice); + return gd->arch.omap_boot_device; } u32 spl_boot_mode(void) { - u32 val = gd->arch.omap_boot_params.omap_bootmode; - - if (val == MMCSD_MODE_RAW) - return MMCSD_MODE_RAW; - else if (val == MMCSD_MODE_FS) - return MMCSD_MODE_FS; - else -#ifdef CONFIG_SUPPORT_EMMC_BOOT - return MMCSD_MODE_EMMCBOOT; -#else - return MMCSD_MODE_UNDEFINED; -#endif + return gd->arch.omap_boot_mode; } void spl_board_init(void) @@ -116,9 +171,12 @@ void spl_board_init(void) /* Prepare console output */ preloader_console_init(); -#ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); +#endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif @@ -150,9 +208,11 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry_noargs_t image_entry = (image_entry_noargs_t) spl_image->entry_point; + u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + debug("image entry point: 0x%X\n", spl_image->entry_point); /* Pass the saved boot_params from rom code */ - image_entry((u32 *)&gd->arch.omap_boot_params); + image_entry((u32 *)boot_params); } #endif diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 6c8f3bc..80794f9 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -90,7 +90,9 @@ void __weak srcomp_enable(void) */ int arch_cpu_init(void) { +#ifdef CONFIG_SPL save_omap_boot_params(); +#endif return 0; } #endif /* CONFIG_ARCH_CPU_INIT */ diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 746df92..5283135 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,8 +16,9 @@ #include <asm/arch/spl.h> #include <linux/linkage.h> -#ifndef CONFIG_OMAP34XX +#ifdef CONFIG_SPL ENTRY(save_boot_params) + ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] b save_boot_params_ret diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index cf86046..b2fce96 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -8,6 +8,7 @@ obj-y := lowlevel_init.o obj-y += board.o +obj-y += boot.o obj-y += clock.o obj-y += sys_info.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b064c0c..17cb5b7 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -18,7 +18,6 @@ */ #include <common.h> #include <dm.h> -#include <mmc.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> @@ -27,8 +26,6 @@ #include <asm/armv7.h> #include <asm/gpio.h> #include <asm/omap_common.h> -#include <asm/arch/mmc_host_def.h> -#include <i2c.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -73,62 +70,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; #endif -#ifdef CONFIG_SPL_BUILD -/* -* We use static variables because global data is not ready yet. -* Initialized data is available in SPL right from the beginning. -* We would not typically need to save these parameters in regular -* U-Boot. This is needed only in SPL at the moment. -*/ -u32 omap3_boot_device = BOOT_DEVICE_NAND; - -/* auto boot mode detection is not possible for OMAP3 - hard code */ -u32 spl_boot_mode(void) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC2: - return MMCSD_MODE_RAW; - case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FS; - break; - default: - puts("spl: ERROR: unknown device - can't select boot mode\n"); - hang(); - } -} - -u32 spl_boot_device(void) -{ - return omap3_boot_device; -} - -int board_mmc_init(bd_t *bis) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1, -1); - break; - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0, -1, -1); - break; - } - return 0; -} - -void spl_board_init(void) -{ - preloader_console_init(); -#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) - gpmc_init(); -#endif -#ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif -} -#endif /* CONFIG_SPL_BUILD */ - - /****************************************************************************** * Routine: secure_unlock * Description: Setup security registers for access diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/cpu/armv7/omap3/boot.c new file mode 100644 index 0000000..66576b2 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/boot.c @@ -0,0 +1,58 @@ +/* + * OMAP3 boot + * + * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +static u32 boot_devices[] = { + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, +}; + +u32 omap_sys_boot_device(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl(&ctrl_base->status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 2497613..1e58772 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -16,16 +16,6 @@ #include <asm/arch/clocks_omap3.h> #include <linux/linkage.h> -#ifdef CONFIG_SPL_BUILD -ENTRY(save_boot_params) - ldr r4, =omap3_boot_device - ldr r5, [r0, #0x4] - and r5, r5, #0xff - str r5, [r4] - b save_boot_params_ret -ENDPROC(save_boot_params) -#endif - /* * Funtion for making PPA HAL API calls in secure devices * Input: diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index bbb65bb..ab60a03 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -196,10 +196,12 @@ u32 get_gpmc0_width(void) * get_board_rev() - setup to pass kernel board revision information * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) *************************************************************************/ +#ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { return 0x20; } +#endif /******************************************************** * get_base(); get upper addr of current execution diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 76a032a..564f1f6 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += boot.o obj-y += sdram_elpida.o obj-y += hwinit.o obj-y += emif.o diff --git a/arch/arm/cpu/armv7/omap4/boot.c b/arch/arm/cpu/armv7/omap4/boot.c new file mode 100644 index 0000000..4b5aa77 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/boot.c @@ -0,0 +1,60 @@ +/* + * OMAP4 boot + * + * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/omap_common.h> +#include <spl.h> + +static u32 boot_devices[] = { + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NONE, + BOOT_DEVICE_XIPWAIT, +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index 1ed146b..8698ec7 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -279,6 +279,7 @@ struct prcm_regs const omap4_prcm = { }; struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_status = 0x4A0022C4, .control_id_code = 0x4A002204, .control_std_fuse_opp_bgap = 0x4a002260, .control_status = 0x4a0022c4, diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index e709f14..f2930d5 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += boot.o obj-y += hwinit.o obj-y += emif.o obj-y += sdram.o diff --git a/arch/arm/cpu/armv7/omap5/boot.c b/arch/arm/cpu/armv7/omap5/boot.c new file mode 100644 index 0000000..583becc --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/boot.c @@ -0,0 +1,46 @@ +/* + * OMAP5 boot + * + * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/omap_common.h> +#include <spl.h> + +static u32 boot_devices[] = { +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + BOOT_DEVICE_MMC2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_SATA, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIP, + BOOT_DEVICE_SPI, + BOOT_DEVICE_SPI, +#else + BOOT_DEVICE_MMC2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_SATA, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIPWAIT, +#endif +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 4 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c index 165c052..c53671a 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c @@ -26,7 +26,6 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> -#include <linux/kconfig.h> static const struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c index ebba438..fa1620c 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c @@ -14,7 +14,6 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> -#include <linux/kconfig.h> /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ #define DRAM_CLK_MUL 2 diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c index 2eded1f..d520a13 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/cpu/armv7m/stm32f4/clock.c @@ -92,7 +92,20 @@ struct pll_psc { #error "CONFIG_STM32_HSE_HZ not defined!" #else #if (CONFIG_STM32_HSE_HZ == 8000000) -struct pll_psc pll_psc_168 = { +#if (CONFIG_SYS_CLK_FREQ == 180000000) +/* 180 MHz */ +struct pll_psc sys_pll_psc = { + .pll_m = 8, + .pll_n = 360, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2 +}; +#else +/* default 168 MHz */ +struct pll_psc sys_pll_psc = { .pll_m = 8, .pll_n = 336, .pll_p = 2, @@ -101,6 +114,7 @@ struct pll_psc pll_psc_168 = { .apb1_psc = APB_PSC_4, .apb2_psc = APB_PSC_2 }; +#endif #else #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" #endif @@ -122,19 +136,19 @@ int configure_clocks(void) while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) ; - /* Enable high performance mode, System frequency up to 168 MHz */ + /* Enable high performance mode, System frequency up to 180 MHz */ setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); setbits_le32(&STM32_RCC->cfgr, (( - pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT) - | (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT) - | (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); - - writel(pll_psc_168.pll_m - | (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT) - | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) - | (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), + sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) + | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) + | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); + + writel(sys_pll_psc.pll_m + | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT) + | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) + | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), &STM32_RCC->pllcfgr); setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC); diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index dee5e25..6466ebb 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -16,4 +16,4 @@ obj-y += tlb.o obj-y += transition.o obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ -obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/ +obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c5ec529..c22f7b6 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -25,9 +25,9 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, /* to activate the MMU we need to set up virtual memory */ static void mmu_setup(void) { - int i, j, el; bd_t *bd = gd->bd; - u64 *page_table = (u64 *)gd->arch.tlb_addr; + u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; + int el; /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { @@ -139,6 +139,37 @@ int dcache_status(void) return (get_sctlr() & CR_C) != 0; } +u64 *__weak arch_get_page_table(void) { + puts("No page table offset defined\n"); + + return NULL; +} + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + u64 *page_table = arch_get_page_table(); + u64 upto, end; + + if (page_table == NULL) + return; + + end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >> + MMU_SECTION_SHIFT; + start = start >> MMU_SECTION_SHIFT; + for (upto = start; upto < end; upto++) { + page_table[upto] &= ~PMD_ATTRINDX_MASK; + page_table[upto] |= PMD_ATTRINDX(option); + } + asm volatile("dsb sy"); + __asm_invalidate_tlb_all(); + asm volatile("dsb sy"); + asm volatile("isb"); + start = start << MMU_SECTION_SHIFT; + end = end << MMU_SECTION_SHIFT; + flush_dcache_range(start, end); + asm volatile("dsb sy"); +} #else /* CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) @@ -170,6 +201,11 @@ int dcache_status(void) return 0; } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ +} + #endif /* CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig new file mode 100644 index 0000000..c8fcfb6 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -0,0 +1,23 @@ +if ARCH_ZYNQMP + +choice + prompt "Xilinx ZynqMP board select" + +config TARGET_ZYNQMP_EP + bool "ZynqMP EP Board" + +endchoice + +config SYS_BOARD + default "zynqmp" + +config SYS_VENDOR + default "xilinx" + +config SYS_SOC + default "zynqmp" + +config SYS_CONFIG_NAME + default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP + +endif diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index efab5ea..d0ed222 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -8,3 +8,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o +obj-y += slcr.o diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 17e32a7..dcb80b5 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -216,12 +216,7 @@ int cpu_release(int nr, int argc, char * const argv[]) printf("R5 lockstep mode\n"); set_r5_tcm_mode(LOCK); set_r5_halt_mode(HALT, LOCK); - - if (boot_addr == 0) - set_r5_start(0); - else - set_r5_start(1); - + set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(LOCK); set_r5_halt_mode(RELEASE, LOCK); diff --git a/arch/arm/cpu/armv8/zynqmp/slcr.c b/arch/arm/cpu/armv8/zynqmp/slcr.c new file mode 100644 index 0000000..713e9a6 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/slcr.c @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clk.h> + +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { +}; + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8ebd693..ba63553 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -32,7 +32,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra114-dalmore.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ - tegra124-venice2.dtb + tegra124-venice2.dtb \ + tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ uniphier-ph1-pro4-ref.dtb \ @@ -45,6 +46,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts new file mode 100644 index 0000000..de35bba --- /dev/null +++ b/arch/arm/dts/tegra210-p2571.dts @@ -0,0 +1,106 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA P2571"; + compatible = "nvidia,p2571", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + i2c1 = "/i2c@0,7000c000"; + i2c2 = "/i2c@0,7000c400"; + i2c3 = "/i2c@0,7000c500"; + i2c4 = "/i2c@0,7000c700"; + i2c5 = "/i2c@0,7000d100"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + spi0 = "/spi@0,7000d400"; + spi1 = "/spi@0,7000da00"; + spi2 = "/spi@0,70410000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@0,7000d100 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@0,7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + spi@0,70410000 { + status = "okay"; + spi-max-frequency = <24000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi new file mode 100644 index 0000000..f3874a1 --- /dev/null +++ b/arch/arm/dts/tegra210.dtsi @@ -0,0 +1,283 @@ +#include <dt-bindings/clock/tegra210-car.h> +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> + +#include "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra210"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@0,50041000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x50041000 0x0 0x1000>, + <0x0 0x50042000 0x0 0x2000>, + <0x0 0x50044000 0x0 0x2000>, + <0x0 0x50046000 0x0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + + tegra_car: clock@0,60006000 { + compatible = "nvidia,tegra210-car"; + reg = <0x0 0x60006000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpio: gpio@0,6000d000 { + compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; + reg = <0x0 0x6000d000 0x0 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + i2c@0,7000c000 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c000 0x0 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>; + status = "disabled"; + }; + + i2c@0,7000c400 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c400 0x0 0x100>; + interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 54>; + status = "disabled"; + }; + + i2c@0,7000c500 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c500 0x0 0x100>; + interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 67>; + status = "disabled"; + }; + + i2c@0,7000c700 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000c700 0x0 0x100>; + interrupts = <0 120 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 103>; + status = "disabled"; + }; + + i2c@0,7000d000 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000d000 0x0 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; + + i2c@0,7000d100 { + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x7000d100 0x0 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; + + uarta: serial@0,70006000 { + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006000 0x0 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + status = "disabled"; + }; + + uartb: serial@0,70006040 { + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006040 0x0 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + status = "disabled"; + }; + + uartc: serial@0,70006200 { + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006200 0x0 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + status = "disabled"; + }; + + uartd: serial@0,70006300 { + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x70006300 0x0 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + status = "disabled"; + }; + + spi@0,7000d400 { + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000d400 0x0 0x200>; + interrupts = <0 59 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + status = "disabled"; + }; + + spi@0,7000d600 { + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000d600 0x0 0x200>; + interrupts = <0 82 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + status = "disabled"; + }; + + spi@0,7000d800 { + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000d800 0x0 0x200>; + interrupts = <0 83 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + status = "disabled"; + }; + + spi@0,7000da00 { + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; + reg = <0x0 0x7000da00 0x0 0x200>; + interrupts = <0 93 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA210_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + status = "disabled"; + }; + + spi@0,70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x0 0x70410000 0x0 0x1000>; + interrupts = <0 10 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 211>; + status = "disabled"; + }; + + padctl: padctl@0,7009f000 { + compatible = "nvidia,tegra210-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + #phy-cells = <1>; + }; + + sdhci@0,700b0000 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x0 0x700b0000 0x0 0x200>; + interrupts = <0 14 0x04>; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disabled"; + }; + + sdhci@0,700b0200 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x0 0x700b0200 0x0 0x200>; + interrupts = <0 15 0x04>; + clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disabled"; + }; + + sdhci@0,700b0400 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x0 0x700b0400 0x0 0x200>; + interrupts = <0 19 0x04>; + clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disabled"; + }; + + sdhci@0,700b0600 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x0 0x700b0600 0x0 0x200>; + interrupts = <0 31 0x04>; + clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disabled"; + }; + + usb@0,7d000000 { + compatible = "nvidia,tegra210-ehci"; + reg = <0x0 0x7d000000 0x0 0x4000>; + interrupts = <0 20 0x04>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA210_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + status = "disabled"; + }; + + usb@0,7d004000 { + compatible = "nvidia,tegra210-ehci"; + reg = <0x0 0x7d004000 0x0 0x4000>; + interrupts = < 53 >; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA210_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 9207159..0b62cb0 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -2,7 +2,7 @@ * Xilinx Zynq 7000 DTSI * Describes the hardware common to all Zynq 7000-based boards. * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx * * SPDX-License-Identifier: GPL-2.0+ */ @@ -21,11 +21,11 @@ reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; + cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 - 222223 1000000 >; }; @@ -44,14 +44,65 @@ reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; - amba { + regulator_vccpint: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VCCPINT"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; - i2c0: zynq-i2c@e0004000 { + adc: adc@f8007100 { + compatible = "xlnx,zynq-xadc-1.00.a"; + reg = <0xf8007100 0x20>; + interrupts = <0 7 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 12>; + }; + + can0: can@e0008000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <&clkc 19>, <&clkc 36>; + clock-names = "can_clk", "pclk"; + reg = <0xe0008000 0x1000>; + interrupts = <0 28 4>; + interrupt-parent = <&intc>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can1: can@e0009000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clocks = <&clkc 20>, <&clkc 37>; + clock-names = "can_clk", "pclk"; + reg = <0xe0009000 0x1000>; + interrupts = <0 51 4>; + interrupt-parent = <&intc>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + gpio0: gpio@e000a000 { + compatible = "xlnx,zynq-gpio-1.0"; + #gpio-cells = <2>; + clocks = <&clkc 42>; + gpio-controller; + interrupt-parent = <&intc>; + interrupts = <0 20 4>; + reg = <0xe000a000 0x1000>; + }; + + i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; @@ -62,7 +113,7 @@ #size-cells = <0>; }; - i2c1: zynq-i2c@e0005000 { + i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; @@ -76,41 +127,46 @@ intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #address-cells = <1>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; - L2: cache-controller { + L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; + interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; - uart0: uart@e0000000 { - compatible = "xlnx,xuartps"; + mc: memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; + + uart0: serial@e0000000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; - uart1: uart@e0001000 { - compatible = "xlnx,xuartps"; + uart1: serial@e0001000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { - compatible = "xlnx,zynq-spi"; + compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; @@ -123,7 +179,7 @@ }; spi1: spi@e0007000 { - compatible = "xlnx,zynq-spi"; + compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; @@ -136,24 +192,28 @@ }; gem0: ethernet@e000b000 { - compatible = "cdns,gem"; - reg = <0xe000b000 0x4000>; + compatible = "cdns,zynq-gem", "cdns,gem"; + reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; }; gem1: ethernet@e000c000 { - compatible = "cdns,gem"; - reg = <0xe000c000 0x4000>; + compatible = "cdns,zynq-gem", "cdns,gem"; + reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; }; - sdhci0: ps7-sdhci@e0100000 { + sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -163,7 +223,7 @@ reg = <0xe0100000 0x1000>; } ; - sdhci1: ps7-sdhci@e0101000 { + sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -176,13 +236,12 @@ slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon"; + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - ps-clk-frequency = <33333333>; fclk-enable = <0>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", @@ -197,6 +256,35 @@ "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; + + pinctrl0: pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + }; + }; + + dmac_s: dmac@f8003000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xf8003000 0x1000>; + interrupt-parent = <&intc>; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; + interrupts = <0 13 4>, + <0 14 4>, <0 15 4>, + <0 16 4>, <0 17 4>, + <0 40 4>, <0 41 4>, + <0 42 4>, <0 43 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <4>; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; + }; + + devcfg: devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; }; global_timer: timer@f8f00200 { @@ -207,27 +295,57 @@ clocks = <&clkc 4>; }; - ttc0: ttc0@f8001000 { + ttc0: timer@f8001000 { interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; - ttc1: ttc1@f8002000 { + ttc1: timer@f8002000 { interrupt-parent = <&intc>; - interrupts = < 0 37 4 0 38 4 0 39 4 >; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; - scutimer: scutimer@f8f00600 { + + scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = < 1 13 0x301 >; compatible = "arm,cortex-a9-twd-timer"; reg = < 0xf8f00600 0x20 >; clocks = <&clkc 4>; } ; + + usb0: usb@e0002000 { + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + status = "disabled"; + clocks = <&clkc 28>; + interrupt-parent = <&intc>; + interrupts = <0 21 4>; + reg = <0xe0002000 0x1000>; + phy_type = "ulpi"; + }; + + usb1: usb@e0003000 { + compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; + status = "disabled"; + clocks = <&clkc 29>; + interrupt-parent = <&intc>; + interrupts = <0 44 4>; + reg = <0xe0003000 0x1000>; + phy_type = "ulpi"; + }; + + watchdog0: watchdog@f8005000 { + clocks = <&clkc 45>; + compatible = "cdns,wdt-r1p2"; + interrupt-parent = <&intc>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + timeout-sec = <10>; + }; }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 4fa0b00..6691a8d 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -1,7 +1,8 @@ /* * Xilinx ZC702 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,380 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC702 Board"; + model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; }; memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw14 { + label = "sw14"; + gpios = <&gpio0 12 0>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + sw13 { + label = "sw13"; + gpios = <&gpio0 14 0>; + linux,code = <103>; /* up */ + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds23 { + label = "ds23"; + gpios = <&gpio0 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&amba { + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + hwmon@52 { + compatible = "ti,ucd9248"; + reg = <52>; + }; + hwmon@53 { + compatible = "ti,ucd9248"; + reg = <53>; + }; + hwmon@54 { + compatible = "ti,ucd9248"; + reg = <54>; + }; + }; + }; +}; + +&pinctrl0 { + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_9_grp"; + }; + + conf { + groups = "can0_9_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO46"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO47"; + bias-disable; + }; + }; + + pinctrl_gem0_default: gem0-default { + mux { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + }; + + conf { + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + conf-rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + bias-disable; + low-power-enable; + }; + + mux-mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + }; + + conf-mdio { + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: gpio0-default { + mux { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + }; + + conf { + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-pull-up { + pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO7", "MIO8"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_10_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_10_grp"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_0_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_0_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + mux-wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "gpio0_15_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 2a80195..cf7bce4 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -1,7 +1,8 @@ /* * Xilinx ZC706 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,301 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC706 Board"; + model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; }; memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + i2cswitch@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + si570: clock-generator@5d { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x5d>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@54 { + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + ucd90120@65 { + compatible = "ti,ucd90120"; + reg = <0x65>; + }; + }; + }; +}; + +&pinctrl0 { + pinctrl_gem0_default: gem0-default { + mux { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + }; + + conf { + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + conf-rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + conf-tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + low-power-enable; + bias-disable; + }; + + mux-mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + }; + + conf-mdio { + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: gpio0-default { + mux { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + }; + + conf { + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-pull-up { + pins = "MIO46", "MIO47"; + bias-pull-up; + }; + + conf-pull-none { + pins = "MIO7"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: i2c0-default { + mux { + groups = "i2c0_10_grp"; + function = "i2c0"; + }; + + conf { + groups = "i2c0_10_grp"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: sdhci0-default { + mux { + groups = "sdio0_2_grp"; + function = "sdio0"; + }; + + conf { + groups = "sdio0_2_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + mux-cd { + groups = "gpio0_14_grp"; + function = "sdio0_cd"; + }; + + conf-cd { + groups = "gpio0_14_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + mux-wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + }; + + conf-wp { + groups = "gpio0_15_grp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index bf107e3..da3a182 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -1,7 +1,7 @@ /* * Xilinx ZC770 XM010 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2013 - 2015 Xilinx, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,20 +9,85 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; serial0 = &uart1; - spi1 = &spi1; + spi0 = &spi1; }; - memory { + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; &spi1 { status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080"; + reg = <1>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@test { + label = "spi-flash"; + reg = <0x0 0x100000>; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; + +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts new file mode 100644 index 0000000..d38c820 --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -0,0 +1,65 @@ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" +/ { + compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + i2c0 = &i2c1; + serial0 = &uart1; + spi0 = &spi0; + }; + + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&can0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 127a661..f8cc503 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -1,7 +1,7 @@ /* * Xilinx ZC770 XM012 board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2013 - 2015 Xilinx, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +9,58 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; serial0 = &uart1; + spi0 = &spi1; }; - memory { + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart1; + stdout-path = &uart1; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&can1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + m24c02_eeprom@52 { + compatible = "at,24c02"; + reg = <0x52>; }; }; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index c61c7e7..436a8cd 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -9,15 +9,71 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; aliases { + ethernet0 = &gem1; + i2c0 = &i2c1; serial0 = &uart0; + spi0 = &spi0; }; - memory { + chosen { + bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; + linux,stdout-path = &uart0; + stdout-path = &uart0; + }; + + memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: at25@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; }; }; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + si570: clock-generator@55 { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x55>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 70cc8a6..5762576 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -1,7 +1,8 @@ /* * Xilinx ZED board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,54 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZED Board"; + model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; serial0 = &uart1; }; memory { device_type = "memory"; - reg = <0 0x20000000>; + reg = <0x0 0x20000000>; }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 20e0386..10f7815 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -1,7 +1,8 @@ /* * Digilent ZYBO board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2012 National Instruments Corp. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,15 +10,44 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZYBO Board"; - compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000"; + model = "Zynq ZYBO Development Board"; + compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; aliases { + ethernet0 = &gem0; serial0 = &uart1; }; memory { device_type = "memory"; - reg = <0 0x20000000>; + reg = <0x0 0x20000000>; }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; }; diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index e5c0b0d..47962da 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -33,4 +33,15 @@ #define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14 #define QSPI_BASE 0x47900000 #endif + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int reserved; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; +}; +#endif + #endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index e756418..4ed8597 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -7,51 +7,65 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ -#if defined(CONFIG_TI816X) -#define BOOT_DEVICE_XIP 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_MMC1 6 -#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_MMC2_2 0xFF + +#if defined(CONFIG_TI814X) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_NAND_I2C 0x06 +#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ +#define BOOT_DEVICE_MMC1 0x09 +#define BOOT_DEVICE_SPI 0x15 +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x44 +#define BOOT_DEVICE_CPGMAC 0x46 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#elif defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAD 0x04 +#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ +#define BOOT_DEVICE_MMC1 0x06 #define BOOT_DEVICE_UART 0x43 -#elif defined(CONFIG_AM43XX) -#define BOOT_DEVICE_NOR 1 -#define BOOT_DEVICE_NAND 5 -#define BOOT_DEVICE_MMC1 7 -#define BOOT_DEVICE_MMC2 8 -#define BOOT_DEVICE_SPI 10 -#define BOOT_DEVICE_USB 13 -#define BOOT_DEVICE_UART 65 -#define BOOT_DEVICE_CPGMAC 71 -#else -#define BOOT_DEVICE_XIP 2 -#define BOOT_DEVICE_NAND 5 -#define BOOT_DEVICE_NAND_I2C 6 -#if defined(CONFIG_AM33XX) -#define BOOT_DEVICE_MMC1 8 -#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ -#elif defined(CONFIG_TI814X) -#define BOOT_DEVICE_MMC1 9 -#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */ -#endif -#define BOOT_DEVICE_SPI 11 -#define BOOT_DEVICE_UART 65 -#define BOOT_DEVICE_USBETH 68 -#define BOOT_DEVICE_CPGMAC 70 -#endif -#define BOOT_DEVICE_MMC2_2 0xFF +#define BOOT_DEVICE_USB 0x45 -#if defined(CONFIG_AM33XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#elif defined(CONFIG_AM33XX) +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_NAND_I2C 0x06 +#define BOOT_DEVICE_MMC1 0x08 +#define BOOT_DEVICE_MMC2 0x09 +#define BOOT_DEVICE_SPI 0x15 +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USBETH 0x44 +#define BOOT_DEVICE_CPGMAC 0x46 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 #elif defined(CONFIG_AM43XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define BOOT_DEVICE_NOR 0x01 +#define BOOT_DEVICE_NAND 0x05 +#define BOOT_DEVICE_MMC1 0x07 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_SPI 0x0A +#define BOOT_DEVICE_UART 0x41 +#define BOOT_DEVICE_USB 0x45 +#define BOOT_DEVICE_CPGMAC 0x47 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #ifdef CONFIG_SPL_USB_SUPPORT -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB #else -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 #endif -#elif defined(CONFIG_TI81XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 #endif + #endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 7eacf27..91b614a 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -11,7 +11,6 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ #include <linux/mtd/omap_gpmc.h> -#include <asm/ti-common/sys_proto.h> #include <asm/arch/cpu.h> u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h index 194b93b..537d13b 100644 --- a/arch/arm/include/asm/arch-omap3/omap.h +++ b/arch/arm/include/asm/arch-omap3/omap.h @@ -142,6 +142,7 @@ struct gpio { #define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ #define NON_SECURE_SRAM_END 0x40210000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4020E000 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC @@ -245,4 +246,16 @@ struct gpio { /* ABB tranxdone mask */ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26) +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned char boot_device; + unsigned char reserved; + unsigned char reset_reason; + unsigned char ch_flags; + unsigned int boot_device_descriptor; +}; +#endif + #endif diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 8350532..a31b4ea 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -7,14 +7,16 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_ONENAND 3 -#define BOOT_DEVICE_MMC2 5 /*emmc*/ -#define BOOT_DEVICE_MMC1 6 -#define BOOT_DEVICE_XIPWAIT 7 -#define BOOT_DEVICE_MMC2_2 0xFF +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_NAND 0x02 +#define BOOT_DEVICE_ONENAND 0x03 +#define BOOT_DEVICE_MMC2 0x05 +#define BOOT_DEVICE_MMC1 0x06 +#define BOOT_DEVICE_XIPWAIT 0x07 +#define BOOT_DEVICE_MMC2_2 0x08 +#define BOOT_DEVICE_UART 0x10 +#define BOOT_DEVICE_USB 0x11 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 3e45ce1..94f29fd 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -52,7 +52,6 @@ void set_muxconf_regs(void); u32 get_cpu_family(void); u32 get_cpu_rev(void); u32 get_sku_id(void); -u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); u32 get_gpmc0_width(void); @@ -75,4 +74,6 @@ void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_set_aux_cr_secure(u32 acr); u32 warm_reset(void); + +void save_omap_boot_params(void); #endif diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index d43dc26..12b1a09 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -124,4 +124,15 @@ struct s32ktimer { /* ABB tranxdone mask */ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif + #endif diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index fb842a2..bace92d 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -7,15 +7,17 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 0xFF +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC1 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_MMC2_2 0x07 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 #endif diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 68c6d6d..524fae4 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -235,4 +235,16 @@ struct ctrl_ioregs { }; #endif /* __ASSEMBLY__ */ + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif + #endif diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index f707998..468ff5a 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -7,17 +7,20 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_SATA 9 -#define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC1 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_MMC2_2 0x07 +#define BOOT_DEVICE_SATA 0x09 +#define BOOT_DEVICE_SPI 0x0A +#define BOOT_DEVICE_QSPI_1 0x0A +#define BOOT_DEVICE_QSPI_4 0x0B #define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index a9f88db..3ed3801 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -14,6 +14,7 @@ /* * Peripheral memory map */ +#define STM32_SYSMEM_BASE 0x1FFF0000 #define STM32_PERIPH_BASE 0x40000000 #define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) @@ -25,6 +26,12 @@ /* * Register maps */ +struct stm32_u_id_regs { + u32 u_id_low; + u32 u_id_mid; + u32 u_id_high; +}; + struct stm32_rcc_regs { u32 cr; /* RCC clock control */ u32 pllcfgr; /* RCC PLL configuration */ @@ -78,6 +85,9 @@ struct stm32_flash_regs { /* * Registers access macros */ +#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) +#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) + #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) #define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index ca40e4e..76773b7 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2011 + * (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -24,8 +24,6 @@ #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ #define PG_UP_TAG_0 0x0 -#define CORESIGHT_UNLOCK 0xC5ACCE55; - /* AP base physical address of internal SRAM */ #define NV_PA_BASE_SRAM 0x40000000 @@ -66,7 +64,7 @@ int tegra_get_sku_info(void); /* Do any chip-specific cache config */ void config_cache(void); -#if defined(CONFIG_TEGRA124) +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) /* Do chip-specific vpr config */ void config_vpr(void); #else diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index de50e08..f690260 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -48,6 +48,7 @@ enum { TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ + TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */ }; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ @@ -94,7 +95,15 @@ struct clk_rst_ctlr { uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ + uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ + uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ + uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ + + uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ + uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ + uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ + + uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */ uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ @@ -136,7 +145,7 @@ struct clk_rst_ctlr { struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - /* Additional (T114) registers */ + /* Additional (T114+) registers */ uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ @@ -207,9 +216,18 @@ struct clk_rst_ctlr { u32 _rsv32_1[7]; /* 0x574-58c */ struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - u32 _rsrv32_2[25]; - /* Tegra124 */ - uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ + + /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */ + uint _rsrv32_2[25]; /* _0x59C - 0x5FC */ + uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */ + + /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */ + uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */ + /* + * NOTE: PLLA1 regs are in the middle of this Y region. Break this in + * two later if PLLA1 is needed, but for now this is cleaner. + */ + uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */ }; /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ @@ -233,6 +251,8 @@ struct clk_rst_ctlr { #define PLL_DIVP_SHIFT 20 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) +/* Special case for T210 PLLU DIVP */ +#define PLLU_DIVP_SHIFT 16 #define PLL_DIVN_SHIFT 8 #define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) @@ -261,6 +281,12 @@ struct clk_rst_ctlr { #define PLL_LFCON_SHIFT 4 #define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) +/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */ +#define PLLU_KVCO_SHIFT 24 +#define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT) +#define PLLU_KCP_SHIFT 25 +#define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT) + #define PLLU_VCO_FREQ_SHIFT 20 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h index 7a86acb..695f3e6 100644 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -21,5 +21,6 @@ #define CHIPID_TEGRA30 0x30 #define CHIPID_TEGRA114 0x35 #define CHIPID_TEGRA124 0x40 +#define CHIPID_TEGRA210 0x21 #endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index 1dd3154..66c0879 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011,2014 + * (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -294,6 +294,7 @@ struct pmc_ctlr { #define CRAIL 0 #define CE0 14 #define C0NC 15 +#define SOR 17 #define PMC_XOFS_SHIFT 1 #define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) @@ -303,7 +304,7 @@ struct pmc_ctlr { #define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) #define TIMER_MULT_CPU_SHIFT 2 #define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) -#elif defined(CONFIG_TEGRA124) +#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) #define TIMER_MULT_SHIFT 0 #define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT) #define TIMER_MULT_CPU_SHIFT 3 @@ -314,7 +315,7 @@ struct pmc_ctlr { #define MULT_2 1 #define MULT_4 2 #define MULT_8 3 -#if defined(CONFIG_TEGRA124) +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) #define MULT_16 4 #endif diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index d63af0e..b6c7cab 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -74,6 +74,7 @@ enum { SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ SKU_ID_T114_1 = 0x01, SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ + SKU_ID_T210_ENG = 0x00, /* unfused value TBD */ }; /* @@ -88,6 +89,7 @@ enum { TEGRA_SOC_T30, TEGRA_SOC_T114, TEGRA_SOC_T124, + TEGRA_SOC_T210, TEGRA_SOC_CNT, TEGRA_SOC_UNKNOWN = -1, diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index c817088..f400c01 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -266,6 +266,9 @@ struct usb_ctlr { /* USBx_UTMIP_BIAS_CFG1_0 */ #define UTMIP_FORCE_PDTRK_POWERDOWN 1 +#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8 +#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \ + (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT) #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 #define UTMIP_BIAS_PDTRK_COUNT_MASK \ (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h new file mode 100644 index 0000000..3a37af4 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/ahb.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_AHB_H_ +#define _TEGRA210_AHB_H_ + +struct ahb_ctlr { + u32 reserved0; /* 00h */ + u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ + u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ + u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ + u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ + u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ + u32 reserved6[2]; /* 18h, 1ch */ + u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ + u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ + u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ + u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ + u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ + u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ + u32 reserved13[2]; /* 38h, 3ch */ + u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ + u32 reserved15; /* 44h */ + u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ + u32 reserved17; /* 4ch */ + u32 gizmo_se; /* _GIZMO_SE_0, 50h */ + u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ + u32 reserved20[3]; /* 58h, 5ch, 60h */ + u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ + u32 reserved22[3]; /* 68h, 6ch, 70h */ + u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ + u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ + u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ + u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ + u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ + u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ + u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ + u32 reserved30[13]; /* 90h ~ c0h */ + u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ + u32 reserved32[5]; /* c8h ~ d8h */ + u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ + u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ + u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ + u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ + u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ + u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ + u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ + u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ + /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ + u32 arbitration_ahb_mem_wrque_mst_id; + u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ + u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ + u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ + u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ + u32 reserved46[4]; /* 110h ~ 11ch */ + u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ + u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ + u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ + u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ + u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ + u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ + /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ + u32 axicif_fastsync0_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ + u32 axicif_fastsync1_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ + u32 axicif_fastsync2_cpuclk_to_mcclk; + /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ + u32 axicif_fastsync0_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ + u32 axicif_fastsync1_mcclk_to_cpuclk; + /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ + u32 axicif_fastsync2_mcclk_to_cpuclk; +}; + +#define PPSB_STOPCLK_ENABLE (1 << 2) + +#define GIZ_ENABLE_SPLIT (1 << 0) +#define GIZ_ENB_FAST_REARB (1 << 2) +#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) + +#define GIZ_USB_IMMEDIATE (1 << 18) + +/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ +#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) + +#endif /* _TEGRA210_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h new file mode 100644 index 0000000..b62e070 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra210 clock PLL tables */ + +#ifndef _TEGRA210_CLOCK_TABLES_H_ +#define _TEGRA210_CLOCK_TABLES_H_ + +/* The PLLs supported by the hardware */ +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, + + /* now the simple ones */ + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SoC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, + + CLOCK_ID_COUNT, /* number of PLLs */ + + /* + * These are clock IDs that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL_0, + CLOCK_ID_CGENERAL_1, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_CGENERAL4_0, + CLOCK_ID_CGENERAL4_1, + CLOCK_ID_CGENERAL4_2, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + + CLOCK_ID_NONE = -1, +}; + +/* The clocks supported by the hardware */ +enum periph_id { + PERIPH_ID_FIRST, + + /* Low word: 31:0 (DEVICES_L) */ + PERIPH_ID_CPU = PERIPH_ID_FIRST, + PERIPH_ID_COP, + PERIPH_ID_TRIGSYS, + PERIPH_ID_ISPB, + PERIPH_ID_RESERVED4, + PERIPH_ID_TMR, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + + /* 8 */ + PERIPH_ID_GPIO, + PERIPH_ID_SDMMC2, + PERIPH_ID_SPDIF, + PERIPH_ID_I2S2, + PERIPH_ID_I2C1, + PERIPH_ID_RESERVED13, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC4, + + /* 16 */ + PERIPH_ID_TCW, + PERIPH_ID_PWM, + PERIPH_ID_I2S3, + PERIPH_ID_RESERVED19, + PERIPH_ID_VI, + PERIPH_ID_RESERVED21, + PERIPH_ID_USBD, + PERIPH_ID_ISP, + + /* 24 */ + PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, + PERIPH_ID_DISP2, + PERIPH_ID_DISP1, + PERIPH_ID_HOST1X, + PERIPH_ID_VCP, + PERIPH_ID_I2S1, + PERIPH_ID_CACHE2, + + /* Middle word: 63:32 (DEVICES_H) */ + PERIPH_ID_MEM, + PERIPH_ID_AHBDMA, + PERIPH_ID_APBDMA, + PERIPH_ID_RESERVED35, + PERIPH_ID_RESERVED36, + PERIPH_ID_STAT_MON, + PERIPH_ID_RESERVED38, + PERIPH_ID_FUSE, + + /* 40 */ + PERIPH_ID_KFUSE, + PERIPH_ID_SBC1, + PERIPH_ID_SNOR, + PERIPH_ID_RESERVED43, + PERIPH_ID_SBC2, + PERIPH_ID_XIO, + PERIPH_ID_SBC3, + PERIPH_ID_I2C5, + + /* 48 */ + PERIPH_ID_DSI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, + PERIPH_ID_HDMI, + PERIPH_ID_CSI, + PERIPH_ID_RESERVED53, + PERIPH_ID_I2C2, + PERIPH_ID_UART3, + + /* 56 */ + PERIPH_ID_MIPI_CAL, + PERIPH_ID_EMC, + PERIPH_ID_USB2, + PERIPH_ID_USB3, + PERIPH_ID_RESERVED60, + PERIPH_ID_VDE, + PERIPH_ID_BSEA, + PERIPH_ID_BSEV, + + /* Upper word 95:64 (DEVICES_U) */ + PERIPH_ID_RESERVED64, + PERIPH_ID_UART4, + PERIPH_ID_UART5, + PERIPH_ID_I2C3, + PERIPH_ID_SBC4, + PERIPH_ID_SDMMC3, + PERIPH_ID_PCIE, + PERIPH_ID_OWR, + + /* 72 */ + PERIPH_ID_AFI, + PERIPH_ID_CORESIGHT, + PERIPH_ID_PCIEXCLK, + PERIPH_ID_AVPUCQ, + PERIPH_ID_LA, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, + PERIPH_ID_DTV, + + /* 80 */ + PERIPH_ID_RESERVED80, + PERIPH_ID_I2CSLOW, + PERIPH_ID_DSIB, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, + + /* 88 */ + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, + PERIPH_ID_RESERVED93, + PERIPH_ID_RESERVED94, + PERIPH_ID_XUSB_DEV, + + PERIPH_ID_VW_FIRST, + /* V word: 31:0 */ + PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, + PERIPH_ID_CPULP, + PERIPH_ID_V_RESERVED2, + PERIPH_ID_MSELECT, + PERIPH_ID_V_RESERVED4, + PERIPH_ID_I2S4, + PERIPH_ID_I2S5, + PERIPH_ID_I2C4, + + /* 104 */ + PERIPH_ID_SBC5, + PERIPH_ID_SBC6, + PERIPH_ID_AHUB, + PERIPH_ID_APB2APE, + PERIPH_ID_V_RESERVED12, + PERIPH_ID_V_RESERVED13, + PERIPH_ID_V_RESERVED14, + PERIPH_ID_HDA2CODEC2X, + + /* 112 */ + PERIPH_ID_ATOMICS, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, + PERIPH_ID_ACTMON, + + /* 120 */ + PERIPH_ID_EXTPERIPH1, + PERIPH_ID_EXTPERIPH2, + PERIPH_ID_EXTPERIPH3, + PERIPH_ID_OOB, + PERIPH_ID_SATA, + PERIPH_ID_HDA, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, + + /* W word: 31:0 */ + PERIPH_ID_HDA2HDMICODEC, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, + + /* 136 */ + PERIPH_ID_CEC, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, + + /* 144 */ + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_DDS, + PERIPH_ID_W_RESERVED23, + + /* 152 */ + PERIPH_ID_W_RESERVED24, + PERIPH_ID_W_RESERVED25, + PERIPH_ID_W_RESERVED26, + PERIPH_ID_DVFS, + PERIPH_ID_XUSB_SS, + PERIPH_ID_W_RESERVED29, + PERIPH_ID_W_RESERVED30, + PERIPH_ID_W_RESERVED31, + + PERIPH_ID_X_FIRST, + /* X word: 31:0 */ + PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, + PERIPH_ID_X_RESERVED1, + PERIPH_ID_X_RESERVED2, + PERIPH_ID_X_RESERVED3, + PERIPH_ID_CAM_MCLK, + PERIPH_ID_CAM_MCLK2, + PERIPH_ID_I2C6, + PERIPH_ID_X_RESERVED7, + + /* 168 */ + PERIPH_ID_X_RESERVED8, + PERIPH_ID_X_RESERVED9, + PERIPH_ID_X_RESERVED10, + PERIPH_ID_VIM2_CLK, + PERIPH_ID_X_RESERVED12, + PERIPH_ID_X_RESERVED13, + PERIPH_ID_EMC_DLL, + PERIPH_ID_X_RESERVED15, + + /* 176 */ + PERIPH_ID_HDMI_AUDIO, + PERIPH_ID_CLK72MHZ, + PERIPH_ID_VIC, + PERIPH_ID_X_RESERVED19, + PERIPH_ID_X_RESERVED20, + PERIPH_ID_DPAUX, + PERIPH_ID_SOR0, + PERIPH_ID_X_RESERVED23, + + /* 184 */ + PERIPH_ID_GPU, + PERIPH_ID_X_RESERVED25, + PERIPH_ID_X_RESERVED26, + PERIPH_ID_X_RESERVED27, + PERIPH_ID_X_RESERVED28, + PERIPH_ID_X_RESERVED29, + PERIPH_ID_X_RESERVED30, + PERIPH_ID_X_RESERVED31, + + PERIPH_ID_Y_FIRST, + /* Y word: 31:0 (192:223) */ + PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST, + PERIPH_ID_Y_RESERVED1, + PERIPH_ID_Y_RESERVED2, + PERIPH_ID_Y_RESERVED3, + PERIPH_ID_Y_RESERVED4, + PERIPH_ID_Y_RESERVED5, + PERIPH_ID_APE, + PERIPH_ID_Y_RESERVED7, + + /* 200 */ + PERIPH_ID_MC_CDPA, + PERIPH_ID_Y_RESERVED9, + PERIPH_ID_Y_RESERVED10, + PERIPH_ID_Y_RESERVED11, + PERIPH_ID_Y_RESERVED12, + PERIPH_ID_PEX_USB_UPHY, + PERIPH_ID_Y_RESERVED14, + PERIPH_ID_Y_RESERVED15, + + /* 208 */ + PERIPH_ID_VI_I2C, + PERIPH_ID_Y_RESERVED17, + PERIPH_ID_Y_RESERVED18, + PERIPH_ID_QSPI, + PERIPH_ID_Y_RESERVED20, + PERIPH_ID_Y_RESERVED21, + PERIPH_ID_Y_RESERVED22, + PERIPH_ID_Y_RESERVED23, + + /* 216 */ + PERIPH_ID_Y_RESERVED24, + PERIPH_ID_Y_RESERVED25, + PERIPH_ID_Y_RESERVED26, + PERIPH_ID_Y_RESERVED27, + PERIPH_ID_Y_RESERVED28, + PERIPH_ID_Y_RESERVED29, + PERIPH_ID_Y_RESERVED30, + PERIPH_ID_Y_RESERVED31, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +enum pll_out_id { + PLL_OUT1, + PLL_OUT2, + PLL_OUT3, + PLL_OUT4 +}; + +/* + * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want + * callers to use the PERIPH_ID for all access to peripheral clocks to avoid + * confusion bewteen PERIPH_ID_... and PERIPHC_... + * + * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be + * confusing. + */ +enum periphc_internal_id { + /* 0x00 */ + PERIPHC_I2S2, + PERIPHC_I2S3, + PERIPHC_SPDIF_OUT, + PERIPHC_SPDIF_IN, + PERIPHC_PWM, + PERIPHC_05h, + PERIPHC_SBC2, + PERIPHC_SBC3, + + /* 0x08 */ + PERIPHC_08h, + PERIPHC_I2C1, + PERIPHC_I2C5, + PERIPHC_0bh, + PERIPHC_0ch, + PERIPHC_SBC1, + PERIPHC_DISP1, + PERIPHC_DISP2, + + /* 0x10 */ + PERIPHC_10h, + PERIPHC_11h, + PERIPHC_VI, + PERIPHC_13h, + PERIPHC_SDMMC1, + PERIPHC_SDMMC2, + PERIPHC_G3D, + PERIPHC_G2D, + + /* 0x18 */ + PERIPHC_18h, + PERIPHC_SDMMC4, + PERIPHC_VFIR, + PERIPHC_1Bh, + PERIPHC_1Ch, + PERIPHC_HSI, + PERIPHC_UART1, + PERIPHC_UART2, + + /* 0x20 */ + PERIPHC_HOST1X, + PERIPHC_21h, + PERIPHC_22h, + PERIPHC_HDMI, + PERIPHC_24h, + PERIPHC_25h, + PERIPHC_I2C2, + PERIPHC_EMC, + + /* 0x28 */ + PERIPHC_UART3, + PERIPHC_29h, + PERIPHC_VI_SENSOR, + PERIPHC_2bh, + PERIPHC_2ch, + PERIPHC_SBC4, + PERIPHC_I2C3, + PERIPHC_SDMMC3, + + /* 0x30 */ + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_VDE, + PERIPHC_OWR, + PERIPHC_NOR, + PERIPHC_CSITE, + PERIPHC_I2S1, + PERIPHC_DTV, + + /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ + PERIPHC_40h = PERIPHC_VW_FIRST, + PERIPHC_MSELECT, + PERIPHC_TSENSOR, + PERIPHC_I2S4, + PERIPHC_I2S5, + PERIPHC_I2C4, + PERIPHC_SBC5, + PERIPHC_SBC6, + + /* 0x48 */ + PERIPHC_AUDIO, + PERIPHC_49h, + PERIPHC_4ah, + PERIPHC_4bh, + PERIPHC_4ch, + PERIPHC_HDA2CODEC2X, + PERIPHC_ACTMON, + PERIPHC_EXTPERIPH1, + + /* 0x50 */ + PERIPHC_EXTPERIPH2, + PERIPHC_EXTPERIPH3, + PERIPHC_52h, + PERIPHC_I2CSLOW, + PERIPHC_SYS, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, + PERIPHC_SATAOOB, + PERIPHC_SATA, + PERIPHC_HDA, /* 0x428 */ + PERIPHC_5fh, + + PERIPHC_X_FIRST, + /* 0x60 */ + PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ + PERIPHC_XUSB_FALCON, + PERIPHC_XUSB_FS, + PERIPHC_XUSB_CORE_DEV, + PERIPHC_XUSB_SS, + PERIPHC_CILAB, + PERIPHC_CILCD, + PERIPHC_CILE, + + /* 0x68 */ + PERIPHC_DSIA_LP, + PERIPHC_DSIB_LP, + PERIPHC_ENTROPY, + PERIPHC_DVFS_REF, + PERIPHC_DVFS_SOC, + PERIPHC_TRACECLKIN, + PERIPHC_6Eh, + PERIPHC_6Fh, + + /* 0x70 */ + PERIPHC_EMC_LATENCY, + PERIPHC_SOC_THERM, + PERIPHC_72h, + PERIPHC_73h, + PERIPHC_74h, + PERIPHC_75h, + PERIPHC_VI_SENSOR2, + PERIPHC_I2C6, + + /* 0x78 */ + PERIPHC_78h, + PERIPHC_EMC_DLL, + PERIPHC_7ah, + PERIPHC_CLK72MHZ, + PERIPHC_7ch, + PERIPHC_7dh, + PERIPHC_VIC, + PERIPHC_7fh, + + PERIPHC_Y_FIRST, + /* 0x80 */ + PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */ + PERIPHC_NVDEC, /* 0x698 */ + PERIPHC_NVJPG, /* 0x69c */ + PERIPHC_NVENC, /* 0x6a0 */ + PERIPHC_84h, + PERIPHC_85h, + PERIPHC_86h, + PERIPHC_87h, + + /* 0x88 */ + PERIPHC_88h, + PERIPHC_89h, + PERIPHC_DMIC3, /* 0x6bc: */ + PERIPHC_APE, /* 0x6c0: */ + PERIPHC_QSPI, /* 0x6c4: */ + PERIPHC_VI_I2C, /* 0x6c8: */ + PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */ + PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */ + + /* 0x90 */ + PERIPHC_MAUD, /* 0x6d4: */ + PERIPHC_TSECB, /* 0x6d8: */ + + PERIPHC_COUNT, + PERIPHC_NONE = -1, +}; + +/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ +#define PERIPH_REG(id) \ + (id < PERIPH_ID_VW_FIRST) ? \ + ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) + +/* Mask value for a clock (within PERIPH_REG(id)) */ +#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) + +/* return 1 if a PLL ID is in range */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) + +/* return 1 if a peripheral ID is in range */ +#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ + (id) < PERIPH_ID_COUNT) + +#endif /* _TEGRA210_CLOCK_TABLES_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h new file mode 100644 index 0000000..3501be2 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/clock.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra210 clock control definitions */ + +#ifndef _TEGRA210_CLOCK_H_ +#define _TEGRA210_CLOCK_H_ + +#include <asm/arch-tegra/clock.h> + +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) + +/* PLL bits that differ from generic clk_rst.h */ +#define PLLC_RESET 30 +#define PLLC_IDDQ 27 +#define PLLD_ENABLE_CLK 21 +#define PLLD_EN_LCKDET 28 + +int tegra_plle_enable(void); + +#endif /* _TEGRA210_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h new file mode 100644 index 0000000..e2301ae --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/flow.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_FLOW_H_ +#define _TEGRA210_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +/* CPUn_CSR_0 */ +#define CSR_ENABLE (1 << 0) +#define CSR_IMMEDIATE_WAKE (1 << 3) +#define CSR_WAIT_WFI_SHIFT 8 + +#endif /* _TEGRA210_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h new file mode 100644 index 0000000..f0851de --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/funcmux.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra210 high-level function multiplexing */ + +#ifndef _TEGRA210_FUNCMUX_H_ +#define _TEGRA210_FUNCMUX_H_ + +#include <asm/arch-tegra/funcmux.h> + +/* Configs supported by the func mux */ +enum { + FUNCMUX_DEFAULT = 0, /* default config */ + + /* UART configs */ + FUNCMUX_UART1_UART1 = 0, + FUNCMUX_UART4_UART4 = 0, +}; +#endif /* _TEGRA210_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h new file mode 100644 index 0000000..fb69baf --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_GP_PADCTRL_H_ +#define _TEGRA210_GP_PADCTRL_H_ + +#include <asm/arch-tegra/gp_padctrl.h> + +/* APB_MISC_GP and padctrl registers */ +struct apb_misc_gp_ctlr { + u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x08 - 0x5C: */ + u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x8C: */ + u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ + u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0xC8-0xE8: */ + u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ +}; + +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + +#endif /* _TEGRA210_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h new file mode 100644 index 0000000..71af423 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/gpio.h @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_GPIO_H_ +#define _TEGRA210_GPIO_H_ + +/* + * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* number of banks */ + +#include <asm/arch-tegra/gpio.h> + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; + uint gpio_masked_config[TEGRA_GPIO_PORTS]; + uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_out[TEGRA_GPIO_PORTS]; + uint gpio_masked_in[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; + uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +enum gpio_pin { + GPIO_PA0 = 0, /* pin 0 */ + GPIO_PA1, + GPIO_PA2, + GPIO_PA3, + GPIO_PA4, + GPIO_PA5, + GPIO_PA6, + GPIO_PA7, + GPIO_PB0, /* pin 8 */ + GPIO_PB1, + GPIO_PB2, + GPIO_PB3, + GPIO_PB4, + GPIO_PB5, + GPIO_PB6, + GPIO_PB7, + GPIO_PC0, /* pin 16 */ + GPIO_PC1, + GPIO_PC2, + GPIO_PC3, + GPIO_PC4, + GPIO_PC5, + GPIO_PC6, + GPIO_PC7, + GPIO_PD0, /* pin 24 */ + GPIO_PD1, + GPIO_PD2, + GPIO_PD3, + GPIO_PD4, + GPIO_PD5, + GPIO_PD6, + GPIO_PD7, + GPIO_PE0, /* pin 32 */ + GPIO_PE1, + GPIO_PE2, + GPIO_PE3, + GPIO_PE4, + GPIO_PE5, + GPIO_PE6, + GPIO_PE7, + GPIO_PF0, /* pin 40 */ + GPIO_PF1, + GPIO_PF2, + GPIO_PF3, + GPIO_PF4, + GPIO_PF5, + GPIO_PF6, + GPIO_PF7, + GPIO_PG0, /* pin 48 */ + GPIO_PG1, + GPIO_PG2, + GPIO_PG3, + GPIO_PG4, + GPIO_PG5, + GPIO_PG6, + GPIO_PG7, + GPIO_PH0, /* pin 56 */ + GPIO_PH1, + GPIO_PH2, + GPIO_PH3, + GPIO_PH4, + GPIO_PH5, + GPIO_PH6, + GPIO_PH7, + GPIO_PI0, /* pin 64 */ + GPIO_PI1, + GPIO_PI2, + GPIO_PI3, + GPIO_PI4, + GPIO_PI5, + GPIO_PI6, + GPIO_PI7, + GPIO_PJ0, /* pin 72 */ + GPIO_PJ1, + GPIO_PJ2, + GPIO_PJ3, + GPIO_PJ4, + GPIO_PJ5, + GPIO_PJ6, + GPIO_PJ7, + GPIO_PK0, /* pin 80 */ + GPIO_PK1, + GPIO_PK2, + GPIO_PK3, + GPIO_PK4, + GPIO_PK5, + GPIO_PK6, + GPIO_PK7, + GPIO_PL0, /* pin 88 */ + GPIO_PL1, + GPIO_PL2, + GPIO_PL3, + GPIO_PL4, + GPIO_PL5, + GPIO_PL6, + GPIO_PL7, + GPIO_PM0, /* pin 96 */ + GPIO_PM1, + GPIO_PM2, + GPIO_PM3, + GPIO_PM4, + GPIO_PM5, + GPIO_PM6, + GPIO_PM7, + GPIO_PN0, /* pin 104 */ + GPIO_PN1, + GPIO_PN2, + GPIO_PN3, + GPIO_PN4, + GPIO_PN5, + GPIO_PN6, + GPIO_PN7, + GPIO_PO0, /* pin 112 */ + GPIO_PO1, + GPIO_PO2, + GPIO_PO3, + GPIO_PO4, + GPIO_PO5, + GPIO_PO6, + GPIO_PO7, + GPIO_PP0, /* pin 120 */ + GPIO_PP1, + GPIO_PP2, + GPIO_PP3, + GPIO_PP4, + GPIO_PP5, + GPIO_PP6, + GPIO_PP7, + GPIO_PQ0, /* pin 128 */ + GPIO_PQ1, + GPIO_PQ2, + GPIO_PQ3, + GPIO_PQ4, + GPIO_PQ5, + GPIO_PQ6, + GPIO_PQ7, + GPIO_PR0, /* pin 136 */ + GPIO_PR1, + GPIO_PR2, + GPIO_PR3, + GPIO_PR4, + GPIO_PR5, + GPIO_PR6, + GPIO_PR7, + GPIO_PS0, /* pin 144 */ + GPIO_PS1, + GPIO_PS2, + GPIO_PS3, + GPIO_PS4, + GPIO_PS5, + GPIO_PS6, + GPIO_PS7, + GPIO_PT0, /* pin 152 */ + GPIO_PT1, + GPIO_PT2, + GPIO_PT3, + GPIO_PT4, + GPIO_PT5, + GPIO_PT6, + GPIO_PT7, + GPIO_PU0, /* pin 160 */ + GPIO_PU1, + GPIO_PU2, + GPIO_PU3, + GPIO_PU4, + GPIO_PU5, + GPIO_PU6, + GPIO_PU7, + GPIO_PV0, /* pin 168 */ + GPIO_PV1, + GPIO_PV2, + GPIO_PV3, + GPIO_PV4, + GPIO_PV5, + GPIO_PV6, + GPIO_PV7, + GPIO_PW0, /* pin 176 */ + GPIO_PW1, + GPIO_PW2, + GPIO_PW3, + GPIO_PW4, + GPIO_PW5, + GPIO_PW6, + GPIO_PW7, + GPIO_PX0, /* pin 184 */ + GPIO_PX1, + GPIO_PX2, + GPIO_PX3, + GPIO_PX4, + GPIO_PX5, + GPIO_PX6, + GPIO_PX7, + GPIO_PY0, /* pin 192 */ + GPIO_PY1, + GPIO_PY2, + GPIO_PY3, + GPIO_PY4, + GPIO_PY5, + GPIO_PY6, + GPIO_PY7, + GPIO_PZ0, /* pin 200 */ + GPIO_PZ1, + GPIO_PZ2, + GPIO_PZ3, + GPIO_PZ4, + GPIO_PZ5, + GPIO_PZ6, + GPIO_PZ7, + GPIO_PAA0, /* pin 208 */ + GPIO_PAA1, + GPIO_PAA2, + GPIO_PAA3, + GPIO_PAA4, + GPIO_PAA5, + GPIO_PAA6, + GPIO_PAA7, + GPIO_PBB0, /* pin 216 */ + GPIO_PBB1, + GPIO_PBB2, + GPIO_PBB3, + GPIO_PBB4, + GPIO_PBB5, + GPIO_PBB6, + GPIO_PBB7, + GPIO_PCC0, /* pin 224 */ + GPIO_PCC1, + GPIO_PCC2, + GPIO_PCC3, + GPIO_PCC4, + GPIO_PCC5, + GPIO_PCC6, + GPIO_PCC7, + GPIO_PDD0, /* pin 232 */ + GPIO_PDD1, + GPIO_PDD2, + GPIO_PDD3, + GPIO_PDD4, + GPIO_PDD5, + GPIO_PDD6, + GPIO_PDD7, + GPIO_PEE0, /* pin 240 */ + GPIO_PEE1, + GPIO_PEE2, + GPIO_PEE3, + GPIO_PEE4, + GPIO_PEE5, + GPIO_PEE6, + GPIO_PEE7, + GPIO_PFF0, /* pin 248 */ + GPIO_PFF1, + GPIO_PFF2, + GPIO_PFF3, + GPIO_PFF4, + GPIO_PFF5, + GPIO_PFF6, + GPIO_PFF7, /* pin 255 */ +}; + +#endif /* _TEGRA210_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h new file mode 100644 index 0000000..77e9aa5 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/mc.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_MC_H_ +#define _TEGRA210_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[4]; /* offset 0x60 - 0x6C */ + u32 mc_security_cfg0; /* offset 0x70 */ + u32 mc_security_cfg1; /* offset 0x74 */ + u32 reserved4[6]; /* offset 0x7C - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved5[74]; /* offset 0x100 - 0x224 */ + u32 mc_smmu_translation_enable_0; /* offset 0x228 */ + u32 mc_smmu_translation_enable_1; /* offset 0x22C */ + u32 mc_smmu_translation_enable_2; /* offset 0x230 */ + u32 mc_smmu_translation_enable_3; /* offset 0x234 */ + u32 mc_smmu_afi_asid; /* offset 0x238 */ + u32 mc_smmu_avpc_asid; /* offset 0x23C */ + u32 mc_smmu_dc_asid; /* offset 0x240 */ + u32 mc_smmu_dcb_asid; /* offset 0x244 */ + u32 reserved6[2]; /* offset 0x248 - 0x24C */ + u32 mc_smmu_hc_asid; /* offset 0x250 */ + u32 mc_smmu_hda_asid; /* offset 0x254 */ + u32 mc_smmu_isp2_asid; /* offset 0x258 */ + u32 reserved7[2]; /* offset 0x25C - 0x260 */ + u32 mc_smmu_msenc_asid; /* offset 0x264 */ + u32 mc_smmu_nv_asid; /* offset 0x268 */ + u32 mc_smmu_nv2_asid; /* offset 0x26C */ + u32 mc_smmu_ppcs_asid; /* offset 0x270 */ + u32 mc_smmu_sata_asid; /* offset 0x274 */ + u32 reserved8[1]; /* offset 0x278 */ + u32 mc_smmu_vde_asid; /* offset 0x27C */ + u32 mc_smmu_vi_asid; /* offset 0x280 */ + u32 mc_smmu_vic_asid; /* offset 0x284 */ + u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ + u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ + u32 reserved9[1]; /* offset 0x290 */ + u32 mc_smmu_tsec_asid; /* offset 0x294 */ + u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ + u32 reserved10[235]; /* offset 0x29C - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) + +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) +#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) + +#endif /* _TEGRA210_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/pmu.h b/arch/arm/include/asm/arch-tegra210/pmu.h new file mode 100644 index 0000000..1e5f388 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/pmu.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2010-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_PMU_H_ +#define _TEGRA210_PMU_H_ + +/* Set core and CPU voltages to nominal levels */ +int pmu_set_nominal(void); + +#endif /* _TEGRA210_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/powergate.h b/arch/arm/include/asm/arch-tegra210/powergate.h new file mode 100644 index 0000000..df6f91d --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/powergate.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_POWERGATE_H_ +#define _TEGRA210_POWERGATE_H_ + +#include <asm/arch-tegra/powergate.h> + +#endif /* _TEGRA210_POWERGATE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/sysctr.h b/arch/arm/include/asm/arch-tegra210/sysctr.h new file mode 100644 index 0000000..e8a13b5 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/sysctr.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_SYSCTR_H_ +#define _TEGRA210_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA210_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h new file mode 100644 index 0000000..95c67fb --- /dev/null +++ b/arch/arm/include/asm/arch-tegra210/tegra.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_TEGRA_H_ +#define _TEGRA210_TEGRA_H_ + +#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ +#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ +#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ +#define NV_PA_SDRAM_BASE 0x80000000 + +#include <asm/arch-tegra/tegra.h> + +#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */ + +#undef NVBOOTINFOTABLE_BCTSIZE +#undef NVBOOTINFOTABLE_BCTPTR +#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ + +#define MAX_NUM_CPU 4 +#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) + +#define TEGRA_USB1_BASE 0x7D000000 + +#endif /* _TEGRA210_TEGRA_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index c9dc49d..7640eab 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -11,6 +11,11 @@ #define ZYNQ_SERIAL_BASEADDR0 0xFF000000 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000 +#define ZYNQ_GEM_BASEADDR0 0xFF0B0000 +#define ZYNQ_GEM_BASEADDR1 0xFF0C0000 +#define ZYNQ_GEM_BASEADDR2 0xFF0D0000 +#define ZYNQ_GEM_BASEADDR3 0xFF0E0000 + #define ZYNQ_SPI_BASEADDR0 0xFF040000 #define ZYNQ_SPI_BASEADDR1 0xFF050000 @@ -20,6 +25,8 @@ #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 +#define ZYNQMP_SATA_BASEADDR 0xFD0C0000 + #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 @@ -55,6 +62,15 @@ struct iou_scntr { #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 +#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 + +struct iou_slcr_regs { + u32 mio_pin[78]; + u32 reserved[442]; +}; + +#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) + #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 struct rpu_regs { diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index d8e0ba1..f5c90d1 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,7 +8,13 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +/* Setup clk for network */ +static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) +{ +} + int zynq_sdhci_init(unsigned long regbase); +int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index bb24f33..4e3ea55 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -8,10 +8,6 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H -#ifdef CONFIG_OMAP -#include <asm/omap_boot.h> -#endif - /* Architecture-specific global data */ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) @@ -45,8 +41,10 @@ struct arch_global_data { unsigned long tlb_size; #endif -#ifdef CONFIG_OMAP - struct omap_boot_parameters omap_boot_params; +#ifdef CONFIG_OMAP_COMMON + u32 omap_boot_device; + u32 omap_boot_mode; + u8 omap_ch_flags; #endif #ifdef CONFIG_FSL_LSCH3 unsigned long mem2_clk; diff --git a/arch/arm/include/asm/omap_boot.h b/arch/arm/include/asm/omap_boot.h deleted file mode 100644 index f77f9d6..0000000 --- a/arch/arm/include/asm/omap_boot.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * Sricharan R <r.sricharan@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ROM code defines */ -/* Boot device */ -#define BOOT_DEVICE_MASK 0xFF -#define BOOT_DEVICE_OFFSET 0x8 -#define DEV_DESC_PTR_OFFSET 0x4 -#define DEV_DATA_PTR_OFFSET 0x18 -#define BOOT_MODE_OFFSET 0x8 -#define RESET_REASON_OFFSET 0x9 -#define CH_FLAGS_OFFSET 0xA - -#define CH_FLAGS_CHSETTINGS (0x1 << 0) -#define CH_FLAGS_CHRAM (0x1 << 1) -#define CH_FLAGS_CHFLASH (0x1 << 2) -#define CH_FLAGS_CHMMCSD (0x1 << 3) - -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - char *boot_message; - unsigned int mem_boot_descriptor; - unsigned char omap_bootdevice; - unsigned char reset_reason; - unsigned char ch_flags; - unsigned long omap_bootmode; -}; -#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 5469435..056affc 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -688,4 +688,17 @@ static inline u8 is_dra72x(void) #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) #define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) +/* Boot parameters */ +#define DEVICE_DATA_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 + +#define CH_FLAGS_CHSETTINGS (1 << 0) +#define CH_FLAGS_CHRAM (1 << 1) +#define CH_FLAGS_CHFLASH (1 << 2) +#define CH_FLAGS_CHMMCSD (1 << 3) + +#ifndef __ASSEMBLY__ +u32 omap_sys_boot_device(void); +#endif + #endif /* _OMAP_COMMON_H_ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 760e8ab..868ea54 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -15,9 +15,15 @@ #define CR_EE (1 << 25) /* Exception (Big) Endian */ #define PGTABLE_SIZE (0x10000) +/* 2MB granularity */ +#define MMU_SECTION_SHIFT 21 #ifndef __ASSEMBLY__ +enum dcache_option { + DCACHE_OFF = 0x3, +}; + #define isb() \ ({asm volatile( \ "isb" : : : "memory"); \ @@ -265,16 +271,6 @@ enum { #endif /** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option); - -/** * Register an update to the page tables, and flush the TLB * * \param start start address of update in page table @@ -295,4 +291,17 @@ phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_ARM64 */ +#ifndef __ASSEMBLY__ +/** + * Change the cache settings for a region. + * + * \param start start address of memory region to change + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option); + +#endif /* __ASSEMBLY__ */ + #endif diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h index d3ab75f..2bdb71c 100644 --- a/arch/arm/include/asm/ti-common/sys_proto.h +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -36,7 +36,7 @@ static inline u8 uboot_loaded_by_spl(void) * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a * mandatory section if CH is present. */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + if (gd->arch.omap_ch_flags & CH_FLAGS_CHSETTINGS) return 0; else return running_from_sdram(); diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index bc9c53c..98a906e 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -74,7 +74,8 @@ zero_gd: cmp x0, x18 b.gt zero_gd #if defined(CONFIG_SYS_MALLOC_F_LEN) - sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + ldr x0, =CONFIG_SYS_MALLOC_F_LEN + sub x0, x18, x0 str x0, [x18, #GD_MALLOC_BASE] #endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index f9f58a3..73ceb83 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -55,8 +55,13 @@ U_BOOT_CMD(mon_install, 2, 0, do_mon_install, static void core_spin(void) { - while (1) - ; /* forever */; + while (1) { + asm volatile ( + "dsb\n" + "isb\n" + "wfi\n" + ); + } } int mon_power_on(int core_id, void *ep) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 54bd648..ba0b865 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,20 +1,49 @@ if TEGRA +config TEGRA_ARMV7_COMMON + bool "Tegra 32-bit" + select SUPPORT_SPL + select SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO + choice prompt "Tegra SoC select" optional config TEGRA20 bool "Tegra20 family" + select TEGRA_ARMV7_COMMON config TEGRA30 bool "Tegra30 family" + select TEGRA_ARMV7_COMMON config TEGRA114 bool "Tegra114 family" + select TEGRA_ARMV7_COMMON config TEGRA124 bool "Tegra124 family" + select TEGRA_ARMV7_COMMON + +config TEGRA210 + bool "Tegra210 family" + select OF_CONTROL + select ARM64 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO endchoice @@ -25,5 +54,6 @@ source "arch/arm/mach-tegra/tegra20/Kconfig" source "arch/arm/mach-tegra/tegra30/Kconfig" source "arch/arm/mach-tegra/tegra114/Kconfig" source "arch/arm/mach-tegra/tegra124/Kconfig" +source "arch/arm/mach-tegra/tegra210/Kconfig" endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fefc180..0db8ee0 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2010,2011 Nvidia Corporation. +# (C) Copyright 2010-2015 Nvidia Corporation. # # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -24,7 +24,9 @@ obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o +#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?) obj-$(CONFIG_TEGRA124) += vpr.o +obj-$(CONFIG_TEGRA210) += vpr.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o ifndef CONFIG_SPL_BUILD @@ -35,3 +37,4 @@ obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ obj-$(CONFIG_TEGRA114) += tegra114/ obj-$(CONFIG_TEGRA124) += tegra124/ +obj-$(CONFIG_TEGRA210) += tegra210/ diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 0b94e8a..e62dda5 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -1,5 +1,5 @@ /* -* (C) Copyright 2010-2014 +* (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -92,6 +92,13 @@ int tegra_get_chip_sku(void) return TEGRA_SOC_T124; } break; + case CHIPID_TEGRA210: + switch (sku_id) { + case SKU_ID_T210_ENG: + default: + return TEGRA_SOC_T210; + } + break; } /* unknown chip/sku id */ @@ -100,6 +107,7 @@ int tegra_get_chip_sku(void) return TEGRA_SOC_UNKNOWN; } +#ifndef CONFIG_ARM64 static void enable_scu(void) { struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; @@ -131,8 +139,8 @@ static u32 get_odmdata(void) * on BCTs for currently supported SoCs, which are locked down. * If this changes in new chips, we can revisit this algorithm. */ - - u32 bct_start, odmdata; + unsigned long bct_start; + u32 odmdata; bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR); odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); @@ -222,3 +230,4 @@ void s_init(void) /* init vpr */ config_vpr(); } +#endif diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 222de6a..40de72d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -1,11 +1,12 @@ /* - * (C) Copyright 2010-2014 + * (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <spl.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> @@ -17,6 +18,8 @@ #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/warmboot.h> +void save_boot_params_ret(void); + DECLARE_GLOBAL_DATA_PTR; enum { @@ -29,6 +32,21 @@ enum { UART_COUNT = 5, }; +static bool from_spl __attribute__ ((section(".data"))); + +#ifndef CONFIG_SPL_BUILD +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ + from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; + save_boot_params_ret(); +} +#endif + +bool spl_was_boot_source(void) +{ + return from_spl; +} + #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) #if !defined(CONFIG_TEGRA124) #error tegra_cpu_is_non_secure has only been validated on Tegra124 @@ -125,12 +143,18 @@ static int uart_configs[] = { -1, FUNCMUX_UART4_GMI, /* UARTD */ -1, -#else /* Tegra124 */ +#elif defined(CONFIG_TEGRA124) FUNCMUX_UART1_KBC, /* UARTA */ -1, -1, FUNCMUX_UART4_GPIO, /* UARTD */ -1, +#else /* Tegra210 */ + FUNCMUX_UART1_UART1, /* UARTA */ + -1, + -1, + FUNCMUX_UART4_UART4, /* UARTD */ + -1, #endif }; @@ -182,7 +206,7 @@ void board_init_uart_f(void) setup_uarts(uart_ids); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index ce9b695..36bcfb0 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -196,6 +196,12 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { + /* Do any special system timer/TSC setup */ +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) + if (!tegra_cpu_is_non_secure()) +#endif + arch_timer_init(); + pinmux_init(); board_init_uart_f(); @@ -274,3 +280,19 @@ void pad_init_mmc(struct mmc_host *host) #endif /* T30 */ } #endif /* MMC */ + +#ifdef CONFIG_ARM64 +/* + * Most hardware on 64-bit Tegra is still restricted to DMA to the lower + * 32-bits of the physical address space. Cap the maximum usable RAM area + * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit + * boundary that most devices can address. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + if (gd->ram_top > 0x100000000) + return 0x100000000; + + return gd->ram_top; +} +#endif diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 94f5bce..0e9cb97 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -21,6 +21,7 @@ #include <asm/arch-tegra/ap.h> #include <asm/arch/gp_padctrl.h> +#ifndef CONFIG_ARM64 void config_cache(void) { u32 reg = 0; @@ -44,3 +45,4 @@ void config_cache(void) reg |= 2; asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); } +#endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 24047b8..5d968d8 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -113,7 +113,11 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, data = readl(&pll->pll_misc); *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT; *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT; - +#if defined(CONFIG_TEGRA210) + /* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */ + *cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT; + *lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT; +#endif return 0; } @@ -132,14 +136,28 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, * - same fields are always mapped at same offsets, except DCCON * - DCCON is always 0, doesn't conflict * - M,N, P of PLLP values are ignored for PLLP + * NOTE: Above is no longer true with T210 - TBD: FIX THIS */ misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); +#if defined(CONFIG_TEGRA210) + /* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */ + if (clkid == CLOCK_ID_USB) { + /* preserve EN_LOCKDET, set by default */ + misc_data = readl(&pll->pll_misc); + misc_data |= (cpcon << PLLU_KCP_SHIFT) | + (lfcon << PLLU_KVCO_SHIFT); + } +#endif data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); if (clkid == CLOCK_ID_USB) +#if defined(CONFIG_TEGRA210) + data |= divp << PLLU_DIVP_SHIFT; +#else data |= divp << PLLU_VCO_FREQ_SHIFT; +#endif else data |= divp << PLL_DIVP_SHIFT; if (pll) { @@ -534,8 +552,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) /* Set cpcon to PLL_MISC */ misc_reg = readl(&pll->pll_misc); +#if !defined(CONFIG_TEGRA210) misc_reg &= ~PLL_CPCON_MASK; misc_reg |= cpcon << PLL_CPCON_SHIFT; +#else + /* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */ + misc_reg &= ~PLLU_KCP_MASK; + misc_reg |= cpcon << PLLU_KCP_SHIFT; +#endif + writel(misc_reg, &pll->pll_misc); /* Enable PLL */ @@ -608,12 +633,6 @@ void clock_init(void) debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); - - /* Do any special system timer/TSC setup */ -#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) - if (!tegra_cpu_is_non_secure()) -#endif - arch_timer_init(); } static void set_avp_clock_source(u32 src) @@ -634,6 +653,7 @@ static void set_avp_clock_source(u32 src) /* * This function is useful on Tegra30, and any later SoCs that have compatible * PLLP configuration registers. + * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c */ void tegra30_set_up_pllp(void) { diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index c6f3b02..f7d45e8 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -29,6 +29,7 @@ int get_num_cpus(void) { struct apb_misc_gp_ctlr *gp; uint rev; + debug("%s entry\n", __func__); gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; @@ -39,6 +40,8 @@ int get_num_cpus(void) break; case CHIPID_TEGRA30: case CHIPID_TEGRA114: + case CHIPID_TEGRA124: + case CHIPID_TEGRA210: default: return 4; break; @@ -128,13 +131,30 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, + + /* + * T210: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 24:20 5 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ + }, }; static inline void pllx_set_iddq(void) { -#if defined(CONFIG_TEGRA124) +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 reg; + debug("%s entry\n", __func__); /* Disable IDDQ */ reg = readl(&clkrst->crc_pllx_misc3); @@ -151,15 +171,14 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, { int chip = tegra_get_chip(); u32 reg; + debug("%s entry\n", __func__); /* If PLLX is already enabled, just return */ if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { - debug("pllx_set_rate: PLLX already enabled, returning\n"); + debug("%s: PLLX already enabled, returning\n", __func__); return 0; } - debug(" pllx_set_rate entry\n"); - pllx_set_iddq(); /* Set BYPASS, m, n and p to PLLX_BASE */ @@ -182,19 +201,19 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, reg = readl(&pll->pll_base); reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); - debug("pllx_set_rate: base = 0x%08X\n", reg); + debug("%s: base = 0x%08X\n", __func__, reg); /* Set lock_enable to PLLX_MISC */ reg = readl(&pll->pll_misc); reg |= PLL_LOCK_ENABLE_MASK; writel(reg, &pll->pll_misc); - debug("pllx_set_rate: misc = 0x%08X\n", reg); + debug("%s: misc = 0x%08X\n", __func__, reg); /* Enable PLLX last, once it's all configured */ reg = readl(&pll->pll_base); reg |= PLL_ENABLE_MASK; writel(reg, &pll->pll_base); - debug("pllx_set_rate: base final = 0x%08X\n", reg); + debug("%s: base final = 0x%08X\n", __func__, reg); return 0; } @@ -206,24 +225,23 @@ void init_pllx(void) int soc_type, sku_info, chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; - - debug("init_pllx entry\n"); + debug("%s entry\n", __func__); /* get SOC (chip) type */ soc_type = tegra_get_chip(); - debug(" init_pllx: SoC = 0x%02X\n", soc_type); + debug("%s: SoC = 0x%02X\n", __func__, soc_type); /* get SKU info */ sku_info = tegra_get_sku_info(); - debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info); + debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info); /* get chip SKU, combo of the above info */ chip_sku = tegra_get_chip_sku(); - debug(" init_pllx: Chip SKU = %d\n", chip_sku); + debug("%s: Chip SKU = %d\n", __func__, chip_sku); /* get osc freq */ osc = clock_get_osc_freq(); - debug(" init_pllx: osc = %d\n", osc); + debug("%s: osc = %d\n", __func__, osc); /* set pllx */ sel = &tegra_pll_x_table[chip_sku][osc]; @@ -234,6 +252,7 @@ void enable_cpu_clock(int enable) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; u32 clk; + debug("%s entry\n", __func__); /* * NOTE: @@ -282,6 +301,7 @@ static void remove_cpu_io_clamps(void) { struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; + debug("%s entry\n", __func__); /* Remove the clamps on the CPU I/O signals */ reg = readl(&pmc->pmc_remove_clamping); @@ -297,6 +317,7 @@ void powerup_cpu(void) struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; + debug("%s entry\n", __func__); if (!is_cpu_powered()) { /* Toggle the CPU power state (OFF -> ON) */ @@ -336,7 +357,7 @@ void reset_A9_cpu(int reset) int num_cpus = get_num_cpus(); int cpu; - debug("reset_a9_cpu entry\n"); + debug("%s entry\n", __func__); /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ for (cpu = 1; cpu < num_cpus; cpu++) reset_cmplx_set_enable(cpu, mask, 1); @@ -350,7 +371,7 @@ void clock_enable_coresight(int enable) { u32 rst, src = 2; - debug("clock_enable_coresight entry\n"); + debug("%s entry\n", __func__); clock_set_enable(PERIPH_ID_CORESIGHT, enable); reset_set_enable(PERIPH_ID_CORESIGHT, !enable); @@ -377,6 +398,8 @@ void clock_enable_coresight(int enable) void halt_avp(void) { + debug("%s entry\n", __func__); + for (;;) { writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29), FLOW_CTLR_HALT_COP_EVENTS); diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index b4ca44f..3f38969 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2014 + * (C) Copyright 2010-2015 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,7 +14,7 @@ #define NVBL_PLLP_KHZ 216000 #define CSITE_KHZ 144000 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ - defined(CONFIG_TEGRA124) + defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) #define NVBL_PLLP_KHZ 408000 #define CSITE_KHZ 204000 #else @@ -35,7 +35,7 @@ #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ #define PG_UP_TAG_0 0x0 -#define CORESIGHT_UNLOCK 0xC5ACCE55; +#define CORESIGHT_UNLOCK 0xC5ACCE55 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) @@ -53,6 +53,10 @@ #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) +/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ +#define SB_AA64_RESET_LOW 0x6000C230 +#define SB_AA64_RESET_HIGH 0x6000C234 + struct clk_pll_table { u16 n; u16 m; diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index 4bc0a3f..1273f94 100644 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S @@ -10,6 +10,20 @@ #include <config.h> #include <linux/linkage.h> +#ifdef CONFIG_ARM64 + .align 5 +ENTRY(reset_cpu) + /* get address for global reset register */ + ldr x1, =PRM_RSTCTRL + ldr w3, [x1] + /* force reset */ + orr w3, w3, #0x10 + str w3, [x1] + mov w0, w0 +1: + b 1b +ENDPROC(reset_cpu) +#else .align 5 ENTRY(reset_cpu) ldr r1, rstctl @ get addr for global reset @@ -23,3 +37,4 @@ _loop_forever: rstctl: .word PRM_RSTCTRL ENDPROC(reset_cpu) +#endif diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index b4a1432..5862c4a 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -78,7 +78,7 @@ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) #endif -#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset)) +#define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset)) #if defined(CONFIG_TEGRA20) diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig new file mode 100644 index 0000000..147e6a8 --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -0,0 +1,18 @@ +if TEGRA210 + +choice + prompt "Tegra210 board select" + +config TARGET_P2571 + bool "NVIDIA Tegra210 P2571 base board" + help + P2571 is a P2530 married to a P1963 I/O board + +endchoice + +config SYS_SOC + default "tegra210" + +source "board/nvidia/p2571/Kconfig" + +endif diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile new file mode 100644 index 0000000..1fb8d1a --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clock.o +obj-y += funcmux.o +obj-y += pinmux.o +obj-y += xusb-padctl.o diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c new file mode 100644 index 0000000..4e7d793 --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -0,0 +1,1091 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra210 Clock control functions */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/sysctr.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/timer.h> +#include <div64.h> +#include <fdtdec.h> + +/* + * Clock types that we can use as a source. The Tegra210 has muxes for the + * peripheral clocks, and in most cases there are four options for the clock + * source. This gives us a clock 'type' and exploits what commonality exists + * in the device. + * + * Letters are obvious, except for T which means CLK_M, and S which means the + * clock derived from 32KHz. Beware that CLK_M (also called OSC in the + * datasheet) and PLL_M are different things. The former is the basic + * clock supplied to the SOC from an external oscillator. The latter is the + * memory clock PLL. + * + * See definitions in clock_id in the header file. + */ +enum clock_type_id { + CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ + CLOCK_TYPE_MCPA, /* and so on */ + CLOCK_TYPE_MCPT, + CLOCK_TYPE_PCM, + CLOCK_TYPE_PCMT, + CLOCK_TYPE_PDCT, + CLOCK_TYPE_ACPT, + CLOCK_TYPE_ASPTE, + CLOCK_TYPE_PMDACD2T, + CLOCK_TYPE_PCST, + + CLOCK_TYPE_PC2CC3M, + CLOCK_TYPE_PC2CC3S_T, + CLOCK_TYPE_PC2CC3M_T, + CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ + CLOCK_TYPE_MC2CC3P_A, + CLOCK_TYPE_M, + CLOCK_TYPE_MCPTM2C2C3, + CLOCK_TYPE_PC2CC3T_S, + CLOCK_TYPE_AC2CC3P_TS2, + CLOCK_TYPE_PC01C00_C42C41TC40, + + CLOCK_TYPE_COUNT, + CLOCK_TYPE_NONE = -1, /* invalid clock type */ +}; + +enum { + CLOCK_MAX_MUX = 8 /* number of source options for each clock */ +}; + +/* + * Clock source mux for each clock type. This just converts our enum into + * a list of mux sources for use by the code. + * + * Note: + * The extra column in each clock source array is used to store the mask + * bits in its register for the source. + */ +#define CLK(x) CLOCK_ID_ ## x +static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { + { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), + CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), + CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_28}, + + /* Additional clock types on Tegra114+ */ + /* CLOCK_TYPE_PC2CC3M */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3S_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_MC2CC3P_A */ + { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_M */ + { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + /* CLOCK_TYPE_MCPTM2C2C3 */ + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3T_S */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_AC2CC3P_TS2 */ + { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC01C00_C42C41TC40 */ + { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE), + CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0), + MASK_BITS_31_29}, +}; + +/* + * Clock type for each peripheral clock source. We put the name in each + * record just so it is easy to match things up + */ +#define TYPE(name, type) type +static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { + /* 0x00 */ + TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), + TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), + + /* 0x08 */ + TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), + TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), + + /* 0x10 */ + TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), + + /* 0x18 */ + TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), + + /* 0x20 */ + TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_23h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), + + /* 0x28 */ + TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), + + /* 0x30 */ + TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), + + /* 0x38 */ + TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), + + /* 0x40 */ + TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), + TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), + + /* 0x48 */ + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), + + /* 0x50 */ + TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), + TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), + TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), + + /* 0x58 */ + TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), + + /* 0x60 */ + TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), + TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), + + /* 0x68 */ + TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), + TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), + TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE), + + /* 0x70 */ + TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), + TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), + + /* 0x78 */ + TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), + TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), + TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), + + /* 0x80 */ + TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE), + TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE), + TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE), + TYPE(PERIPHC_84h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_85h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_86h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_87h, CLOCK_TYPE_NONE), + + /* 0x88 */ + TYPE(PERIPHC_88h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_89h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE), + TYPE(PERIPHC_APE, CLOCK_TYPE_NONE), + TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40), + TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE), + TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE), + TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE), + + /* 0x90 */ + TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE), + TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE), +}; + +/* + * This array translates a periph_id to a periphc_internal_id + * + * Not present/matched up: + * uint vi_sensor; _VI_SENSOR_0, 0x1A8 + * SPDIF - which is both 0x08 and 0x0c + * + */ +#define NONE(name) (-1) +#define OFFSET(name, value) PERIPHC_ ## name +#define INTERNAL_ID(id) (id & 0x000000ff) +static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { + /* Low word: 31:0 */ + NONE(CPU), + NONE(COP), + NONE(TRIGSYS), + NONE(ISPB), + NONE(RESERVED4), + NONE(TMR), + PERIPHC_UART1, + PERIPHC_UART2, /* and vfir 0x68 */ + + /* 8 */ + NONE(GPIO), + PERIPHC_SDMMC2, + PERIPHC_SPDIF_IN, + PERIPHC_I2S2, + PERIPHC_I2C1, + NONE(RESERVED13), + PERIPHC_SDMMC1, + PERIPHC_SDMMC4, + + /* 16 */ + NONE(TCW), + PERIPHC_PWM, + PERIPHC_I2S3, + NONE(RESERVED19), + PERIPHC_VI, + NONE(RESERVED21), + NONE(USBD), + NONE(ISP), + + /* 24 */ + NONE(RESERVED24), + NONE(RESERVED25), + PERIPHC_DISP2, + PERIPHC_DISP1, + PERIPHC_HOST1X, + NONE(VCP), + PERIPHC_I2S1, + NONE(CACHE2), + + /* Middle word: 63:32 */ + NONE(MEM), + NONE(AHBDMA), + NONE(APBDMA), + NONE(RESERVED35), + NONE(RESERVED36), + NONE(STAT_MON), + NONE(RESERVED38), + NONE(FUSE), + + /* 40 */ + NONE(KFUSE), + PERIPHC_SBC1, /* SBCx = SPIx */ + PERIPHC_NOR, + NONE(RESERVED43), + PERIPHC_SBC2, + NONE(XIO), + PERIPHC_SBC3, + PERIPHC_I2C5, + + /* 48 */ + NONE(DSI), + NONE(RESERVED49), + PERIPHC_HSI, + NONE(RESERVED51), + NONE(CSI), + NONE(RESERVED53), + PERIPHC_I2C2, + PERIPHC_UART3, + + /* 56 */ + NONE(MIPI_CAL), + PERIPHC_EMC, + NONE(USB2), + NONE(USB3), + NONE(RESERVED60), + PERIPHC_VDE, + NONE(BSEA), + NONE(BSEV), + + /* Upper word 95:64 */ + NONE(RESERVED64), + PERIPHC_UART4, + PERIPHC_UART5, + PERIPHC_I2C3, + PERIPHC_SBC4, + PERIPHC_SDMMC3, + NONE(PCIE), + PERIPHC_OWR, + + /* 72 */ + NONE(AFI), + PERIPHC_CSITE, + NONE(PCIEXCLK), + NONE(AVPUCQ), + NONE(LA), + NONE(TRACECLKIN), + NONE(SOC_THERM), + NONE(DTV), + + /* 80 */ + NONE(RESERVED80), + PERIPHC_I2CSLOW, + NONE(DSIB), + PERIPHC_TSEC, + NONE(RESERVED84), + NONE(RESERVED85), + NONE(RESERVED86), + NONE(EMUCIF), + + /* 88 */ + NONE(RESERVED88), + NONE(XUSB_HOST), + NONE(RESERVED90), + PERIPHC_MSENC, + NONE(RESERVED92), + NONE(RESERVED93), + NONE(RESERVED94), + NONE(XUSB_DEV), + + /* V word: 31:0 */ + NONE(CPUG), + NONE(CPULP), + NONE(V_RESERVED2), + PERIPHC_MSELECT, + NONE(V_RESERVED4), + PERIPHC_I2S4, + PERIPHC_I2S5, + PERIPHC_I2C4, + + /* 104 */ + PERIPHC_SBC5, + PERIPHC_SBC6, + PERIPHC_AUDIO, + NONE(APBIF), + NONE(V_RESERVED12), + NONE(V_RESERVED13), + NONE(V_RESERVED14), + PERIPHC_HDA2CODEC2X, + + /* 112 */ + NONE(ATOMICS), + NONE(V_RESERVED17), + NONE(V_RESERVED18), + NONE(V_RESERVED19), + NONE(V_RESERVED20), + NONE(V_RESERVED21), + NONE(V_RESERVED22), + PERIPHC_ACTMON, + + /* 120 */ + NONE(EXTPERIPH1), + NONE(EXTPERIPH2), + NONE(EXTPERIPH3), + NONE(OOB), + PERIPHC_SATA, + PERIPHC_HDA, + NONE(TZRAM), + NONE(SE), + + /* W word: 31:0 */ + NONE(HDA2HDMICODEC), + NONE(SATACOLD), + NONE(W_RESERVED2), + NONE(W_RESERVED3), + NONE(W_RESERVED4), + NONE(W_RESERVED5), + NONE(W_RESERVED6), + NONE(W_RESERVED7), + + /* 136 */ + NONE(CEC), + NONE(W_RESERVED9), + NONE(W_RESERVED10), + NONE(W_RESERVED11), + NONE(W_RESERVED12), + NONE(W_RESERVED13), + NONE(XUSB_PADCTL), + NONE(W_RESERVED15), + + /* 144 */ + NONE(W_RESERVED16), + NONE(W_RESERVED17), + NONE(W_RESERVED18), + NONE(W_RESERVED19), + NONE(W_RESERVED20), + NONE(ENTROPY), + NONE(DDS), + NONE(W_RESERVED23), + + /* 152 */ + NONE(W_RESERVED24), + NONE(W_RESERVED25), + NONE(W_RESERVED26), + NONE(DVFS), + NONE(XUSB_SS), + NONE(W_RESERVED29), + NONE(W_RESERVED30), + NONE(W_RESERVED31), + + /* X word: 31:0 */ + NONE(SPARE), + NONE(X_RESERVED1), + NONE(X_RESERVED2), + NONE(X_RESERVED3), + NONE(CAM_MCLK), + NONE(CAM_MCLK2), + PERIPHC_I2C6, + NONE(X_RESERVED7), + + /* 168 */ + NONE(X_RESERVED8), + NONE(X_RESERVED9), + NONE(X_RESERVED10), + NONE(VIM2_CLK), + NONE(X_RESERVED12), + NONE(X_RESERVED13), + NONE(EMC_DLL), + NONE(X_RESERVED15), + + /* 176 */ + NONE(X_RESERVED16), + NONE(CLK72MHZ), + NONE(VIC), + NONE(X_RESERVED19), + NONE(X_RESERVED20), + NONE(DPAUX), + NONE(SOR0), + NONE(X_RESERVED23), + + /* 184 */ + NONE(GPU), + NONE(X_RESERVED25), + NONE(X_RESERVED26), + NONE(X_RESERVED27), + NONE(X_RESERVED28), + NONE(X_RESERVED29), + NONE(X_RESERVED30), + NONE(X_RESERVED31), + + /* Y: 192 (192 - 223) */ + NONE(Y_RESERVED0), + PERIPHC_SDMMC_LEGACY_TM, + PERIPHC_NVDEC, + PERIPHC_NVJPG, + NONE(Y_RESERVED4), + PERIPHC_DMIC3, /* 197 */ + PERIPHC_APE, /* 198 */ + NONE(Y_RESERVED7), + + /* 200 */ + NONE(Y_RESERVED8), + NONE(Y_RESERVED9), + NONE(Y_RESERVED10), + NONE(Y_RESERVED11), + NONE(Y_RESERVED12), + NONE(Y_RESERVED13), + NONE(Y_RESERVED14), + NONE(Y_RESERVED15), + + /* 208 */ + PERIPHC_VI_I2C, /* 208 */ + NONE(Y_RESERVED17), + NONE(Y_RESERVED18), + PERIPHC_QSPI, /* 211 */ + NONE(Y_RESERVED20), + NONE(Y_RESERVED21), + NONE(Y_RESERVED22), + NONE(Y_RESERVED23), + + /* 216 */ + NONE(Y_RESERVED24), + NONE(Y_RESERVED25), + NONE(Y_RESERVED26), + PERIPHC_NVENC, /* 219 */ + NONE(Y_RESERVED28), + NONE(Y_RESERVED29), + NONE(Y_RESERVED30), + NONE(Y_RESERVED31), +}; + +/* + * Get the oscillator frequency, from the corresponding hardware configuration + * field. Note that Tegra30+ support 3 new higher freqs, but we map back + * to the old T20 freqs. Support for the higher oscillators is TBD. + */ +enum clock_osc_freq clock_get_osc_freq(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + reg = readl(&clkrst->crc_osc_ctrl); + reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + /* + * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz, + * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz + */ + if (reg == 5) { + debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg); + /* Map it to 19.2MHz for now. 38.4MHz OSC support TBD */ + return 1; + } + + /* + * Map to most common (T20) freqs (except 38.4, handled above): + * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3 + */ + return reg >> 2; +} + +/* Returns a pointer to the clock source register for a peripheral */ +u32 *get_periph_source_reg(enum periph_id periph_id) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + enum periphc_internal_id internal_id; + + /* Coresight is a special case */ + if (periph_id == PERIPH_ID_CSI) + return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; + + assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); + internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); + assert(internal_id != -1); + + if (internal_id < PERIPHC_VW_FIRST) + /* L, H, U */ + return &clkrst->crc_clk_src[internal_id]; + + if (internal_id < PERIPHC_X_FIRST) { + /* VW */ + internal_id -= PERIPHC_VW_FIRST; + return &clkrst->crc_clk_src_vw[internal_id]; + } + + if (internal_id < PERIPHC_Y_FIRST) { + /* X */ + internal_id -= PERIPHC_X_FIRST; + return &clkrst->crc_clk_src_x[internal_id]; + } + + /* Y */ + internal_id -= PERIPHC_Y_FIRST; + return &clkrst->crc_clk_src_y[internal_id]; +} + +/** + * Given a peripheral ID and the required source clock, this returns which + * value should be programmed into the source mux for that peripheral. + * + * There is special code here to handle the one source type with 5 sources. + * + * @param periph_id peripheral to start + * @param source PLL id of required parent clock + * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) + * @return mux value (0-4, or -1 if not found) + */ +int get_periph_clock_source(enum periph_id periph_id, + enum clock_id parent, int *mux_bits, int *divider_bits) +{ + enum clock_type_id type; + enum periphc_internal_id internal_id; + int mux; + + assert(clock_periph_id_isvalid(periph_id)); + + internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]); + assert(periphc_internal_id_isvalid(internal_id)); + + type = clock_periph_type[internal_id]; + assert(clock_type_id_isvalid(type)); + + *mux_bits = clock_source[type][CLOCK_MAX_MUX]; + + if (type == CLOCK_TYPE_PC2CC3M_T16) + *divider_bits = 16; + else + *divider_bits = 8; + + for (mux = 0; mux < CLOCK_MAX_MUX; mux++) + if (clock_source[type][mux] == parent) + return mux; + + /* if we get here, either us or the caller has made a mistake */ + printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, + parent); + return -1; +} + +void clock_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *clk; + u32 reg; + + /* Enable/disable the clock to this peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) + clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; + else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) + clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; + else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) + clk = &clkrst->crc_clk_out_enb_x; + else + clk = &clkrst->crc_clk_out_enb_y; + + reg = readl(clk); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, clk); +} + +void reset_set_enable(enum periph_id periph_id, int enable) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 *reset; + u32 reg; + + /* Enable/disable reset to the peripheral */ + assert(clock_periph_id_isvalid(periph_id)); + if (periph_id < PERIPH_ID_VW_FIRST) + reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; + else if ((int)periph_id < (int)PERIPH_ID_X_FIRST) + reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; + else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST) + reset = &clkrst->crc_rst_devices_x; + else + reset = &clkrst->crc_rst_devices_y; + + reg = readl(reset); + if (enable) + reg |= PERIPH_MASK(periph_id); + else + reg &= ~PERIPH_MASK(periph_id); + writel(reg, reset); +} + +#ifdef CONFIG_OF_CONTROL +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra210 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +enum periph_id clk_id_to_periph_id(int clk_id) +{ + if (clk_id > PERIPH_ID_COUNT) + return PERIPH_ID_NONE; + + switch (clk_id) { + case PERIPH_ID_RESERVED4: + case PERIPH_ID_RESERVED25: + case PERIPH_ID_RESERVED35: + case PERIPH_ID_RESERVED36: + case PERIPH_ID_RESERVED38: + case PERIPH_ID_RESERVED43: + case PERIPH_ID_RESERVED49: + case PERIPH_ID_RESERVED53: + case PERIPH_ID_RESERVED64: + case PERIPH_ID_RESERVED84: + case PERIPH_ID_RESERVED85: + case PERIPH_ID_RESERVED86: + case PERIPH_ID_RESERVED88: + case PERIPH_ID_RESERVED90: + case PERIPH_ID_RESERVED92: + case PERIPH_ID_RESERVED93: + case PERIPH_ID_RESERVED94: + case PERIPH_ID_V_RESERVED2: + case PERIPH_ID_V_RESERVED4: + case PERIPH_ID_V_RESERVED17: + case PERIPH_ID_V_RESERVED18: + case PERIPH_ID_V_RESERVED19: + case PERIPH_ID_V_RESERVED20: + case PERIPH_ID_V_RESERVED21: + case PERIPH_ID_V_RESERVED22: + case PERIPH_ID_W_RESERVED2: + case PERIPH_ID_W_RESERVED3: + case PERIPH_ID_W_RESERVED4: + case PERIPH_ID_W_RESERVED5: + case PERIPH_ID_W_RESERVED6: + case PERIPH_ID_W_RESERVED7: + case PERIPH_ID_W_RESERVED9: + case PERIPH_ID_W_RESERVED10: + case PERIPH_ID_W_RESERVED11: + case PERIPH_ID_W_RESERVED12: + case PERIPH_ID_W_RESERVED13: + case PERIPH_ID_W_RESERVED15: + case PERIPH_ID_W_RESERVED16: + case PERIPH_ID_W_RESERVED17: + case PERIPH_ID_W_RESERVED18: + case PERIPH_ID_W_RESERVED19: + case PERIPH_ID_W_RESERVED20: + case PERIPH_ID_W_RESERVED23: + case PERIPH_ID_W_RESERVED29: + case PERIPH_ID_W_RESERVED30: + case PERIPH_ID_W_RESERVED31: + return PERIPH_ID_NONE; + default: + return clk_id; + } +} +#endif /* CONFIG_OF_CONTROL */ + +/* + * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here. + * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM. + */ +void tegra210_setup_pllp(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */ + + /* OUT1 */ + /* Assert RSTN before enable */ + reg = PLLP_OUT1_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); + /* Set divisor and reenable */ + reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) + | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); + + /* OUT3, 4 */ + /* Assert RSTN before enable */ + reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + /* Set divisor and reenable */ + reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) + | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) + | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + + /* + * NOTE: If you want to change PLLP_OUT2 away from 204MHz, + * you can change PLLP_BASE DIVP here. Currently defaults + * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz. + * See Table 13 in section 5.1.4 in T210 TRM for more info. + */ +} + +void clock_early_init(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 data; + + tegra210_setup_pllp(); + + /* + * PLLC output frequency set to 600Mhz + * PLLD output frequency set to 925Mhz + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); + break; + + case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); + break; + + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); + break; + case CLOCK_OSC_FREQ_19_2: + clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); + clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); + break; + default: + /* + * These are not supported. It is too early to print a + * message and the UART likely won't work anyway due to the + * oscillator being wrong. + */ + break; + } + + /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */ + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, + (1 << PLLC_IDDQ)); + udelay(2); + + /* + * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps + * to pll_out[1] + */ + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], + (1 << PLLC_RESET)); + udelay(2); + + /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */ + data = (1 << PLLD_ENABLE_CLK) | (1 << PLLD_EN_LCKDET); + writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); + udelay(2); +} + +void arch_timer_init(void) +{ + struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; + u32 freq, val; + + freq = clock_get_rate(CLOCK_ID_OSC); + debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + + /* ARM CNTFRQ */ +#ifndef CONFIG_ARM64 + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); +#endif + + /* Only Tegra114+ has the System Counter regs */ + debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); + writel(freq, &sysctr->cntfid0); + + val = readl(&sysctr->cntcr); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel(val, &sysctr->cntcr); + debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); +} + +#define PLLE_SS_CNTL 0x68 +#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) +#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) +#define PLLE_SS_CNTL_SSCINVERT (1 << 15) +#define PLLE_SS_CNTL_SSCCENTER (1 << 14) +#define PLLE_SS_CNTL_SSCBYP (1 << 12) +#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) +#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) +#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) + +#define PLLE_BASE 0x0e8 +#define PLLE_BASE_ENABLE (1 << 30) +#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) +#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) +#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) +#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) + +#define PLLE_MISC 0x0ec +#define PLLE_MISC_IDDQ_SWCTL (1 << 14) +#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) +#define PLLE_MISC_PTS (1 << 8) +#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) +#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) + +#define PLLE_AUX 0x48c +#define PLLE_AUX_SEQ_ENABLE (1 << 24) +#define PLLE_AUX_ENABLE_SWCTL (1 << 4) + +int tegra_plle_enable(void) +{ + unsigned int m = 1, n = 200, cpcon = 13; + u32 value; + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value &= ~PLLE_BASE_LOCK_OVERRIDE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); + value |= PLLE_AUX_ENABLE_SWCTL; + value &= ~PLLE_AUX_SEQ_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value |= PLLE_MISC_IDDQ_SWCTL; + value &= ~PLLE_MISC_IDDQ_OVERRIDE; + value |= PLLE_MISC_LOCK_ENABLE; + value |= PLLE_MISC_PTS; + value |= PLLE_MISC_VREG_BG_CTRL(3); + value |= PLLE_MISC_VREG_CTRL(2); + writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); + + udelay(5); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | + PLLE_SS_CNTL_BYPASS_SS; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value &= ~PLLE_BASE_PLDIV_CML(0xf); + value &= ~PLLE_BASE_NDIV(0xff); + value &= ~PLLE_BASE_MDIV(0xff); + value |= PLLE_BASE_PLDIV_CML(cpcon); + value |= PLLE_BASE_NDIV(n); + value |= PLLE_BASE_MDIV(m); + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); + value |= PLLE_BASE_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); + + /* wait for lock */ + udelay(300); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_SSCINVERT; + value &= ~PLLE_SS_CNTL_SSCCENTER; + + value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); + value &= ~PLLE_SS_CNTL_SSCINC(0xff); + value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); + + value |= PLLE_SS_CNTL_SSCINCINTR(0x20); + value |= PLLE_SS_CNTL_SSCINC(0x01); + value |= PLLE_SS_CNTL_SSCMAX(0x25); + + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_SSCBYP; + value &= ~PLLE_SS_CNTL_BYPASS_SS; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + value &= ~PLLE_SS_CNTL_INTERP_RESET; + writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); + + udelay(1); + + return 0; +} diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/arch/arm/mach-tegra/tegra210/funcmux.c new file mode 100644 index 0000000..618d228 --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/funcmux.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Tegra210 high-level function multiplexing */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> + +int funcmux_select(enum periph_id id, int config) +{ + int bad_config = config != FUNCMUX_DEFAULT; + + switch (id) { + /* + * Add other periph IDs here as needed. + * Note that all pinmux/pads should have already + * been set up in the board pinmux table in + * pinmux-config-<board>.h for all periphs. + * Leave this in for the odd case where a mux + * needs to be changed on-the-fly. + */ + + default: + debug("%s: invalid periph_id %d", __func__, id); + return -1; + } + + if (bad_config) { + debug("%s: invalid config %d for periph_id %d", __func__, + config, id); + return -1; + } + return 0; +} diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c new file mode 100644 index 0000000..3c10a96 --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> + +#include <asm/io.h> + +#include <asm/arch/clock.h> +#include <asm/arch-tegra/xusb-padctl.h> + +#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> + +struct tegra_xusb_phy_ops { + int (*prepare)(struct tegra_xusb_phy *phy); + int (*enable)(struct tegra_xusb_phy *phy); + int (*disable)(struct tegra_xusb_phy *phy); + int (*unprepare)(struct tegra_xusb_phy *phy); +}; + +struct tegra_xusb_phy { + const struct tegra_xusb_phy_ops *ops; + + struct tegra_xusb_padctl *padctl; +}; + +struct tegra_xusb_padctl { + struct fdt_resource regs; + + unsigned int enable; + + struct tegra_xusb_phy phys[2]; +}; + +static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, + unsigned long offset) +{ + u32 value = readl(padctl->regs.start + offset); + debug("padctl: %08lx > %08x\n", offset, value); + return value; +} + +static inline void padctl_writel(struct tegra_xusb_padctl *padctl, + u32 value, unsigned long offset) +{ + debug("padctl: %08lx < %08x\n", offset, value); + writel(value, padctl->regs.start + offset); +} + +#define XUSB_PADCTL_ELPG_PROGRAM 0x024 +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) +#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29) + +static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) +{ + u32 value; + + if (padctl->enable++ > 0) + return 0; + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + return 0; +} + +static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) +{ + u32 value; + + if (padctl->enable == 0) { + error("unbalanced enable/disable"); + return 0; + } + + if (--padctl->enable > 0) + return 0; + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + udelay(100); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); + value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); + + return 0; +} + +static int phy_prepare(struct tegra_xusb_phy *phy) +{ + int err; + + err = tegra_xusb_padctl_enable(phy->padctl); + if (err < 0) + return err; + + reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0); + + return 0; +} + +static int phy_unprepare(struct tegra_xusb_phy *phy) +{ + reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); + + return tegra_xusb_padctl_disable(phy->padctl); +} + +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0) + +#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 +#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0) + +#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c +#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4) + +#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 +#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16) + +#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c +#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13) +#define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12) + +#define CLK_RST_XUSBIO_PLL_CFG0 0x51c +#define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) +#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13) +#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) +#define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) +#define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) + +static int pcie_phy_enable(struct tegra_xusb_phy *phy) +{ + struct tegra_xusb_padctl *padctl = phy->padctl; + unsigned long start; + u32 value; + + debug("> %s(phy=%p)\n", __func__, phy); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a); + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK; + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK; + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25); + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + udelay(1); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + + debug(" waiting for calibration\n"); + + start = get_timer(0); + + while (get_timer(start) < 250) { + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) + break; + } + + debug(" done\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + + debug(" waiting for calibration to stop\n"); + + start = get_timer(0); + + while (get_timer(start) < 250) { + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) + break; + } + + debug(" done\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + debug(" waiting for PLL to lock...\n"); + start = get_timer(0); + + while (get_timer(start) < 250) { + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) + break; + } + + debug(" done\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; + value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + + debug(" waiting for register calibration...\n"); + start = get_timer(0); + + while (get_timer(start) < 250) { + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) + break; + } + + debug(" done\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + + debug(" waiting for register calibration to stop...\n"); + start = get_timer(0); + + while (get_timer(start) < 250) { + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) + break; + } + + debug(" done\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + + value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); + value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; + value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; + value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; + value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; + writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); + + value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; + padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); + + udelay(1); + + value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); + value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; + writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); + + debug("< %s()\n", __func__); + return 0; +} + +static int pcie_phy_disable(struct tegra_xusb_phy *phy) +{ + return 0; +} + +static const struct tegra_xusb_phy_ops pcie_phy_ops = { + .prepare = phy_prepare, + .enable = pcie_phy_enable, + .disable = pcie_phy_disable, + .unprepare = phy_unprepare, +}; + +static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) { + .phys = { + [0] = { + .ops = &pcie_phy_ops, + }, + }, +}; + +static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, + const void *fdt, int node) +{ + int err; + + err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); + if (err < 0) { + error("registers not found"); + return err; + } + + debug("regs: %pa-%pa\n", &padctl->regs.start, + &padctl->regs.end); + + return 0; +} + +static int process_nodes(const void *fdt, int nodes[], unsigned int count) +{ + unsigned int i; + int err; + + debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes, + count); + + for (i = 0; i < count; i++) { + enum fdt_compat_id id; + + if (!fdtdec_get_is_enabled(fdt, nodes[i])) + continue; + + id = fdtdec_lookup(fdt, nodes[i]); + switch (id) { + case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL: + case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL: + break; + + default: + error("unsupported compatible: %s", + fdtdec_get_compatible(id)); + continue; + } + + err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]); + if (err < 0) { + error("failed to parse DT: %d", + err); + continue; + } + + /* deassert XUSB padctl reset */ + reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); + + /* only a single instance is supported */ + break; + } + + debug("< %s()\n", __func__); + return 0; +} + +struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) +{ + struct tegra_xusb_phy *phy = NULL; + + switch (type) { + case TEGRA_XUSB_PADCTL_PCIE: + phy = &padctl->phys[0]; + phy->padctl = padctl; + break; + } + + return phy; +} + +int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->prepare) + return phy->ops->prepare(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->enable) + return phy->ops->enable(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->disable) + return phy->ops->disable(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) +{ + if (phy && phy->ops && phy->ops->unprepare) + return phy->ops->unprepare(phy); + + return phy ? -ENOSYS : -EINVAL; +} + +void tegra_xusb_padctl_init(const void *fdt) +{ + int count, nodes[1]; + + debug("> %s(fdt=%p)\n", __func__, fdt); + + count = fdtdec_find_aliases_for_id(fdt, "padctl", + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, + nodes, ARRAY_SIZE(nodes)); + if (process_nodes(fdt, nodes, count)) + return; + + count = fdtdec_find_aliases_for_id(fdt, "padctl", + COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, + nodes, ARRAY_SIZE(nodes)); + if (process_nodes(fdt, nodes, count)) + return; + + debug("< %s()\n", __func__); +} diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3b3f446..18451d3 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -22,9 +22,11 @@ config MPC8260 config MPC83xx bool "MPC83xx" + select CREATE_ARCH_SYMLINK config MPC85xx bool "MPC85xx" + select CREATE_ARCH_SYMLINK config MPC86xx bool "MPC86xx" @@ -34,6 +36,7 @@ config 8xx config 4xx bool "PPC4xx" + select CREATE_ARCH_SYMLINK endchoice diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cbbaa4f..e8968a7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -369,4 +369,14 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). +config PCIE_ECAM_SIZE + hex + default 0x10000000 + help + This is the size of memory-mapped address of PCI configuration space, + which is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, + so a default 0x10000000 size covers all of the 256 buses which is the + maximum number of PCI buses as defined by the PCI specification. + endmenu diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index af927b9..b9134cf 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -363,13 +363,26 @@ int x86_cpu_init_f(void) mtrr_cap = native_read_msr(MTRR_CAP_MSR); if (mtrr_cap & MTRR_CAP_FIX) { /* Mark the VGA RAM area as uncacheable */ - native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0); - - /* Mark the PCI ROM area as uncacheable */ - native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0); - native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0); + native_write_msr(MTRR_FIX_16K_A0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* + * Mark the PCI ROM area as cacheable to improve ROM + * execution performance. + */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_C8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); /* Enable the fixed range MTRRs */ msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); @@ -683,6 +696,15 @@ __weak int x86_init_cpus(void) #ifdef CONFIG_SMP debug("Init additional CPUs\n"); x86_mp_init(); +#else + struct udevice *dev; + + /* + * This causes the cpu-x86 driver to be probed. + * We don't check return value here as we want to allow boards + * which have not been converted to use cpu uclass driver to boot. + */ + uclass_first_device(UCLASS_CPU, &dev); #endif return 0; diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index c777d36..853c82f 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -32,14 +32,76 @@ DECLARE_GLOBAL_DATA_PTR; "pushl $"#x"\n" \ "jmp irq_common_entry\n" +static char *exceptions[] = { + "Divide Error", + "Debug", + "NMI Interrupt", + "Breakpoint", + "Overflow", + "BOUND Range Exceeded", + "Invalid Opcode (Undefined Opcode)", + "Device Not Avaiable (No Math Coprocessor)", + "Double Fault", + "Coprocessor Segment Overrun", + "Invalid TSS", + "Segment Not Present", + "Stack Segment Fault", + "Gerneral Protection", + "Page Fault", + "Reserved", + "x87 FPU Floating-Point Error", + "Alignment Check", + "Machine Check", + "SIMD Floating-Point Exception", + "Virtualization Exception", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved" +}; + static void dump_regs(struct irq_regs *regs) { + unsigned long cs, eip, eflags; unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; unsigned long sp; + /* + * Some exceptions cause an error code to be saved on the current stack + * after the EIP value. We should extract CS/EIP/EFLAGS from different + * position on the stack based on the exception number. + */ + switch (regs->irq_id) { + case EXC_DF: + case EXC_TS: + case EXC_NP: + case EXC_SS: + case EXC_GP: + case EXC_PF: + case EXC_AC: + cs = regs->context.ctx2.xcs; + eip = regs->context.ctx2.eip; + eflags = regs->context.ctx2.eflags; + /* We should fix up the ESP due to error code */ + regs->esp += 4; + break; + default: + cs = regs->context.ctx1.xcs; + eip = regs->context.ctx1.eip; + eflags = regs->context.ctx1.eflags; + break; + } + printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n", - (u16)regs->xcs, regs->eip, regs->eflags); + (u16)cs, eip, eflags); printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", regs->eax, regs->ebx, regs->ecx, regs->edx); @@ -85,6 +147,13 @@ static void dump_regs(struct irq_regs *regs) } } +static void do_exception(struct irq_regs *regs) +{ + printf("%s\n", exceptions[regs->irq_id]); + dump_regs(regs); + hang(); +} + struct idt_entry { u16 base_low; u16 selector; @@ -201,111 +270,10 @@ void irq_llsr(struct irq_regs *regs) * Order Number: 253665-029US, November 2008 * Table 6-1. Exceptions and Interrupts */ - switch (regs->irq_id) { - case 0x00: - printf("Divide Error (Division by zero)\n"); - dump_regs(regs); - hang(); - break; - case 0x01: - printf("Debug Interrupt (Single step)\n"); - dump_regs(regs); - break; - case 0x02: - printf("NMI Interrupt\n"); - dump_regs(regs); - break; - case 0x03: - printf("Breakpoint\n"); - dump_regs(regs); - break; - case 0x04: - printf("Overflow\n"); - dump_regs(regs); - hang(); - break; - case 0x05: - printf("BOUND Range Exceeded\n"); - dump_regs(regs); - hang(); - break; - case 0x06: - printf("Invalid Opcode (UnDefined Opcode)\n"); - dump_regs(regs); - hang(); - break; - case 0x07: - printf("Device Not Available (No Math Coprocessor)\n"); - dump_regs(regs); - hang(); - break; - case 0x08: - printf("Double fault\n"); - dump_regs(regs); - hang(); - break; - case 0x09: - printf("Co-processor segment overrun\n"); - dump_regs(regs); - hang(); - break; - case 0x0a: - printf("Invalid TSS\n"); - dump_regs(regs); - break; - case 0x0b: - printf("Segment Not Present\n"); - dump_regs(regs); - hang(); - break; - case 0x0c: - printf("Stack Segment Fault\n"); - dump_regs(regs); - hang(); - break; - case 0x0d: - printf("General Protection\n"); - dump_regs(regs); - break; - case 0x0e: - printf("Page fault\n"); - dump_regs(regs); - hang(); - break; - case 0x0f: - printf("Floating-Point Error (Math Fault)\n"); - dump_regs(regs); - break; - case 0x10: - printf("Alignment check\n"); - dump_regs(regs); - break; - case 0x11: - printf("Machine Check\n"); - dump_regs(regs); - break; - case 0x12: - printf("SIMD Floating-Point Exception\n"); - dump_regs(regs); - break; - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - case 0x18: - case 0x19: - case 0x1a: - case 0x1b: - case 0x1c: - case 0x1d: - case 0x1e: - case 0x1f: - printf("Reserved Exception\n"); - dump_regs(regs); - break; - - default: + if (regs->irq_id < 32) { + /* Architecture defined exception */ + do_exception(regs); + } else { /* Hardware or User IRQ */ do_irq(regs->irq_id); } diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index ea169b0..89d4a5e 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -16,7 +16,6 @@ #include <asm/pci.h> #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> -#include <linux/kconfig.h> struct gt_powermeter { u16 reg; diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index bc1a0f0..3efd3e8 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -252,7 +252,6 @@ static void pch_rtc_init(pci_dev_t dev) /* TODO: Handle power failure */ if (rtc_failed) printf("RTC power failed\n"); - rtc_init(); } /* CougarPoint PCH Power Management init */ diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index af907c5..7f3b13d 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -128,6 +128,14 @@ static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry) static int read_seed_from_cmos(struct pei_data *pei_data) { u16 c1, c2, checksum, seed_checksum; + struct udevice *dev; + int rcode = 0; + + rcode = uclass_get_device(UCLASS_RTC, 0, &dev); + if (rcode) { + debug("Cannot find RTC: err=%d\n", rcode); + return -ENODEV; + } /* * Read scrambler seeds from CMOS RAM. We don't want to store them in @@ -135,11 +143,11 @@ static int read_seed_from_cmos(struct pei_data *pei_data) * the flash too much. So we store these in CMOS and the large MRC * data in SPI flash. */ - pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED); + rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed); debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3); + rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3); debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); @@ -150,8 +158,8 @@ static int read_seed_from_cmos(struct pei_data *pei_data) sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK); - seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; + seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; if (checksum != seed_checksum) { debug("%s: invalid seed checksum\n", __func__); @@ -223,13 +231,21 @@ static int build_mrc_data(struct mrc_data_container **datap) static int write_seeds_to_cmos(struct pei_data *pei_data) { u16 c1, c2, checksum; + struct udevice *dev; + int rcode = 0; + + rcode = uclass_get_device(UCLASS_RTC, 0, &dev); + if (rcode) { + debug("Cannot find RTC: err=%d\n", rcode); + return -ENODEV; + } /* Save the MRC seed values to CMOS */ - rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); + rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); @@ -240,8 +256,8 @@ static int write_seeds_to_cmos(struct pei_data *pei_data) sizeof(u32)); checksum = add_ip_checksums(sizeof(u32), c1, c2); - rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); - rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); + rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff); + rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff); return 0; } diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index c209f15..f8da080 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -152,23 +152,32 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, return 0; } -void pci_assign_irqs(int bus, int device, int func, u8 irq[4]) +void pci_assign_irqs(int bus, int device, u8 irq[4]) { pci_dev_t bdf; + int func; + u16 vendor; u8 pin, line; - bdf = PCI_BDF(bus, device, func); + for (func = 0; func < 8; func++) { + bdf = PCI_BDF(bus, device, func); + vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID); + if (vendor == 0xffff || vendor == 0x0000) + continue; - pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); + pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN); - /* PCI spec says all values except 1..4 are reserved */ - if ((pin < 1) || (pin > 4)) - return; + /* PCI spec says all values except 1..4 are reserved */ + if ((pin < 1) || (pin > 4)) + continue; - line = irq[pin - 1]; + line = irq[pin - 1]; + if (!line) + continue; - debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", - line, bus, device, func, 'A' + pin - 1); + debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n", + line, bus, device, func, 'A' + pin - 1); - x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line); + } } diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 1a9140b..2e94456 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +static bool i440fx; + void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; @@ -50,7 +52,7 @@ void board_pci_setup_hose(struct pci_controller *hose) int board_pci_post_scan(struct pci_controller *hose) { int ret = 0; - u16 device; + u16 device, xbcs; int pam, i; pci_dev_t vga; ulong start; @@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose) * PCI device ID. */ device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); - pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; + i440fx = (device == PCI_DEVICE_ID_INTEL_82441); + pam = i440fx ? I440FX_PAM : Q35_PAM; /* * Initialize Programmable Attribute Map (PAM) Registers @@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose) for (i = 0; i < PAM_NUM; i++) x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); - if (device == PCI_DEVICE_ID_INTEL_82441) { + if (i440fx) { /* * Enable legacy IDE I/O ports decode * @@ -82,6 +85,15 @@ int board_pci_post_scan(struct pci_controller *hose) */ x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + + /* Enable I/O APIC */ + xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + xbcs |= APIC_EN; + x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + } else { + /* Configure PCIe ECAM base address */ + x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); } /* @@ -92,10 +104,35 @@ int board_pci_post_scan(struct pci_controller *hose) * board, it shows as device 2, while for Q35 and ICH9 chipset board, * it shows as device 1. */ - vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA; + vga = i440fx ? I440FX_VGA : Q35_VGA; start = get_timer(0); ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); debug("BIOS ran in %lums\n", get_timer(start)); return ret; } + +#ifdef CONFIG_GENERATE_MP_TABLE +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + u8 irq; + + if (i440fx) { + /* + * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not + * connected to I/O APIC INTPIN#16-19. Instead they are routed + * to an irq number controled by the PIRQ routing register. + */ + irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE); + } else { + /* + * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. + * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. + */ + irq = pirq < 8 ? pirq + 16 : pirq + 12; + } + + return irq; +} +#endif diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index d8761fd..660f967 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -6,4 +6,3 @@ obj-y += fsp_configs.o obj-y += tnc.o topcliff.o -obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index d27b2d9..de50893 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -25,7 +25,6 @@ static void unprotect_spi_flash(void) int arch_cpu_init(void) { - struct pci_controller *hose; int ret; post_code(POST_CPU_INIT); @@ -37,10 +36,6 @@ int arch_cpu_init(void) if (ret) return ret; - ret = pci_early_init_hose(&hose); - if (ret) - return ret; - unprotect_spi_flash(); return 0; diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c deleted file mode 100644 index 6c291f9..0000000 --- a/arch/x86/cpu/queensbay/tnc_pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/pci.h> -#include <asm/fsp/fsp_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 7c7034c..ad390bf 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 4eccefd..84eae3a 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 60da1f5..3af9cc3 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -90,8 +90,12 @@ pci { #address-cells = <3>; #size-cells = <2>; - compatible = "intel,pci"; + compatible = "pci-x86"; device_type = "pci"; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; pcie@17,0 { #address-cells = <3>; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 2ba081e..d77ff8a 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-router/intel-irq.h> /include/ "skeleton.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Galileo"; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 0e59b18..9527233 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 557428a..c26c71b 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "QEMU x86 (I440FX)"; @@ -23,6 +24,18 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index c259f2a..2e785fa 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -20,6 +20,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "rtc.dtsi" / { model = "QEMU x86 (Q35)"; @@ -34,6 +35,18 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi index 93dacd7..1797e04 100644 --- a/arch/x86/dts/rtc.dtsi +++ b/arch/x86/dts/rtc.dtsi @@ -1,6 +1,7 @@ / { rtc { compatible = "motorola,mc146818"; + u-boot,dm-pre-reloc; reg = <0x70 2>; }; }; diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index 5cbffff..b67d342 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -13,10 +13,18 @@ #define PAM_NUM 7 #define PAM_RW 0x33 +/* X-Bus Chip Select Register */ +#define XBCS 0x4e +#define APIC_EN (1 << 8) + /* IDE Timing Register */ #define IDE0_TIM 0x40 #define IDE1_TIM 0x42 -#define IDE_DECODE_EN 0x8000 +#define IDE_DECODE_EN (1 << 15) + +/* PCIe ECAM Base Address Register */ +#define PCIEX_BAR 0x60 +#define BAR_EN (1 << 0) /* I/O Ports */ #define CMOS_ADDR_PORT 0x70 diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index 00cbe07..fcd766b 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -13,6 +13,30 @@ #include <asm/types.h> +/* Architecture defined exceptions */ +enum x86_exception { + EXC_DE = 0, + EXC_DB, + EXC_NMI, + EXC_BP, + EXC_OF, + EXC_BR, + EXC_UD, + EXC_NM, + EXC_DF, + EXC_CSO, + EXC_TS, + EXC_NP, + EXC_SS, + EXC_GP, + EXC_PF, + EXC_MF = 16, + EXC_AC, + EXC_MC, + EXC_XM, + EXC_VE +}; + /* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index efa9231..ad8eba9 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -432,6 +432,23 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid, u32 mptable_finalize(struct mp_config_table *mc); /** + * mp_determine_pci_dstirq() - Determine PCI device's int pin on the I/O APIC + * + * This determines a PCI device's interrupt pin number on the I/O APIC. + * + * This can be implemented by platform codes to handle specifal cases, which + * do not conform to the normal chipset/board design where PIRQ[A-H] are mapped + * directly to I/O APIC INTPIN#16-23. + * + * @bus: bus number of the pci device + * @dev: device number of the pci device + * @func: function number of the pci device + * @pirq: PIRQ number the PCI device's interrupt pin is routed to + * @return: interrupt pin number on the I/O APIC + */ +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); + +/** * write_mp_table() - Write MP table * * This writes MP table at a given address. diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 70762ee..f9b30f6 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -55,6 +55,8 @@ #define MTRR_FIX_4K_F0000_MSR 0x26e #define MTRR_FIX_4K_F8000_MSR 0x26f +#define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) + #if !defined(__ASSEMBLER__) /** diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 56eaa25..f7e968e 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -72,11 +72,10 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, * * @bus: PCI bus number * @device: PCI device number - * @func: PCI function number * @irq: An array of IRQ numbers that are assigned to INTA through * INTD of this PCI device. */ -void pci_assign_irqs(int bus, int device, int func, u8 irq[4]); +void pci_assign_irqs(int bus, int device, u8 irq[4]); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index a727dbf..3849bc0 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -63,9 +63,19 @@ struct irq_regs { /* Pushed by vector handler (irq_<num>) */ long irq_id; /* Pushed by cpu in response to interrupt */ - long eip; - long xcs; - long eflags; + union { + struct { + long eip; + long xcs; + long eflags; + } ctx1; + struct { + long err; + long eip; + long xcs; + long eflags; + } ctx2; + } context; } __attribute__ ((packed)); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 4c0a7c8..28552fa 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -77,5 +77,11 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) num_entries++; } + /* Mark PCIe ECAM address range as reserved */ + entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; + entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; + return num_entries; } diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index f16fbcb..f3ad116 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -21,6 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; +static bool isa_irq_occupied[16]; + struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf) { u32 mc; @@ -243,10 +245,18 @@ static void mptable_add_isa_interrupts(struct mp_config_table *mc, int bus_isa, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0, apicid, 2); - for (i = 3; i < 16; i++) + for (i = 3; i < 16; i++) { + /* + * Do not write ISA interrupt entry if it is already occupied + * by the platform devices. + */ + if (isa_irq_occupied[i]) + continue; + mp_write_intsrc(mc, MP_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, i, apicid, i); + } } /* @@ -269,6 +279,13 @@ static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base, return (i == entry_num) ? false : true; } +/* TODO: move this to driver model */ +__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */ + return pirq + 16; +} + static int mptable_add_intsrc(struct mp_config_table *mc, int bus_isa, int apicid) { @@ -280,10 +297,6 @@ static int mptable_add_intsrc(struct mp_config_table *mc, const u32 *cell; int i; - /* Legacy Interrupts */ - debug("Writing ISA IRQs\n"); - mptable_add_isa_interrupts(mc, bus_isa, apicid, 0); - /* Get I/O interrupt information from device tree */ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER); if (node < 0) { @@ -304,28 +317,41 @@ static int mptable_add_intsrc(struct mp_config_table *mc, for (i = 0; i < count; i++) { struct pirq_routing pr; + int bus, dev, func; + int dstirq; pr.bdf = fdt_addr_to_cpu(cell[0]); pr.pin = fdt_addr_to_cpu(cell[1]); pr.pirq = fdt_addr_to_cpu(cell[2]); + bus = PCI_BUS(pr.bdf); + dev = PCI_DEV(pr.bdf); + func = PCI_FUNC(pr.bdf); if (check_dup_entry(intsrc_base, intsrc_entries, - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin)) { + bus, dev, pr.pin)) { debug("found entry for bus %d device %d INT%c, skipping\n", - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), - 'A' + pr.pin - 1); + bus, dev, 'A' + pr.pin - 1); cell += sizeof(struct pirq_routing) / sizeof(u32); continue; } - /* PIRQ[A-H] are always connected to I/O APIC INTPIN#16-23 */ - mp_write_pci_intsrc(mc, MP_INT, PCI_BUS(pr.bdf), - PCI_DEV(pr.bdf), pr.pin, apicid, - pr.pirq + 16); + dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); + /* + * For PIRQ which is connected to I/O APIC interrupt pin#0-15, + * mark it as occupied so that we can skip it later. + */ + if (dstirq < 16) + isa_irq_occupied[dstirq] = true; + mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin, + apicid, dstirq); intsrc_entries++; cell += sizeof(struct pirq_routing) / sizeof(u32); } + /* Legacy Interrupts */ + debug("Writing ISA IRQs\n"); + mptable_add_isa_interrupts(mc, bus_isa, apicid, 0); + return 0; } diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index 7a34dcf..ba41169 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -98,8 +98,7 @@ void pirq_route_irqs(struct irq_info *irq, int num) } /* Bus, device, slots IRQs for {A,B,C,D} */ - pci_assign_irqs(irq->bus, irq->devfn >> 3, irq->devfn & 7, - irq_slot); + pci_assign_irqs(irq->bus, irq->devfn >> 3, irq_slot); irq++; } diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 144471c..a1ec57e 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -61,8 +61,11 @@ __weak unsigned install_e820_map(unsigned max_entries, entries[2].addr = ISA_END_ADDRESS; entries[2].size = gd->ram_size - ISA_END_ADDRESS; entries[2].type = E820_RAM; + entries[3].addr = CONFIG_PCIE_ECAM_BASE; + entries[3].size = CONFIG_PCIE_ECAM_SIZE; + entries[3].type = E820_RESERVED; - return 3; + return 4; } static void build_command_line(char *command_line, int auto_boot) diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index fad0551..6d3b18a 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -82,7 +82,7 @@ static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval) #ifdef CONFIG_SYS_MMC_ENV_PART uint mmc_get_env_part(struct mmc *mmc) { - u32 bootmode = gd->arch.omap_boot_params.omap_bootmode; + u32 bootmode = gd->arch.omap_boot_mode; uint bootpart = CONFIG_SYS_MMC_ENV_PART; /* diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index 9c5fbaa..9c838ba 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -234,8 +234,8 @@ static const struct pmux_pingrp_config nyan_big_pingrps[] = { PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), @@ -257,7 +257,7 @@ static const struct pmux_pingrp_config nyan_big_pingrps[] = { PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig new file mode 100644 index 0000000..7bc4874 --- /dev/null +++ b/board/nvidia/p2571/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2571 + +config SYS_BOARD + default "p2571" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2571" + +endif diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS new file mode 100644 index 0000000..c165135 --- /dev/null +++ b/board/nvidia/p2571/MAINTAINERS @@ -0,0 +1,6 @@ +P2571 BOARD +M: Tom Warren <twarren@nvidia.com> +S: Maintained +F: board/nvidia/p2571/ +F: include/configs/p2571.h +F: configs/p2571_defconfig diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile new file mode 100644 index 0000000..223062e --- /dev/null +++ b/board/nvidia/p2571/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += max77620_init.o +obj-y += p2571.o diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c new file mode 100644 index 0000000..ed8d4dc --- /dev/null +++ b/board/nvidia/p2571/max77620_init.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include "max77620_init.h" + +/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */ + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} + +void pmic_enable_cpu_vdd(void) +{ + uint reg; + debug("%s entry\n", __func__); + + /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ + debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__); + /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */ + reg = 0x0900 | MAX77620_GPIO5_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */ + debug("%s: Setting GPIO1 to enable HDMI\n", __func__); + reg = 0x0900 | MAX77620_GPIO1_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ + reg = 0x1C00 | MAX77620_AME_GPIO; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */ + debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n", + __func__); + /* bit1=0, SD1 remote sense disabled */ + reg = 0x0400 | MAX77620_CNFG2SD_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* SD1 output = 1.125V */ + reg = 0x2A00 | MAX77620_SD1_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xF200 | MAX77620_CNFG1_L2_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__); + /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xCA00 | MAX77620_CNFG1_L1_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); +} diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h new file mode 100644 index 0000000..9d5cce7 --- /dev/null +++ b/board/nvidia/p2571/max77620_init.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MAX77620_INIT_H_ +#define _MAX77620_INIT_H_ + +/* MAX77620-PMIC-specific early init regs */ + +#define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */ + +#define MAX77620_SD0_REG 0x16 +#define MAX77620_SD1_REG 0x17 +#define MAX77620_SD2_REG 0x18 +#define MAX77620_SD3_REG 0x19 +#define MAX77620_CNFG2SD_REG 0x22 + +#define MAX77620_CNFG1_L0_REG 0x23 +#define MAX77620_CNFG2_L0_REG 0x24 +#define MAX77620_CNFG1_L1_REG 0x25 +#define MAX77620_CNFG2_L1_REG 0x26 +#define MAX77620_CNFG1_L2_REG 0x27 +#define MAX77620_CNFG2_L2_REG 0x28 +#define MAX77620_CNFG1_L3_REG 0x29 +#define MAX77620_CNFG2_L3_REG 0x2A +#define MAX77620_CNFG1_L4_REG 0x2B +#define MAX77620_CNFG2_L4_REG 0x2C +#define MAX77620_CNFG1_L5_REG 0x2D +#define MAX77620_CNFG2_L5_REG 0x2E +#define MAX77620_CNFG1_L6_REG 0x2F +#define MAX77620_CNFG2_L6_REG 0x30 +#define MAX77620_CNFG1_L7_REG 0x31 +#define MAX77620_CNFG2_L7_REG 0x32 +#define MAX77620_CNFG1_L8_REG 0x33 +#define MAX77620_CNFG2_L8_REG 0x34 +#define MAX77620_CNFG3_LDO_REG 0x35 + +#define MAX77620_GPIO0_REG 0x36 +#define MAX77620_GPIO1_REG 0x37 +#define MAX77620_GPIO2_REG 0x38 +#define MAX77620_GPIO3_REG 0x39 +#define MAX77620_GPIO4_REG 0x3A +#define MAX77620_GPIO5_REG 0x3B +#define MAX77620_GPIO6_REG 0x3C +#define MAX77620_GPIO7_REG 0x3D +#define MAX77620_GPIO_PUE_GPIO 0x3E +#define MAX77620_GPIO_PDE_GPIO 0x3F + +#define MAX77620_AME_GPIO 0x40 +#define MAX77620_REG_ONOFF_CFG1 0x41 +#define MAX77620_REG_ONOFF_CFG2 0x42 + +#define MAX77620_CID0_REG 0x58 +#define MAX77620_CID1_REG 0x59 +#define MAX77620_CID2_REG 0x5A +#define MAX77620_CID3_REG 0x5B +#define MAX77620_CID4_REG 0x5C +#define MAX77620_CID5_REG 0x5D + +#define I2C_SEND_2_BYTES 0x0A02 + +void pmic_enable_cpu_vdd(void); + +#endif /* _MAX77620_INIT_H_ */ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c new file mode 100644 index 0000000..fc710c1 --- /dev/null +++ b/board/nvidia/p2571/p2571.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "pinmux-config-p2571.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(p2571_gpio_inits, + ARRAY_SIZE(p2571_gpio_inits)); + + pinmux_config_pingrp_table(p2571_pingrps, + ARRAY_SIZE(p2571_pingrps)); + + pinmux_config_drvgrp_table(p2571_drvgrps, + ARRAY_SIZE(p2571_drvgrps)); +} diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h new file mode 100644 index 0000000..ac414f0 --- /dev/null +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_P2571_H_ +#define _PINMUX_CONFIG_P2571_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config p2571_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(A5, IN), + GPIO_INIT(D4, IN), + GPIO_INIT(E4, OUT0), + GPIO_INIT(G0, IN), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V6, OUT1), + GPIO_INIT(X4, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC3, IN), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config p2571_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config p2571_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_P2571_H */ diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 2dd5d93..f418186 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -285,3 +285,22 @@ int board_init(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char serialno[25]; + uint32_t u_id_low, u_id_mid, u_id_high; + + if (!getenv("serial#")) { + u_id_low = readl(&STM32_U_ID->u_id_low); + u_id_mid = readl(&STM32_U_ID->u_id_mid); + u_id_high = readl(&STM32_U_ID->u_id_high); + sprintf(serialno, "%08x%08x%08x", + u_id_high, u_id_mid, u_id_low); + setenv("serial#", serialno); + } + + return 0; +} +#endif diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index 149bb51..7d4409b 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -1,6 +1,5 @@ #include <common.h> #include <asm/arch/dram.h> -#include <linux/kconfig.h> static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index 596a206..e3fa243 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -2,7 +2,6 @@ #include <common.h> #include <asm/arch/dram.h> -#include <linux/kconfig.h> static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index 9ee90a4..6586fab 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -47,7 +47,6 @@ Board configuration files: include/configs/k2hk_evm.h include/configs/k2e_evm.h include/configs/k2l_evm.h -include/configs/k2l_evm.h As u-boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig @@ -71,7 +70,7 @@ Don't forget to add ARCH=arm and CROSS_COMPILE. To build u-boot.bin >make k2hk_evm_defconfig - >make u-boot-spi.gph + >make u-boot.bin To build u-boot-spi.gph >make k2hk_evm_defconfig diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 8892a28..0cefb34 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -48,7 +48,7 @@ int dram_init(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 20522fb..fd5d6fe 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -25,7 +25,7 @@ ifeq ($(init-objs),) ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),) init-objs := ps7_init_gpl.o $(if $(CONFIG_SPL_BUILD),\ -$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custome_hw_platform/)) +$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/)) endif endif diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig deleted file mode 100644 index b07932e..0000000 --- a/board/xilinx/zynqmp/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_XILINX_ZYNQMP - -config SYS_BOARD - default "zynqmp" - -config SYS_VENDOR - default "xilinx" - -config SYS_SOC - default "zynqmp" - -config SYS_CONFIG_NAME - default "xilinx_zynqmp" - -endif diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index da33340..20ca652 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,6 +1,7 @@ -XILINX_ZYNQMP BOARD +XILINX_ZYNQMP_EP BOARD M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp.h -F: configs/xilinx_zynqmp_defconfig +F: include/configs/xilinx_zynqmp_ep.h +F: configs/xilinx_zynqmp_ep_defconfig diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f5ff64d..0c9a814 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -7,6 +7,8 @@ #include <common.h> #include <netdev.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -15,6 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { + printf("EL Level:\tEL%d\n", current_el()); + return 0; } @@ -51,6 +55,39 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) +{ + ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); + scsi_scan(1); +} +#endif + +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) +# if defined(CONFIG_ZYNQ_GEM0) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, + CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM1) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, + CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM2) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, + CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM3) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, + CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); +# endif +#endif + return ret; +} + #ifdef CONFIG_CMD_MMC int board_mmc_init(bd_t *bd) { diff --git a/common/board_info.c b/common/board_info.c index 42d0641..4e5a1f7 100644 --- a/common/board_info.c +++ b/common/board_info.c @@ -14,8 +14,7 @@ int __weak checkboard(void) /* * If the root node of the DTB has a "model" property, show it. - * If CONFIG_OF_CONTROL is disabled or the "model" property is missing, - * fall back to checkboard(). + * Then call checkboard(). */ int show_board_info(void) { @@ -25,10 +24,8 @@ int show_board_info(void) model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (model) { + if (model) printf("Model: %s\n", model); - return 0; - } #endif return checkboard(); diff --git a/common/cmd_mp.c b/common/cmd_mp.c index 328b338..a80c642 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -7,11 +7,32 @@ #include <common.h> #include <command.h> +static int cpu_status_all(void) +{ + unsigned long cpuid; + + for (cpuid = 0; ; cpuid++) { + if (!is_core_valid(cpuid)) { + if (cpuid == 0) { + printf("Core num: %lu is not valid\n", cpuid); + return 1; + } + break; + } + cpu_status(cpuid); + } + + return 0; +} + static int cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long cpuid; + if (argc == 2 && strncmp(argv[1], "status", 6) == 0) + return cpu_status_all(); + if (argc < 3) return CMD_RET_USAGE; @@ -48,6 +69,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_LONGHELP static char cpu_help_text[] = "<num> reset - Reset cpu <num>\n" + "cpu status - Status of all cpus\n" "cpu <num> status - Status of cpu <num>\n" "cpu <num> disable - Disable cpu <num>\n" "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]" diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index abf0941..080b376 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -793,8 +793,12 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) /* Try bootm for legacy and FIT format image */ if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID) do_bootm(cmdtp, 0, bootm_argc, bootm_argv); -#ifdef CONFIG_CMD_BOOTZ - /* Try booting a zImage */ +#ifdef CONFIG_CMD_BOOTI + /* Try booting an AArch64 Linux kernel image */ + else + do_booti(cmdtp, 0, bootm_argc, bootm_argv); +#elif defined(CONFIG_CMD_BOOTZ) + /* Try booting a Image */ else do_bootz(cmdtp, 0, bootm_argc, bootm_argv); #endif diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 4589b30..c72d29e 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_EVM=y CONFIG_SPL=y +CONFIG_FIT=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 9931d65..e394dab 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index b3a5f28..340510f 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 17e6a72..aa1232d 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y +CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 1ced47e..3f80483 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -15,5 +15,6 @@ CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 29dd44b..e98f5eb 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -21,5 +21,6 @@ CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig new file mode 100644 index 0000000..8494bb5 --- /dev/null +++ b/configs/p2571_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_P2571=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 5639cc5..4b18d51 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -1,6 +1,8 @@ CONFIG_X86=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -9,9 +11,11 @@ CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/xilinx_zynqmp_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 1c64eea..fda44ea 100644 --- a/configs/xilinx_zynqmp_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y -CONFIG_TARGET_XILINX_ZYNQMP=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set @@ -15,3 +15,4 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp" # CONFIG_CMD_NFS is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y +CONFIG_SYS_TEXT_BASE=0x8000000 diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig new file mode 100644 index 0000000..8f9221d --- /dev/null +++ b/configs/zynq_zc770_xm011_defconfig @@ -0,0 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt index f397a36..cb29457 100644 --- a/doc/device-tree-bindings/spi/spi-zynq.txt +++ b/doc/device-tree-bindings/spi/spi-zynq.txt @@ -1,29 +1,32 @@ -Zynq SPI controller Device Tree Bindings ----------------------------------------- +Cadence SPI controller Device Tree Bindings +------------------------------------------- Required properties: -- compatible : Should be "xlnx,spi-zynq". +- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6". - reg : Physical base address and size of SPI registers map. -- status : Status will be disabled in dtsi and enabled in required dts. -- interrupt-parent : Must be core interrupt controller. - interrupts : Property with a value describing the interrupt number. -- clocks : Clock phandles (see clock bindings for details). +- interrupt-parent : Must be core interrupt controller - clock-names : List of input clock names - "ref_clk", "pclk" (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). - spi-max-frequency : Maximum SPI clocking speed of device in Hz +Optional properties: +- num-cs : Number of chip selects used. + If a decoder is used, this will be the number of + chip selects after the decoder. +- is-decoded-cs : Flag to indicate whether decoder is used or not. + Example: - spi@e0006000 { - compatible = "xlnx,zynq-spi"; - reg = <0xe0006000 0x1000>; - status = "disabled"; - interrupt-parent = <&intc>; - interrupts = <0 26 4>; - clocks = <&clkc 25>, <&clkc 34>; + spi@e0007000 { + compatible = "xlnx,zynq-spi-r1p6"; clock-names = "ref_clk", "pclk"; - spi-max-frequency = <166666700>; - #address-cells = <1>; - #size-cells = <0>; + clocks = <&clkc 26>, <&clkc 35>; + interrupt-parent = <&intc>; + interrupts = <0 49 4>; + num-cs = <4>; + is-decoded-cs = <0>; + reg = <0xe0007000 0x1000>; } ; diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 0560afa..675162d 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -198,9 +198,9 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret; - debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x offset: 0x%llx bufoffset: 0x%x\n", + debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x offset: 0x%llx bufoffset: 0x%lx\n", __func__, dfu->name, buf, size, blk_seq_num, dfu->offset, - dfu->i_buf - dfu->i_buf_start); + (unsigned long)(dfu->i_buf - dfu->i_buf_start)); if (!dfu->inited) { /* initial state */ diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index fd865e1..2a780f7 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -156,7 +156,7 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, dfu->data.mmc.dev, dfu->data.mmc.part); if (op != DFU_OP_SIZE) - sprintf(cmd_buf + strlen(cmd_buf), " 0x%x", (unsigned int)buf); + sprintf(cmd_buf + strlen(cmd_buf), " %p", buf); sprintf(cmd_buf + strlen(cmd_buf), " %s", dfu->name); diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index fc95646..a428978 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -235,7 +235,7 @@ static int send_recv_packets(struct i2c_bus *i2c_bus, if ((words == 1) && last_bytes) { local = 0; memcpy(&local, dptr, last_bytes); - } else if ((unsigned)dptr & 3) { + } else if ((unsigned long)dptr & 3) { memcpy(&local, dptr, sizeof(u32)); } else { local = *wptr; @@ -258,7 +258,7 @@ static int send_recv_packets(struct i2c_bus *i2c_bus, local = readl(&control->rx_fifo); if ((words == 1) && last_bytes) memcpy(dptr, (char *)&local, last_bytes); - else if ((unsigned)dptr & 3) + else if ((unsigned long)dptr & 3) memcpy(dptr, &local, sizeof(u32)); else *wptr = local; diff --git a/drivers/misc/pca9551_led.c b/drivers/misc/pca9551_led.c index 79b1e20..d4034f6 100644 --- a/drivers/misc/pca9551_led.c +++ b/drivers/misc/pca9551_led.c @@ -32,7 +32,10 @@ struct pca9551_blink_rate { u8 pwm; /* Pulse width modulation, see PCA9551_7.pdf p. 6 */ }; -static int freq0, freq1; +static int freq_last = -1; +static int mask_last = -1; +static int idx_last = -1; +static int mode_last; static int pca9551_led_get_state(int led, int *state) { @@ -135,21 +138,30 @@ void __led_blink(led_id_t mask, int freq) { struct pca9551_blink_rate rate; int mode; - int blink; + int idx; - if ((freq0 == 0) || (freq == freq0)) { - blink = 0; - mode = PCA9551_LED_STATE_BLINK0; - freq0 = freq; + if ((freq == freq_last) || (mask == mask_last)) { + idx = idx_last; + mode = mode_last; } else { - blink = 1; - mode = PCA9551_LED_STATE_BLINK1; - freq1 = freq; + /* Toggle blink index */ + if (idx_last == 0) { + idx = 1; + mode = PCA9551_LED_STATE_BLINK1; + } else { + idx = 0; + mode = PCA9551_LED_STATE_BLINK0; + } + + idx_last = idx; + mode_last = mode; } + freq_last = freq; + mask_last = mask; rate.psc = ((freq * 38) / 1000) - 1; rate.pwm = 128; /* 50% duty cycle */ - pca9551_led_set_blink_rate(blink, rate); + pca9551_led_set_blink_rate(idx, rate); pca9551_led_set_state(mask, mode); } diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index d555692..6f8b4d0 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -2,7 +2,7 @@ * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang <mk7.kang@samsung.com> * Jaehoon Chung <jh80.chung@samsung.com> - * Portions Copyright 2011-2013 NVIDIA Corporation + * Portions Copyright 2011-2015 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -67,7 +67,7 @@ static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, data->blocksize); - writel((u32)bbstate->bounce_buffer, &host->reg->sysad); + writel((u32)(unsigned long)bbstate->bounce_buffer, &host->reg->sysad); /* * DMASEL[4:3] * 00 = Selects SDMA @@ -233,8 +233,8 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, if (cmd->resp_type & MMC_RSP_136) { /* CRC is stripped so we need to do some shifting. */ for (i = 0; i < 4; i++) { - unsigned int offset = - (unsigned int)(&host->reg->rspreg3 - i); + unsigned long offset = + (unsigned long)(&host->reg->rspreg3 - i); cmd->response[i] = readl(offset) << 8; if (i != 3) { @@ -668,6 +668,16 @@ void tegra_mmc_init(void) const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra210 MMC controllers are present */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA210_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); + debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T30 mmc node(s)!\n", __func__); + return; + } + /* See if any Tegra124 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 0c5fdee..67b5702 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -512,6 +512,13 @@ static int keystone2_eth_rcv_packet(struct eth_device *dev) return pkt_size; } +#ifdef CONFIG_MCAST_TFTP +static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set) +{ + return 0; +} +#endif + /* * This function initializes the EMAC hardware. */ @@ -537,6 +544,9 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) dev->halt = keystone2_eth_close; dev->send = keystone2_eth_send_packet; dev->recv = keystone2_eth_rcv_packet; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = keystone2_eth_bcast_addr; +#endif eth_register(dev); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index c723dbb..b2006df 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -20,6 +20,7 @@ #include <phy.h> #include <miiphy.h> #include <watchdog.h> +#include <asm/system.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -58,7 +59,14 @@ #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ -#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ +#ifdef CONFIG_ARM64 +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ +#else +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ +#endif + +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ + ZYNQ_GEM_NWCFG_FDEN | \ ZYNQ_GEM_NWCFG_FSREM | \ ZYNQ_GEM_NWCFG_MDCCLKDIV) @@ -130,7 +138,7 @@ struct emac_bd { u32 status; }; -#define RX_BUF 3 +#define RX_BUF 32 /* Page table entries are set to 1MB, or multiples of 1MB * (not < 1MB). driver uses less bd's so use 1MB bdspace. */ @@ -155,7 +163,7 @@ struct zynq_gem_priv { static inline int mdio_wait(struct eth_device *dev) { struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - u32 timeout = 200; + u32 timeout = 20000; /* Wait till MDIO interface is ready to accept a new transaction. */ while (--timeout) { @@ -395,12 +403,18 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) priv->tx_bd->addr = (u32)ptr; priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | - ZYNQ_GEM_TXBUF_LAST_MASK; + ZYNQ_GEM_TXBUF_LAST_MASK | + ZYNQ_GEM_TXBUF_WRAP_MASK; addr = (u32) ptr; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); + + addr = (u32)priv->rxbuffers; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); barrier(); /* Start transmit */ @@ -436,8 +450,6 @@ static int zynq_gem_recv(struct eth_device *dev) if (frame_len) { u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; addr &= ~(ARCH_DMA_MINALIGN - 1); - u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); - invalidate_dcache_range(addr, addr + size); net_process_received_packet((u8 *)addr, frame_len); @@ -511,7 +523,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); - /* Align bd_space to 1MB */ + /* Align bd_space to MMU_SECTION_SHIFT */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 3be76c9..c7d93f9 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -207,8 +207,7 @@ int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, if (ret) return ret; - return pci_bus_write_config(bus, PCI_MASK_BUS(bdf), offset, value, - size); + return pci_bus_write_config(bus, bdf, offset, value, size); } int pci_write_config32(pci_dev_t bdf, int offset, u32 value) @@ -247,8 +246,7 @@ int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, if (ret) return ret; - return pci_bus_read_config(bus, PCI_MASK_BUS(bdf), offset, valuep, - size); + return pci_bus_read_config(bus, bdf, offset, valuep, size); } int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) @@ -303,14 +301,10 @@ int pci_auto_config_devices(struct udevice *bus) for (ret = device_find_first_child(bus, &dev); !ret && dev; ret = device_find_next_child(&dev)) { - struct pci_controller *ctlr_hose; unsigned int max_bus; debug("%s: device %s\n", __func__, dev->name); - - /* The root controller has the region information */ - ctlr_hose = hose->ctlr->uclass_priv; - max_bus = pciauto_config_device(ctlr_hose, pci_get_bdf(dev)); + max_bus = pciauto_config_device(hose, pci_get_bdf(dev)); sub_bus = max(sub_bus, max_bus); } debug("%s: done\n", __func__); @@ -328,7 +322,7 @@ int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) parent = hose->bus; /* Find the bus within the parent */ - ret = pci_bus_find_devfn(parent, bdf, &bus); + ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus); if (ret) { debug("%s: Cannot find device %x on bus %s: %d\n", __func__, bdf, parent->name, ret); @@ -383,7 +377,7 @@ static bool pci_match_one_id(const struct pci_device_id *id, * This only looks at certain fields in the descriptor. */ static int pci_find_and_bind_driver(struct udevice *parent, - struct pci_device_id *find_id, int devfn, + struct pci_device_id *find_id, pci_dev_t bdf, struct udevice **devp) { struct pci_driver_entry *start, *entry; @@ -430,8 +424,8 @@ static int pci_find_and_bind_driver(struct udevice *parent, } /* Bind a generic driver so that the device can be used */ - sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(devfn), - PCI_FUNC(devfn)); + sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf), + PCI_FUNC(bdf)); str = strdup(name); if (!str) return -ENOMEM; @@ -455,42 +449,44 @@ int pci_bind_bus_devices(struct udevice *bus) { ulong vendor, device; ulong header_type; - pci_dev_t devfn, end; + pci_dev_t bdf, end; bool found_multi; int ret; found_multi = false; - end = PCI_DEVFN(PCI_MAX_PCI_DEVICES - 1, PCI_MAX_PCI_FUNCTIONS - 1); - for (devfn = PCI_DEVFN(0, 0); devfn < end; devfn += PCI_DEVFN(0, 1)) { + end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1, + PCI_MAX_PCI_FUNCTIONS - 1); + for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end; + bdf += PCI_BDF(0, 0, 1)) { struct pci_child_platdata *pplat; struct udevice *dev; ulong class; - if (PCI_FUNC(devfn) && !found_multi) + if (PCI_FUNC(bdf) && !found_multi) continue; /* Check only the first access, we don't expect problems */ - ret = pci_bus_read_config(bus, devfn, PCI_HEADER_TYPE, + ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8); if (ret) goto error; - pci_bus_read_config(bus, devfn, PCI_VENDOR_ID, &vendor, + pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); if (vendor == 0xffff || vendor == 0x0000) continue; - if (!PCI_FUNC(devfn)) + if (!PCI_FUNC(bdf)) found_multi = header_type & 0x80; debug("%s: bus %d/%s: found device %x, function %d\n", __func__, - bus->seq, bus->name, PCI_DEV(devfn), PCI_FUNC(devfn)); - pci_bus_read_config(bus, devfn, PCI_DEVICE_ID, &device, + bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf)); + pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device, PCI_SIZE_16); - pci_bus_read_config(bus, devfn, PCI_CLASS_REVISION, &class, + pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class, PCI_SIZE_32); class >>= 8; /* Find this device in the device tree */ - ret = pci_bus_find_devfn(bus, devfn, &dev); + ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev); /* Search for a driver */ @@ -504,13 +500,13 @@ int pci_bind_bus_devices(struct udevice *bus) find_id.device = device; find_id.class = class; if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { - pci_bus_read_config(bus, devfn, + pci_bus_read_config(bus, bdf, PCI_SUBSYSTEM_VENDOR_ID, &val, PCI_SIZE_32); find_id.subvendor = val & 0xffff; find_id.subdevice = val >> 16; } - ret = pci_find_and_bind_driver(bus, &find_id, devfn, + ret = pci_find_and_bind_driver(bus, &find_id, bdf, &dev); } if (ret) @@ -518,7 +514,7 @@ int pci_bind_bus_devices(struct udevice *bus) /* Update the platform data */ pplat = dev_get_parent_platdata(dev); - pplat->devfn = devfn; + pplat->devfn = PCI_MASK_BUS(bdf); pplat->vendor = vendor; pplat->device = device; pplat->class = class; @@ -689,20 +685,20 @@ static int pci_uclass_child_post_bind(struct udevice *dev) return 0; } -int pci_bridge_read_config(struct udevice *bus, pci_dev_t devfn, uint offset, - ulong *valuep, enum pci_size_t size) +static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) { struct pci_controller *hose = bus->uclass_priv; - pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn); return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); } -int pci_bridge_write_config(struct udevice *bus, pci_dev_t devfn, uint offset, - ulong value, enum pci_size_t size) +static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) { struct pci_controller *hose = bus->uclass_priv; - pci_dev_t bdf = PCI_ADD_BUS(bus->seq, devfn); return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); } diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index e034ed1..a7af8cb 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -213,21 +213,39 @@ void pciauto_setup_device(struct pci_controller *hose, void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { - struct pci_region *pci_mem = hose->pci_mem; - struct pci_region *pci_prefetch = hose->pci_prefetch; - struct pci_region *pci_io = hose->pci_io; + struct pci_region *pci_mem; + struct pci_region *pci_prefetch; + struct pci_region *pci_io; u16 cmdstat, prefechable_64; +#ifdef CONFIG_DM_PCI + /* The root controller has the region information */ + struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + + pci_mem = ctlr_hose->pci_mem; + pci_prefetch = ctlr_hose->pci_prefetch; + pci_io = ctlr_hose->pci_io; +#else + pci_mem = hose->pci_mem; + pci_prefetch = hose->pci_prefetch; + pci_io = hose->pci_io; +#endif + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; /* Configure bus number registers */ +#ifdef CONFIG_DM_PCI + pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); + pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); +#else pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev) - hose->first_busno); pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus - hose->first_busno); +#endif pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { @@ -290,13 +308,30 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, void pciauto_postscan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { - struct pci_region *pci_mem = hose->pci_mem; - struct pci_region *pci_prefetch = hose->pci_prefetch; - struct pci_region *pci_io = hose->pci_io; + struct pci_region *pci_mem; + struct pci_region *pci_prefetch; + struct pci_region *pci_io; + +#ifdef CONFIG_DM_PCI + /* The root controller has the region information */ + struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + + pci_mem = ctlr_hose->pci_mem; + pci_prefetch = ctlr_hose->pci_prefetch; + pci_io = ctlr_hose->pci_io; +#else + pci_mem = hose->pci_mem; + pci_prefetch = hose->pci_prefetch; + pci_io = hose->pci_io; +#endif /* Configure bus number registers */ +#ifdef CONFIG_DM_PCI + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); +#else pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus - hose->first_busno); +#endif if (pci_mem) { /* Round memory allocator to 1MB boundary */ @@ -416,10 +451,26 @@ void pciauto_config_init(struct pci_controller *hose) */ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) { + struct pci_region *pci_mem; + struct pci_region *pci_prefetch; + struct pci_region *pci_io; unsigned int sub_bus = PCI_BUS(dev); unsigned short class; int n; +#ifdef CONFIG_DM_PCI + /* The root controller has the region information */ + struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + + pci_mem = ctlr_hose->pci_mem; + pci_prefetch = ctlr_hose->pci_prefetch; + pci_io = ctlr_hose->pci_io; +#else + pci_mem = hose->pci_mem; + pci_prefetch = hose->pci_prefetch; + pci_io = hose->pci_io; +#endif + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); switch (class) { @@ -427,8 +478,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); - pciauto_setup_device(hose, dev, 2, hose->pci_mem, - hose->pci_prefetch, hose->pci_io); + pciauto_setup_device(hose, dev, 2, pci_mem, + pci_prefetch, pci_io); #ifdef CONFIG_DM_PCI n = dm_pci_hose_probe_bus(hose, dev); @@ -458,8 +509,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) * just do a minimal setup of the bridge, * let the OS take care of the rest */ - pciauto_setup_device(hose, dev, 0, hose->pci_mem, - hose->pci_prefetch, hose->pci_io); + pciauto_setup_device(hose, dev, 0, pci_mem, + pci_prefetch, pci_io); DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); @@ -493,8 +544,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) DEBUGF("PCI AutoConfig: Found PowerPC device\n"); default: - pciauto_setup_device(hose, dev, 6, hose->pci_mem, - hose->pci_prefetch, hose->pci_io); + pciauto_setup_device(hose, dev, 6, pci_mem, + pci_prefetch, pci_io); break; } diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index f67c9c7..07f1726 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -224,7 +224,7 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose, #ifdef CONFIG_DM_PCI /* The root controller has the region information */ - hose = hose->ctlr->uclass_priv; + hose = pci_bus_to_hose(0); #endif /* @@ -289,6 +289,11 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose, return bus_addr; } +#ifdef CONFIG_DM_PCI + /* The root controller has the region information */ + hose = pci_bus_to_hose(0); +#endif + /* * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index c5c3e10..7ae1f0e 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -79,7 +79,7 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus) 250000000); plat->speed_hz = plat->frequency / 2; - debug("zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n", + debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, plat->frequency); return 0; @@ -309,7 +309,7 @@ static const struct dm_spi_ops zynq_spi_ops = { }; static const struct udevice_id zynq_spi_ids[] = { - { .compatible = "xlnx,zynq-spi" }, + { .compatible = "xlnx,zynq-spi-r1p6" }, { } }; diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index e2574d7..0edd557 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2009-2013 NVIDIA Corporation + * Copyright (c) 2009-2015 NVIDIA Corporation * Copyright (c) 2013 Lucas Stach * * SPDX-License-Identifier: GPL-2.0+ @@ -64,6 +64,7 @@ enum usb_ctlr_type { USB_CTLR_T20, USB_CTLR_T30, USB_CTLR_T114, + USB_CTLR_T210, USB_CTRL_COUNT, }; @@ -149,6 +150,15 @@ static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } }; +/* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ +static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, +}; + /* UTMIP Idle Wait Delay */ static const u8 utmip_idle_wait_delay = 17; @@ -177,6 +187,10 @@ static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { .has_hostpc = 1, .pll_parameter = (const unsigned *)T114_usb_pll, }, + { + .has_hostpc = 1, + .pll_parameter = (const unsigned *)T210_usb_pll, + }, }; /* @@ -458,6 +472,16 @@ static int init_utmi_usb_controller(struct fdt_usb *config, UTMIP_DEBOUNCE_CFG0_MASK, timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); + if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) { + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, + UTMIP_DEBOUNCE_CFG0_MASK, + (timing[PARAM_DEBOUNCE_A_TIME] >> 1) + << UTMIP_DEBOUNCE_CFG0_SHIFT); + clrsetbits_le32(&usbctlr->utmip_bias_cfg1, + UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK, + 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT); + } + setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); /* Disable battery charge enabling bit */ @@ -643,6 +667,10 @@ static int init_ulpi_usb_controller(struct fdt_usb *config, static void config_clock(const u32 timing[]) { + debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n", + __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], + timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); + clock_start_pll(CLOCK_ID_USB, timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); @@ -823,6 +851,7 @@ static const struct udevice_id ehci_usb_ids[] = { { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, + { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 }, { } }; diff --git a/include/command.h b/include/command.h index bd3fc04..6c04cd9 100644 --- a/include/command.h +++ b/include/command.h @@ -104,6 +104,8 @@ static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) extern int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +extern int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); + extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, char *const argv[]); diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h index 4d52ba1..141fc99 100644 --- a/include/configs/adp-ag101.h +++ b/include/configs/adp-ag101.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/ag101.h> +#include <asm/arch-ag101/ag101.h> /* * CPU and Board Configuration Options diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 06860b5..4296c6b 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/ag101.h> +#include <asm/arch-ag101/ag101.h> /* * CPU and Board Configuration Options diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h index 026696c..0c7573a 100644 --- a/include/configs/adp-ag102.h +++ b/include/configs/adp-ag102.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/ag102.h> +#include <asm/arch-ag102/ag102.h> /* * CPU and Board Configuration Options diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b90a60d..e9808a7 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -42,6 +42,8 @@ #define CONFIG_MISC_INIT_R +#define CONFIG_OF_LIBFDT + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b43489d..d148169 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -80,7 +80,7 @@ #endif /* Now bring in the rest of the common code. */ -#include <configs/ti_armv7_common.h> +#include <configs/ti_armv7_omap.h> /* Always 64 KiB env size */ #define CONFIG_ENV_SIZE (64 << 10) diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index a28ceb7..4f4ebf5 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -15,19 +15,17 @@ #define CONFIG_K2E_EVM /* U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "K2E EVM # " - #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "addr_mon=0x0c140000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=uImage-k2e-evm.dtb\0" \ - "name_mon=skern-k2e-evm.bin\0" \ + "name_fdt=k2e-evm.dtb\0" \ + "name_mon=skern-k2e.bin\0" \ "name_ubi=k2e-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2e-evm.gph\0" \ "name_fs=arago-console-image-k2e-evm.cpio.gz\0" -#include <configs/ks2_evm.h> +#include <configs/ti_armv7_keystone2.h> /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000 diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index eae7721..6c6dcb1 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -15,19 +15,17 @@ #define CONFIG_K2HK_EVM /* U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "K2HK EVM # " - #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "addr_mon=0x0c5f0000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=uImage-k2hk-evm.dtb\0" \ - "name_mon=skern-k2hk-evm.bin\0" \ + "name_fdt=k2hk-evm.dtb\0" \ + "name_mon=skern-k2hk.bin\0" \ "name_ubi=k2hk-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" -#include <configs/ks2_evm.h> +#include <configs/ti_armv7_keystone2.h> /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c200000 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 57da057..9bacfa4 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -15,19 +15,17 @@ #define CONFIG_K2L_EVM /* U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "K2L EVM # " - #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "addr_mon=0x0c140000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \ - "name_fdt=uImage-k2l-evm.dtb\0" \ - "name_mon=skern-k2l-evm.bin\0" \ + "name_fdt=k2l-evm.dtb\0" \ + "name_mon=skern-k2l.bin\0" \ "name_ubi=k2l-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2l-evm.gph\0" \ "name_fs=arago-console-image-k2l-evm.cpio.gz\0" -#include <configs/ks2_evm.h> +#include <configs/ti_armv7_keystone2.h> /* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index efc583f..6e3ce4d 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -109,7 +109,7 @@ /* USB */ #define CONFIG_MUSB_UDC -#define CONFIG_MUSB_HDC +#define CONFIG_MUSB_HCD #define CONFIG_USB_OMAP3 #define CONFIG_TWL4030_USB diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 76bf3b6..a1a90ec 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -105,7 +105,7 @@ "defaultdisplay=dvi\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ diff --git a/include/configs/p2571.h b/include/configs/p2571.h new file mode 100644 index 0000000..77faf5f --- /dev/null +++ b/include/configs/p2571.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _P2571_H +#define _P2571_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_MAX77620_POWER + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (P2571) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +/* + * TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back + * breaks 64-bit build in ci_udc.c + */ +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _P2571_H */ diff --git a/include/configs/pepper.h b/include/configs/pepper.h index 16149f6..0bdcf22 100644 --- a/include/configs/pepper.h +++ b/include/configs/pepper.h @@ -41,7 +41,7 @@ "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${mmcroot} " \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f33f9b4..f7bef70 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -133,7 +133,7 @@ #define CONFIG_I2C #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP24XX diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 1b4fd21..1ac3db6 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -15,6 +15,7 @@ #define CONFIG_OF_LIBFDT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R #define CONFIG_SYS_FLASH_BASE 0x08000000 @@ -61,6 +62,8 @@ #define CONFIG_STM32_HSE_HZ 8000000 +#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */ + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_CMDLINE_TAG @@ -80,7 +83,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "console=ttystm0,115200 earlyprintk consoleblank=0 ignore_loglevel" + "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" #define CONFIG_BOOTCOMMAND \ "run bootcmd_romfs" diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 483222f..e67ff7b 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -62,11 +62,19 @@ #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #endif +#ifdef CONFIG_ARM64 +#define FDT_HIGH "ffffffffffffffff" +#define INITRD_HIGH "ffffffffffffffff" +#else +#define FDT_HIGH "ffffffff" +#define INITRD_HIGH "ffffffff" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - "fdt_high=ffffffff\0" \ - "initrd_high=ffffffff\0" \ + "fdt_high=" FDT_HIGH "\0" \ + "initrd_high=" INITRD_HIGH "\0" \ BOOTENV \ BOARD_EXTRA_ENV_SETTINGS \ CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7b4c0d7..ffe167e 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -18,8 +18,11 @@ #include <asm/arch/tegra.h> /* get chip and board defs */ +/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ +#ifndef CONFIG_ARM64 #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#endif /* * Display CPU and Board information @@ -43,7 +46,9 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif +#ifndef CONFIG_ARM64 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ +#endif /* * NS16550 Configuration @@ -101,9 +106,11 @@ #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#ifndef CONFIG_ARM64 #ifndef CONFIG_SPL_BUILD #define CONFIG_USE_ARCH_MEMCPY #endif +#endif /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 1aee5c8..af7698d 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -26,7 +26,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h new file mode 100644 index 0000000..0348d47 --- /dev/null +++ b/include/configs/tegra210-common.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA210_COMMON_H_ +#define _TEGRA210_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A57 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* Generic Interrupt Controller */ +#define CONFIG_GICV2 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_LOADADDR 0x81000000 +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 + +#endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 4d2ae28..9697431 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -94,6 +94,6 @@ #endif /* Now bring in the rest of the common code. */ -#include <configs/ti_armv7_common.h> +#include <configs/ti_armv7_omap.h> #endif /* __CONFIG_TI_AM335X_COMMON_H__ */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 0aea7d1..6dc5ebd 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -18,8 +18,6 @@ #define __CONFIG_TI_ARMV7_COMMON_H__ /* Common define for many platforms. */ -#define CONFIG_OMAP -#define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD /* @@ -76,8 +74,11 @@ #define CONFIG_NR_DRAM_BANKS 1 #endif #define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) +#endif /* Timer information. */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ @@ -86,39 +87,20 @@ #define CONFIG_I2C #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP24XX /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC #define CONFIG_CMD_MMC /* McSPI IP block */ #define CONFIG_SPI -#define CONFIG_OMAP3_SPI #define CONFIG_CMD_SPI /* GPIO block */ -#define CONFIG_OMAP_GPIO #define CONFIG_CMD_GPIO /* - * GPMC NAND block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#ifdef CONFIG_NAND -#define CONFIG_NAND_OMAP_GPMC -#ifndef CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_BASE 0x8000000 -#endif -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND -#endif - -/* * The following are general good-enough settings for U-Boot. We set a * large malloc pool as we generally have a lot of DDR, and we opt for * function over binary size in the main portion of U-Boot as this is @@ -161,7 +143,7 @@ * mtdparts, both for ease of use in U-Boot and for passing information * on to the Linux kernel. */ -#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) || defined(CONFIG_NAND_DAVINCI) #define CONFIG_MTD_DEVICE /* Required for mtdparts */ #define CONFIG_CMD_MTDPARTS #endif @@ -252,15 +234,14 @@ #define CONFIG_SPL_EXT_SUPPORT #endif -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ -#endif +#define CONFIG_SYS_THUMB_BUILD /* General parts of the framework, required. */ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/ks2_evm.h b/include/configs/ti_armv7_keystone2.h index eb4bcaf..2b6a229 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ti_armv7_keystone2.h @@ -14,10 +14,7 @@ /* U-Boot Build Configuration */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_THUMB_BUILD /* SoC Configuration */ #define CONFIG_ARCH_CPU_INIT @@ -28,11 +25,9 @@ /* Memory Configuration */ #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ GENERATED_GBL_DATA_SIZE) @@ -49,15 +44,10 @@ #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ CONFIG_SYS_SPL_MALLOC_SIZE + \ CONFIG_SPL_STACK_SIZE - 4) -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SPL_FRAMEWORK /* UART Configuration */ #define CONFIG_SYS_NS16550 @@ -68,13 +58,10 @@ #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* SPI Configuration */ -#define CONFIG_SPI #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI -#define CONFIG_CMD_SPI #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED @@ -148,7 +135,6 @@ #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE /* I2C Configuration */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_DAVINCI #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ @@ -185,7 +171,6 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x100000 #define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE #define CONFIG_RBTREE #define CONFIG_LZO #define MTDIDS_DEFAULT "nand0=davinci_nand.0" @@ -198,8 +183,6 @@ #define CONFIG_USB_XHCI_DWC3 #define CONFIG_USB_XHCI_KEYSTONE #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION #define CONFIG_FS_FAT #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -209,65 +192,46 @@ #define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE /* U-Boot command configuration */ -#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES -#define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_NAND #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC /* U-Boot general configuration */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_MISC_INIT_R -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE 2048 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE #define CONFIG_TIMESTAMP /* EDMA3 */ #define CONFIG_TI_EDMA3 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" #define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "boot=ubi\0" \ "tftp_root=/\0" \ "nfs_root=/export\0" \ "mem_lpae=1\0" \ "mem_reserve=512M\0" \ - "addr_fdt=0x87000000\0" \ - "addr_kern=0x88000000\0" \ - "addr_uboot=0x87000000\0" \ - "addr_fs=0x82000000\0" \ "addr_ubi=0x82000000\0" \ "addr_secdb_key=0xc000000\0" \ - "fdt_high=0xffffffff\0" \ - "name_kern=uImage-keystone-evm.bin\0" \ + "name_kern=zImage\0" \ "run_mon=mon_install ${addr_mon}\0" \ - "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ + "run_kern=bootz ${loadaddr} - ${fdtaddr}\0" \ "init_net=run args_all args_net\0" \ "init_ubi=run args_all args_ubi; " \ "ubi part ubifs; ubifsmount ubi:boot;" \ "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ - "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ - "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ - "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ - "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ + "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ + "get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0" \ + "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ + "get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0" \ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ @@ -280,10 +244,10 @@ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ "${nfs_options} ip=dhcp\0" \ "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ - "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ - "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ + "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ + "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ "burn_ubi=nand erase.part ubifs; " \ "nand write ${addr_ubi} ubifs ${filesize}\0" \ @@ -302,15 +266,26 @@ #define CONFIG_BOOTARGS \ /* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP -#define CONFIG_SYS_BARGSIZE 1024 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) -#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) -#define CONFIG_SUPPORT_RAW_INITRD +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +/* We wont be loading up OS from SPL for now.. */ +#undef CONFIG_SPL_OS_BOOT + +/* We do not have MMC support.. yet.. */ +#undef CONFIG_SPL_LIBDISK_SUPPORT +#undef CONFIG_SPL_MMC_SUPPORT +#undef CONFIG_SPL_FAT_SUPPORT +#undef CONFIG_SPL_EXT_SUPPORT +#undef CONFIG_MMC +#undef CONFIG_GENERIC_MMC +#undef CONFIG_CMD_MMC + +/* And no support for GPIO, yet.. */ +#undef CONFIG_SPL_GPIO_SUPPORT +#undef CONFIG_CMD_GPIO /* we may include files below only after all above definitions */ #include <asm/arch/hardware.h> diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h new file mode 100644 index 0000000..7548170 --- /dev/null +++ b/include/configs/ti_armv7_omap.h @@ -0,0 +1,49 @@ +/* + * ti_armv7_omap.h + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The various ARMv7 SoCs from TI all share a number of IP blocks when + * implementing a given feature. This is meant to isolate the features + * that are based on OMAP architecture. + */ +#ifndef __CONFIG_TI_ARMV7_OMAP_H__ +#define __CONFIG_TI_ARMV7_OMAP_H__ + +/* Common defines for all OMAP architecture based SoCs */ +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +/* I2C IP block */ +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX + +/* MMC/SD IP block */ +#define CONFIG_OMAP_HSMMC + +/* SPI IP Block */ +#define CONFIG_OMAP3_SPI + +/* GPIO block */ +#define CONFIG_OMAP_GPIO + +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#ifndef CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE 0x8000000 +#endif +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_CMD_NAND +#endif + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 429b109..be231a5 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -84,6 +84,6 @@ #endif /* Now bring in the rest of the common code. */ -#include <configs/ti_armv7_common.h> +#include <configs/ti_armv7_omap.h> #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index e966134..b299aed 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -52,7 +52,7 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif -#include <configs/ti_armv7_common.h> +#include <configs/ti_armv7_omap.h> /* * Hardware drivers @@ -171,6 +171,7 @@ /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ #undef CONFIG_SYS_I2C #undef CONFIG_SYS_I2C_OMAP24XX +#undef CONFIG_SPL_I2C_SUPPORT #endif #endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 4179a57..fe04692 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -40,14 +40,12 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_PALMAS_POWER -#endif #include <asm/arch/cpu.h> #include <asm/arch/omap.h> -#include <configs/ti_armv7_common.h> +#include <configs/ti_armv7_omap.h> /* * Hardware drivers diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ad82ed6..68853b6 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -40,7 +40,6 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP" -#define CONFIG_SYS_TEXT_BASE 0x8000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) /* Flat Device Tree Definitions */ @@ -53,16 +52,20 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000) /* Serial setup */ -#define CONFIG_ZYNQ_SERIAL_UART0 -#define CONFIG_ZYNQ_SERIAL +#if defined(CONFIG_ZYNQMP_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_ARMV8 +#else +# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +# define CONFIG_ZYNQ_SERIAL +# endif +#endif #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_ZYNQ_SDHCI0 - /* Command line configuration */ #define CONFIG_CMD_ENV #define CONFIG_CMD_EXT2 @@ -73,6 +76,16 @@ #define CONFIG_CMD_ELF #define CONFIG_MP +#define CONFIG_CMD_MII + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL +#define CONFIG_BOOTP_SERVERIP + /* SPI */ #ifdef CONFIG_ZYNQ_SPI # define CONFIG_SPI_FLASH_SST @@ -127,8 +140,16 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_ZYNQ_I2C0 -#define CONFIG_SYS_I2C_ZYNQ +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) || \ + defined(CONFIG_ZYNQ_GEM2) || defined(CONFIG_ZYNQ_GEM3) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +#endif /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) @@ -138,8 +159,6 @@ # define CONFIG_SYS_I2C_ZYNQ_SLAVE 0 #endif -#define CONFIG_ZYNQMP_EEPROM - /* EEPROM */ #ifdef CONFIG_ZYNQMP_EEPROM # define CONFIG_CMD_EEPROM @@ -150,6 +169,17 @@ # define CONFIG_SYS_EEPROM_SIZE (64 * 1024) #endif +#ifdef CONFIG_AHCI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_SCSI +#endif + #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h new file mode 100644 index 0000000..c872f7c --- /dev/null +++ b/include/configs/xilinx_zynqmp_ep.h @@ -0,0 +1,27 @@ +/* + * Configuration for Xilinx ZynqMP emulation + * platforms. See zynqmp-common.h for ZynqMP + * common configs + * + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * + * Based on Configuration for Versatile Express + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_EP_H +#define __CONFIG_ZYNQMP_EP_H + +#define CONFIG_ZYNQ_SERIAL_UART0 +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_ZYNQ_EEPROM +#define CONFIG_AHCI + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_EP_H */ diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 16b9047..7a1b872 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -21,6 +21,9 @@ # define CONFIG_ZYNQ_SDHCI0 # define CONFIG_ZYNQ_SPI +#elif defined(CONFIG_ZC770_XM011) +# define CONFIG_ZYNQ_SERIAL_UART1 + #elif defined(CONFIG_ZC770_XM012) # define CONFIG_ZYNQ_SERIAL_UART1 # undef CONFIG_SYS_NO_FLASH diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h new file mode 100644 index 0000000..d134741 --- /dev/null +++ b/include/dt-bindings/clock/tegra210-car.h @@ -0,0 +1,342 @@ +/* + * This header provides Tegra210-specific constants for binding + * nvidia,tegra210-car. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA210_CLK_ISPB 3 +#define TEGRA210_CLK_RTC 4 +#define TEGRA210_CLK_TIMER 5 +#define TEGRA210_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA210_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA210_CLK_I2S1 11 +#define TEGRA210_CLK_I2C1 12 +/* 13 */ +#define TEGRA210_CLK_SDMMC1 14 +#define TEGRA210_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA210_CLK_PWM 17 +#define TEGRA210_CLK_I2S2 18 +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA210_CLK_USBD 22 +#define TEGRA210_CLK_ISP 23 +/* 26 */ +/* 25 */ +#define TEGRA210_CLK_DISP2 26 +#define TEGRA210_CLK_DISP1 27 +#define TEGRA210_CLK_HOST1X 28 +#define TEGRA210_CLK_VCP 29 +#define TEGRA210_CLK_I2S0 30 +/* 31 */ + +#define TEGRA210_CLK_MC 32 +/* 33 */ +#define TEGRA210_CLK_APBDMA 34 +/* 35 */ +#define TEGRA210_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA210_CLK_KFUSE 40 +#define TEGRA210_CLK_SBC1 41 +#define TEGRA210_CLK_NOR 42 +/* 43 */ +#define TEGRA210_CLK_SBC2 44 +/* 45 */ +#define TEGRA210_CLK_SBC3 46 +#define TEGRA210_CLK_I2C5 47 +#define TEGRA210_CLK_DSIA 48 +/* 49 */ +#define TEGRA210_CLK_MIPI 50 +#define TEGRA210_CLK_HDMI 51 +#define TEGRA210_CLK_CSI 52 +/* 53 */ +#define TEGRA210_CLK_I2C2 54 +#define TEGRA210_CLK_UARTC 55 +#define TEGRA210_CLK_MIPI_CAL 56 +#define TEGRA210_CLK_EMC 57 +#define TEGRA210_CLK_USB2 58 +#define TEGRA210_CLK_USB3 59 +/* 60 */ +#define TEGRA210_CLK_VDE 61 +#define TEGRA210_CLK_BSEA 62 +#define TEGRA210_CLK_BSEV 63 + +/* 64 */ +#define TEGRA210_CLK_UARTD 65 +/* 66 */ +#define TEGRA210_CLK_I2C3 67 +#define TEGRA210_CLK_SBC4 68 +#define TEGRA210_CLK_SDMMC3 69 +#define TEGRA210_CLK_PCIE 70 +#define TEGRA210_CLK_OWR 71 +#define TEGRA210_CLK_AFI 72 +#define TEGRA210_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA210_CLK_LA 76 +#define TEGRA210_CLK_TRACE 77 +#define TEGRA210_CLK_SOC_THERM 78 +#define TEGRA210_CLK_DTV 79 +/* 80 */ +#define TEGRA210_CLK_I2CSLOW 81 +#define TEGRA210_CLK_DSIB 82 +#define TEGRA210_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA210_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA210_CLK_MSENC 91 +#define TEGRA210_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA210_CLK_MSELECT 99 +#define TEGRA210_CLK_TSENSOR 100 +#define TEGRA210_CLK_I2S3 101 +#define TEGRA210_CLK_I2S4 102 +#define TEGRA210_CLK_I2C4 103 +#define TEGRA210_CLK_SBC5 104 +#define TEGRA210_CLK_SBC6 105 +#define TEGRA210_CLK_D_AUDIO 106 +#define TEGRA210_CLK_APBIF 107 +#define TEGRA210_CLK_DAM0 108 +#define TEGRA210_CLK_DAM1 109 +#define TEGRA210_CLK_DAM2 110 +#define TEGRA210_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA210_CLK_AUDIO0_2X 113 +#define TEGRA210_CLK_AUDIO1_2X 114 +#define TEGRA210_CLK_AUDIO2_2X 115 +#define TEGRA210_CLK_AUDIO3_2X 116 +#define TEGRA210_CLK_AUDIO4_2X 117 +#define TEGRA210_CLK_SPDIF_2X 118 +#define TEGRA210_CLK_ACTMON 119 +#define TEGRA210_CLK_EXTERN1 120 +#define TEGRA210_CLK_EXTERN2 121 +#define TEGRA210_CLK_EXTERN3 122 +#define TEGRA210_CLK_SATA_OOB 123 +#define TEGRA210_CLK_SATA 124 +#define TEGRA210_CLK_HDA 125 +/* 126 */ +#define TEGRA210_CLK_SE 127 + +#define TEGRA210_CLK_HDA2HDMI 128 +#define TEGRA210_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA210_CLK_CILAB 144 +#define TEGRA210_CLK_CILCD 145 +#define TEGRA210_CLK_CILE 146 +#define TEGRA210_CLK_DSIALP 147 +#define TEGRA210_CLK_DSIBLP 148 +#define TEGRA210_CLK_ENTROPY 149 +#define TEGRA210_CLK_DDS 150 +/* 151 */ +#define TEGRA210_CLK_DP2 152 +#define TEGRA210_CLK_AMX 153 +#define TEGRA210_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA210_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA210_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA210_CLK_VIM2_CLK 171 +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +#define TEGRA210_CLK_HDMI_AUDIO 176 +#define TEGRA210_CLK_CLK72MHZ 177 +#define TEGRA210_CLK_VIC03 178 +/* 179 */ +#define TEGRA210_CLK_ADX1 180 +#define TEGRA210_CLK_DPAUX 181 +#define TEGRA210_CLK_SOR0 182 +/* 183 */ +#define TEGRA210_CLK_GPU 184 +#define TEGRA210_CLK_AMX1 185 +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ +#define TEGRA210_CLK_UARTB 192 +#define TEGRA210_CLK_VFIR 193 +#define TEGRA210_CLK_SPDIF_IN 194 +#define TEGRA210_CLK_SPDIF_OUT 195 +#define TEGRA210_CLK_VI 196 +#define TEGRA210_CLK_VI_SENSOR 197 +#define TEGRA210_CLK_FUSE 198 +#define TEGRA210_CLK_FUSE_BURN 199 +#define TEGRA210_CLK_CLK_32K 200 +#define TEGRA210_CLK_CLK_M 201 +#define TEGRA210_CLK_CLK_M_DIV2 202 +#define TEGRA210_CLK_CLK_M_DIV4 203 +#define TEGRA210_CLK_PLL_REF 204 +#define TEGRA210_CLK_PLL_C 205 +#define TEGRA210_CLK_PLL_C_OUT1 206 +#define TEGRA210_CLK_PLL_C2 207 +#define TEGRA210_CLK_PLL_C3 208 +#define TEGRA210_CLK_PLL_M 209 +#define TEGRA210_CLK_PLL_M_OUT1 210 +#define TEGRA210_CLK_PLL_P 211 +#define TEGRA210_CLK_PLL_P_OUT1 212 +#define TEGRA210_CLK_PLL_P_OUT2 213 +#define TEGRA210_CLK_PLL_P_OUT3 214 +#define TEGRA210_CLK_PLL_P_OUT4 215 +#define TEGRA210_CLK_PLL_A 216 +#define TEGRA210_CLK_PLL_A_OUT0 217 +#define TEGRA210_CLK_PLL_D 218 +#define TEGRA210_CLK_PLL_D_OUT0 219 +#define TEGRA210_CLK_PLL_D2 220 +#define TEGRA210_CLK_PLL_D2_OUT0 221 +#define TEGRA210_CLK_PLL_U 222 +#define TEGRA210_CLK_PLL_U_480M 223 + +#define TEGRA210_CLK_PLL_U_60M 224 +#define TEGRA210_CLK_PLL_U_48M 225 +#define TEGRA210_CLK_PLL_U_12M 226 +/* 227 */ +/* 228 */ +#define TEGRA210_CLK_PLL_RE_VCO 229 +#define TEGRA210_CLK_PLL_RE_OUT 230 +#define TEGRA210_CLK_PLL_E 231 +#define TEGRA210_CLK_SPDIF_IN_SYNC 232 +#define TEGRA210_CLK_I2S0_SYNC 233 +#define TEGRA210_CLK_I2S1_SYNC 234 +#define TEGRA210_CLK_I2S2_SYNC 235 +#define TEGRA210_CLK_I2S3_SYNC 236 +#define TEGRA210_CLK_I2S4_SYNC 237 +#define TEGRA210_CLK_VIMCLK_SYNC 238 +#define TEGRA210_CLK_AUDIO0 239 +#define TEGRA210_CLK_AUDIO1 240 +#define TEGRA210_CLK_AUDIO2 241 +#define TEGRA210_CLK_AUDIO3 242 +#define TEGRA210_CLK_AUDIO4 243 +#define TEGRA210_CLK_SPDIF 244 +#define TEGRA210_CLK_CLK_OUT_1 245 +#define TEGRA210_CLK_CLK_OUT_2 246 +#define TEGRA210_CLK_CLK_OUT_3 247 +#define TEGRA210_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA210_CLK_XUSB_HOST_SRC 252 +#define TEGRA210_CLK_XUSB_FALCON_SRC 253 +#define TEGRA210_CLK_XUSB_FS_SRC 254 +#define TEGRA210_CLK_XUSB_SS_SRC 255 + +#define TEGRA210_CLK_XUSB_DEV_SRC 256 +#define TEGRA210_CLK_XUSB_DEV 257 +#define TEGRA210_CLK_XUSB_HS_SRC 258 +#define TEGRA210_CLK_SCLK 259 +#define TEGRA210_CLK_HCLK 260 +#define TEGRA210_CLK_PCLK 261 +/* 262 */ +/* 263 */ +#define TEGRA210_CLK_DFLL_REF 264 +#define TEGRA210_CLK_DFLL_SOC 265 +#define TEGRA210_CLK_VI_SENSOR2 266 +#define TEGRA210_CLK_PLL_P_OUT5 267 +#define TEGRA210_CLK_CML0 268 +#define TEGRA210_CLK_CML1 269 +#define TEGRA210_CLK_PLL_C4 270 +#define TEGRA210_CLK_PLL_DP 271 +#define TEGRA210_CLK_PLL_E_MUX 272 +#define TEGRA210_CLK_PLLD_DSI 273 +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA210_CLK_AUDIO0_MUX 300 +#define TEGRA210_CLK_AUDIO1_MUX 301 +#define TEGRA210_CLK_AUDIO2_MUX 302 +#define TEGRA210_CLK_AUDIO3_MUX 303 +#define TEGRA210_CLK_AUDIO4_MUX 304 +#define TEGRA210_CLK_SPDIF_MUX 305 +#define TEGRA210_CLK_CLK_OUT_1_MUX 306 +#define TEGRA210_CLK_CLK_OUT_2_MUX 307 +#define TEGRA210_CLK_CLK_OUT_3_MUX 308 +/* 309 */ +/* 310 */ +#define TEGRA210_CLK_SOR0_LVDS 311 +#define TEGRA210_CLK_XUSB_SS_DIV2 312 + +#define TEGRA210_CLK_PLL_M_UD 313 +#define TEGRA210_CLK_PLL_C_UD 314 + +#define TEGRA210_CLK_PLL_X 227 +#define TEGRA210_CLK_PLL_X_OUT0 228 + +#define TEGRA210_CLK_CCLK_G 262 +#define TEGRA210_CLK_CCLK_LP 263 + +#define TEGRA210_CLK_CLK_MAX 315 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 2323603..4b3f8d1 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -137,6 +137,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ @@ -145,6 +146,8 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, /* Tegra124 XUSB pad controller */ + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, + /* Tegra210 XUSB pad controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ diff --git a/include/linker_lists.h b/include/linker_lists.h index b22d169..76898ab 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -83,7 +83,7 @@ * global list name ("outer"); iterators for only a sub-list should use * the full sub-list name ("outer_2_inner"). * - * Here is an example of the sections generated from a global list + * Here is an example of the sections generated from a global list * named "drivers", two sub-lists named "i2c" and "pci", and iterators * defined for the whole list and each sub-list: * @@ -103,7 +103,7 @@ */ /** - * ll_sym() - Access a linker-generated array entry + * llsym() - Access a linker-generated array entry * @_type: Data type of the entry * @_name: Name of the entry * @_list: name of the list. Should contain only characters allowed @@ -142,7 +142,7 @@ * the inner sections are present in the array. * * Example: - * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = { * .x = 3, * .y = 4, * }; @@ -162,7 +162,7 @@ * This is like ll_entry_declare() but creates multiple entries. It should * be assigned to an array. * - * ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub) = { * { .x = 3, .y = 4 }, * { .x = 8, .y = 2 }, * { .x = 1, .y = 7 } @@ -222,7 +222,7 @@ */ #define ll_entry_end(_type, _list) \ ({ \ - static char end[0] __aligned(4) __attribute__((unused, \ + static char end[0] __aligned(4) __attribute__((unused, \ section(".u_boot_list_2_"#_list"_3"))); \ (_type *)&end; \ }) @@ -256,8 +256,8 @@ * @_name: Name of the entry * @_list: Name of the list in which this entry is placed * - * This function returns a pointer to a particular entry in LG-array - * identified by the subsection of u_boot_list where the entry resides + * This function returns a pointer to a particular entry in linker-generated + * array identified by the subsection of u_boot_list where the entry resides * and it's name. * * Example: @@ -272,7 +272,7 @@ ({ \ extern _type _u_boot_list_2_##_list##_2_##_name; \ _type *_ll_result = \ - &_u_boot_list_2_##_list##_2_##_name; \ + &_u_boot_list_2_##_list##_2_##_name; \ _ll_result; \ }) @@ -297,7 +297,7 @@ }) /** - * ll_entry_end() - Point after last entry of last linker-generated array + * ll_end() - Point after last entry of last linker-generated array * @_type: Data type of the entry * * This function returns (_type *) pointer after the very last entry of @@ -311,7 +311,7 @@ */ #define ll_end(_type) \ ({ \ - static char end[0] __aligned(4) __attribute__((unused, \ + static char end[0] __aligned(4) __attribute__((unused, \ section(".u_boot_list_3"))); \ (_type *)&end; \ }) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 232ca74..a954051 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -31,6 +31,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"), COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"), COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), @@ -38,6 +39,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"), COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"), COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"), + COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), @@ -88,29 +90,45 @@ const char *fdtdec_get_compatible(enum fdt_compat_id id) fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, const char *prop_name, fdt_size_t *sizep) { - const fdt_addr_t *cell; - int len; + const fdt32_t *ptr, *end; + int parent, na, ns, len; + fdt_addr_t addr; debug("%s: %s: ", __func__, prop_name); - cell = fdt_getprop(blob, node, prop_name, &len); - if (cell && ((!sizep && len == sizeof(fdt_addr_t)) || - len == sizeof(fdt_addr_t) * 2)) { - fdt_addr_t addr = fdt_addr_to_cpu(*cell); - if (sizep) { - const fdt_size_t *size; - - size = (fdt_size_t *)((char *)cell + - sizeof(fdt_addr_t)); - *sizep = fdt_size_to_cpu(*size); - debug("addr=%08lx, size=%llx\n", - (ulong)addr, (u64)*sizep); - } else { - debug("%08lx\n", (ulong)addr); - } - return addr; + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("(no parent found)\n"); + return FDT_ADDR_T_NONE; } - debug("(not found)\n"); - return FDT_ADDR_T_NONE; + + na = fdt_address_cells(blob, parent); + ns = fdt_size_cells(blob, parent); + + ptr = fdt_getprop(blob, node, prop_name, &len); + if (!ptr) { + debug("(not found)\n"); + return FDT_ADDR_T_NONE; + } + + end = ptr + len / sizeof(*ptr); + + if (ptr + na + ns > end) { + debug("(not enough data: expected %d bytes, got %d bytes)\n", + (na + ns) * 4, len); + return FDT_ADDR_T_NONE; + } + + addr = fdtdec_get_number(ptr, na); + + if (sizep) { + *sizep = fdtdec_get_number(ptr + na, ns); + debug("addr=%pa, size=%pa\n", &addr, sizep); + } else { + debug("%pa\n", &addr); + } + + return addr; } fdt_addr_t fdtdec_get_addr(const void *blob, int node, diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index d20f20a..f02eb37 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -131,17 +131,15 @@ cc-disable-warning = $(call try-run,\ $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) # cc-version -# Usage gcc-ver := $(call cc-version) cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC)) # cc-fullversion -# Usage gcc-ver := $(call cc-fullversion) cc-fullversion = $(shell $(CONFIG_SHELL) \ $(srctree)/scripts/gcc-version.sh -p $(CC)) # cc-ifversion # Usage: EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1) -cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3)) +cc-ifversion = $(shell [ $(cc-version) $(1) $(2) ] && echo $(3) || echo $(4)) # added for U-Boot binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) @@ -163,13 +161,12 @@ ld-option = $(call try-run,\ ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2)) # ld-version -# Usage: $(call ld-version) # Note this is mainly for HJ Lu's 3 number binutil versions ld-version = $(shell $(LD) --version | $(srctree)/scripts/ld-version.sh) # ld-ifversion # Usage: $(call ld-ifversion, -ge, 22252, y) -ld-ifversion = $(shell [ $(call ld-version) $(1) $(2) ] && echo $(3)) +ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4)) ###### @@ -185,6 +182,24 @@ build := -f $(srctree)/scripts/Makefile.build obj # $(Q)$(MAKE) $(modbuiltin)=dir modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.dtbinst obj= +# Usage: +# $(Q)$(MAKE) $(dtbinst)=dir +dtbinst := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.dtbinst obj + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj= +# Usage: +# $(Q)$(MAKE) $(clean)=dir +clean := -f $(srctree)/scripts/Makefile.clean obj + +### +# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.headersinst obj= +# Usage: +# $(Q)$(MAKE) $(hdr-inst)=dir +hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj + # Prefix -I with $(srctree) if it is not an absolute path. # skip if -I has no parameter addtree = $(if $(patsubst -I%,%,$(1)), \ diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 36bfa17..d668982 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -107,6 +107,7 @@ include/config.h: scripts/Makefile.autoconf create_symlink FORCE # Otherwise, create a symbolic link to arch/$(ARCH)/include/asm/arch-$(SOC). PHONY += create_symlink create_symlink: +ifdef CONFIG_CREATE_ARCH_SYMLINK ifneq ($(KBUILD_SRC),) $(Q)mkdir -p include/asm $(Q)if [ -d $(KBUILD_SRC)/arch/$(ARCH)/mach-$(SOC)/include/mach ]; then \ @@ -123,6 +124,7 @@ else fi; \ ln -fsn $$dest arch/$(ARCH)/include/asm/arch endif +endif PHONY += FORCE FORCE: diff --git a/scripts/Makefile.build b/scripts/Makefile.build index ac0554e..de818ae 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -253,8 +253,9 @@ sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH "$(if $(part-of-module),1,0)" "$(@)"; recordmcount_source := $(srctree)/scripts/recordmcount.pl endif -cmd_record_mcount = \ - if [ "$(findstring -pg,$(_c_flags))" = "-pg" ]; then \ +cmd_record_mcount = \ + if [ "$(findstring $(CC_FLAGS_FTRACE),$(_c_flags))" = \ + "$(CC_FLAGS_FTRACE)" ]; then \ $(sub_cmd_record_mcount) \ fi; endif diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean index 21e1f21..4853631 100644 --- a/scripts/Makefile.clean +++ b/scripts/Makefile.clean @@ -7,10 +7,7 @@ src := $(obj) PHONY := __clean __clean: -# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir -# Usage: -# $(Q)$(MAKE) $(clean)=dir -clean := -f $(srctree)/scripts/Makefile.clean obj +include scripts/Kbuild.include # The filename Kbuild has precedence over Makefile kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) @@ -50,19 +47,19 @@ __clean-files := $(extra-y) $(extra-m) $(extra-) \ __clean-files := $(filter-out $(no-clean-files), $(__clean-files)) -# as clean-files is given relative to the current directory, this adds -# a $(obj) prefix, except for absolute paths +# clean-files is given relative to the current directory, unless it +# starts with $(objtree)/ (which means "./", so do not add "./" unless +# you want to delete a file from the toplevel object directory). __clean-files := $(wildcard \ - $(addprefix $(obj)/, $(filter-out /%, $(__clean-files))) \ - $(filter /%, $(__clean-files))) + $(addprefix $(obj)/, $(filter-out $(objtree)/%, $(__clean-files))) \ + $(filter $(objtree)/%, $(__clean-files))) -# as clean-dirs is given relative to the current directory, this adds -# a $(obj) prefix, except for absolute paths +# same as clean-files __clean-dirs := $(wildcard \ - $(addprefix $(obj)/, $(filter-out /%, $(clean-dirs))) \ - $(filter /%, $(clean-dirs))) + $(addprefix $(obj)/, $(filter-out $(objtree)/%, $(clean-dirs))) \ + $(filter $(objtree)/%, $(clean-dirs))) # ========================================================================== @@ -79,9 +76,6 @@ endif ifneq ($(strip $(__clean-dirs)),) +$(call cmd,cleandir) endif -ifneq ($(strip $(clean-rule)),) - +$(clean-rule) -endif @: @@ -96,11 +90,6 @@ PHONY += $(subdir-ymn) $(subdir-ymn): $(Q)$(MAKE) $(clean)=$@ -# If quiet is set, only print short version of command - -cmd = @$(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))' &&) $(cmd_$(1)) - - # Declare the contents of the .PHONY variable as phony. We keep that # information in a variable se we can use it in if_changed and friends. diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8731fc6..84915d7 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -119,6 +119,16 @@ _c_flags += $(if $(patsubst n%,, \ $(CFLAGS_GCOV)) endif +# +# Enable address sanitizer flags for kernel except some files or directories +# we don't want to check (depends on variables KASAN_SANITIZE_obj.o, KASAN_SANITIZE) +# +ifeq ($(CONFIG_KASAN),y) +_c_flags += $(if $(patsubst n%,, \ + $(KASAN_SANITIZE_$(basetarget).o)$(KASAN_SANITIZE)y), \ + $(CFLAGS_KASAN)) +endif + # If building the kernel in a separate objtree expand all occurrences # of -Idir to -I$(srctree)/dir except for absolute paths (starting with '/'). @@ -274,7 +284,8 @@ $(obj)/%.dtb.S: $(obj)/%.dtb quiet_cmd_dtc = DTC $@ # Modified for U-Boot -cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ + $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ @@ -285,18 +296,6 @@ $(obj)/%.dtb: $(src)/%.dts FORCE dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) -# Helper targets for Installing DTBs into the boot directory -quiet_cmd_dtb_install = INSTALL $< - cmd_dtb_install = cp $< $(2) - -_dtbinst_pre_: - $(Q)if [ -d $(INSTALL_DTBS_PATH).old ]; then rm -rf $(INSTALL_DTBS_PATH).old; fi - $(Q)if [ -d $(INSTALL_DTBS_PATH) ]; then mv $(INSTALL_DTBS_PATH) $(INSTALL_DTBS_PATH).old; fi - $(Q)mkdir -p $(INSTALL_DTBS_PATH) - -%.dtb_dtbinst_: $(obj)/%.dtb _dtbinst_pre_ - $(call cmd,dtb_install,$(INSTALL_DTBS_PATH)) - # Bzip2 # --------------------------------------------------------------------------- diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index ff4ce6e..46ddf2d 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -2,7 +2,7 @@ # Kernel configuration targets # These targets are used from top-level makefile -PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config \ +PHONY += xconfig gconfig menuconfig config silentoldconfig update-po-config \ localmodconfig localyesconfig # Added for U-Boot @@ -17,30 +17,31 @@ else Kconfig := Kconfig endif +ifeq ($(quiet),silent_) +silent := -s +endif + # We need this, in case the user has it in its environment unexport CONFIG_ xconfig: $(obj)/qconf - $< $(Kconfig) + $< $(silent) $(Kconfig) gconfig: $(obj)/gconf - $< $(Kconfig) + $< $(silent) $(Kconfig) menuconfig: $(obj)/mconf - $< $(Kconfig) + $< $(silent) $(Kconfig) config: $(obj)/conf - $< --oldaskconfig $(Kconfig) + $< $(silent) --oldaskconfig $(Kconfig) nconfig: $(obj)/nconf - $< $(Kconfig) - -oldconfig: $(obj)/conf - $< --$@ $(Kconfig) + $< $(silent) $(Kconfig) silentoldconfig: $(obj)/conf $(Q)mkdir -p include/config include/generated - $< --$@ $(Kconfig) + $< $(silent) --$@ $(Kconfig) localyesconfig localmodconfig: $(obj)/streamline_config.pl $(obj)/conf $(Q)mkdir -p include/config include/generated @@ -49,18 +50,18 @@ localyesconfig localmodconfig: $(obj)/streamline_config.pl $(obj)/conf cmp -s .tmp.config .config || \ (mv -f .config .config.old.1; \ mv -f .tmp.config .config; \ - $(obj)/conf --silentoldconfig $(Kconfig); \ + $(obj)/conf $(silent) --silentoldconfig $(Kconfig); \ mv -f .config.old.1 .config.old) \ else \ mv -f .tmp.config .config; \ - $(obj)/conf --silentoldconfig $(Kconfig); \ + $(obj)/conf $(silent) --silentoldconfig $(Kconfig); \ fi $(Q)rm -f .tmp.config # Create new linux.pot file # Adjust charset to UTF-8 in .po file to accept UTF-8 in Kconfig files update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h - $(Q)echo " GEN config.pot" + $(Q)$(kecho) " GEN config.pot" $(Q)xgettext --default-domain=linux \ --add-comments --keyword=_ --keyword=N_ \ --from-code=UTF-8 \ @@ -71,65 +72,62 @@ update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h $(Q)(for i in `ls $(srctree)/arch/*/Kconfig \ $(srctree)/arch/*/um/Kconfig`; \ do \ - echo " GEN $$i"; \ + $(kecho) " GEN $$i"; \ $(obj)/kxgettext $$i \ >> $(obj)/config.pot; \ done ) - $(Q)echo " GEN linux.pot" + $(Q)$(kecho) " GEN linux.pot" $(Q)msguniq --sort-by-file --to-code=UTF-8 $(obj)/config.pot \ --output $(obj)/linux.pot $(Q)rm -f $(obj)/config.pot -PHONY += allnoconfig allyesconfig allmodconfig alldefconfig randconfig +# These targets map 1:1 to the commandline options of 'conf' +simple-targets := oldconfig allnoconfig allyesconfig allmodconfig \ + alldefconfig randconfig listnewconfig olddefconfig +PHONY += $(simple-targets) -allnoconfig allyesconfig allmodconfig alldefconfig randconfig: $(obj)/conf - $< --$@ $(Kconfig) +$(simple-targets): $(obj)/conf + $< $(silent) --$@ $(Kconfig) -PHONY += listnewconfig olddefconfig oldnoconfig savedefconfig defconfig - -listnewconfig olddefconfig: $(obj)/conf - $< --$@ $(Kconfig) +PHONY += oldnoconfig savedefconfig defconfig # oldnoconfig is an alias of olddefconfig, because people already are dependent # on its behavior(sets new symbols to their default value but not 'n') with the # counter-intuitive name. -oldnoconfig: $(obj)/conf - $< --olddefconfig $(Kconfig) +oldnoconfig: olddefconfig savedefconfig: $(obj)/conf - $< --$@=defconfig $(Kconfig) + $< $(silent) --$@=defconfig $(Kconfig) defconfig: $(obj)/conf ifeq ($(KBUILD_DEFCONFIG),) - $< --defconfig $(Kconfig) + $< $(silent) --defconfig $(Kconfig) else - @echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'" - $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG) $(Kconfig) + @$(kecho) "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'" + $(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$(KBUILD_DEFCONFIG) $(Kconfig) endif %_defconfig: $(obj)/conf - $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) + $(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) # Added for U-Boot (backward compatibility) %_config: %_defconfig @: -configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config) +configfiles=$(wildcard $(srctree)/kernel/configs/$@ $(srctree)/arch/$(SRCARCH)/configs/$@) -define mergeconfig -$(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target)) -$(if $(call configfiles,$(1)),, $(error No configuration exists for this target on this architecture)) -$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(call configfiles,$(1)) -$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig -endef +%.config: $(obj)/conf + $(if $(call configfiles),, $(error No configuration exists for this target on this architecture)) + $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m .config $(configfiles) + +$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig PHONY += kvmconfig -kvmconfig: - $(call mergeconfig,kvm_guest) +kvmconfig: kvm_guest.config + @: PHONY += tinyconfig -tinyconfig: allnoconfig - $(call mergeconfig,tiny) +tinyconfig: + $(Q)$(MAKE) -f $(srctree)/Makefile allnoconfig tiny.config # Help text used by make help help: @@ -231,7 +229,7 @@ $(obj)/.tmp_qtcheck: $(src)/Makefile # QT needs some extra effort... $(obj)/.tmp_qtcheck: - @set -e; echo " CHECK qt"; dir=""; pkg=""; \ + @set -e; $(kecho) " CHECK qt"; dir=""; pkg=""; \ if ! pkg-config --exists QtCore 2> /dev/null; then \ echo "* Unable to find the QT4 tool qmake. Trying to use QT3"; \ pkg-config --exists qt 2> /dev/null && pkg=qt; \ diff --git a/scripts/kconfig/conf.c b/scripts/kconfig/conf.c index fef75fc..6c20431 100644 --- a/scripts/kconfig/conf.c +++ b/scripts/kconfig/conf.c @@ -471,7 +471,7 @@ static struct option long_opts[] = { static void conf_usage(const char *progname) { - printf("Usage: %s [option] <kconfig-file>\n", progname); + printf("Usage: %s [-s] [option] <kconfig-file>\n", progname); printf("[option] is _one_ of the following:\n"); printf(" --listnewconfig List new options\n"); printf(" --oldaskconfig Start a new configuration using a line-oriented program\n"); @@ -501,7 +501,11 @@ int main(int ac, char **av) tty_stdio = isatty(0) && isatty(1) && isatty(2); - while ((opt = getopt_long(ac, av, "", long_opts, NULL)) != -1) { + while ((opt = getopt_long(ac, av, "s", long_opts, NULL)) != -1) { + if (opt == 's') { + conf_set_message_callback(NULL); + continue; + } input_mode = (enum input_mode)opt; switch (opt) { case silentoldconfig: diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c index 2f778df..9847ae6 100644 --- a/scripts/kconfig/confdata.c +++ b/scripts/kconfig/confdata.c @@ -16,6 +16,11 @@ #include "lkc.h" +struct conf_printer { + void (*print_symbol)(FILE *, struct symbol *, const char *, void *); + void (*print_comment)(FILE *, const char *, void *); +}; + static void conf_warning(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))); @@ -59,6 +64,7 @@ static void conf_message(const char *fmt, ...) va_start(ap, fmt); if (conf_message_callback) conf_message_callback(fmt, ap); + va_end(ap); } const char *conf_get_configname(void) diff --git a/scripts/kconfig/expr.c b/scripts/kconfig/expr.c index d662652..fb0a2a2 100644 --- a/scripts/kconfig/expr.c +++ b/scripts/kconfig/expr.c @@ -11,6 +11,12 @@ #define DEBUG_EXPR 0 +static int expr_eq(struct expr *e1, struct expr *e2); +static struct expr *expr_eliminate_yn(struct expr *e); +static struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2); +static struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2); +static void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2); + struct expr *expr_alloc_symbol(struct symbol *sym) { struct expr *e = xcalloc(1, sizeof(*e)); @@ -186,7 +192,7 @@ void expr_eliminate_eq(struct expr **ep1, struct expr **ep2) #undef e1 #undef e2 -int expr_eq(struct expr *e1, struct expr *e2) +static int expr_eq(struct expr *e1, struct expr *e2) { int res, old_count; @@ -228,7 +234,7 @@ int expr_eq(struct expr *e1, struct expr *e2) return 0; } -struct expr *expr_eliminate_yn(struct expr *e) +static struct expr *expr_eliminate_yn(struct expr *e) { struct expr *tmp; @@ -823,7 +829,7 @@ bool expr_depends_symbol(struct expr *dep, struct symbol *sym) return false; } -struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2) +static struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2) { struct expr *tmp = NULL; expr_extract_eq(E_AND, &tmp, ep1, ep2); @@ -834,7 +840,7 @@ struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2) return tmp; } -struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2) +static struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2) { struct expr *tmp = NULL; expr_extract_eq(E_OR, &tmp, ep1, ep2); @@ -845,7 +851,7 @@ struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2) return tmp; } -void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2) +static void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2) { #define e1 (*ep1) #define e2 (*ep2) @@ -976,11 +982,8 @@ tristate expr_calc_value(struct expr *e) } } -int expr_compare_type(enum expr_type t1, enum expr_type t2) +static int expr_compare_type(enum expr_type t1, enum expr_type t2) { -#if 0 - return 1; -#else if (t1 == t2) return 0; switch (t1) { @@ -1005,7 +1008,6 @@ int expr_compare_type(enum expr_type t1, enum expr_type t2) } printf("[%dgt%d?]", t1, t2); return 0; -#endif } static inline struct expr * diff --git a/scripts/kconfig/expr.h b/scripts/kconfig/expr.h index 412ea8a..a2fc96a 100644 --- a/scripts/kconfig/expr.h +++ b/scripts/kconfig/expr.h @@ -205,18 +205,13 @@ struct expr *expr_alloc_and(struct expr *e1, struct expr *e2); struct expr *expr_alloc_or(struct expr *e1, struct expr *e2); struct expr *expr_copy(const struct expr *org); void expr_free(struct expr *e); -int expr_eq(struct expr *e1, struct expr *e2); void expr_eliminate_eq(struct expr **ep1, struct expr **ep2); tristate expr_calc_value(struct expr *e); -struct expr *expr_eliminate_yn(struct expr *e); struct expr *expr_trans_bool(struct expr *e); struct expr *expr_eliminate_dups(struct expr *e); struct expr *expr_transform(struct expr *e); int expr_contains_symbol(struct expr *dep, struct symbol *sym); bool expr_depends_symbol(struct expr *dep, struct symbol *sym); -struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2); -struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2); -void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2); struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym); struct expr *expr_simplify_unmet_dep(struct expr *e1, struct expr *e2); diff --git a/scripts/kconfig/gconf.c b/scripts/kconfig/gconf.c index d0a35b2..26d208b 100644 --- a/scripts/kconfig/gconf.c +++ b/scripts/kconfig/gconf.c @@ -169,14 +169,6 @@ void init_main_window(const gchar * glade_file) style = gtk_widget_get_style(main_wnd); widget = glade_xml_get_widget(xml, "toolbar1"); -#if 0 /* Use stock Gtk icons instead */ - replace_button_icon(xml, main_wnd->window, style, - "button1", (gchar **) xpm_back); - replace_button_icon(xml, main_wnd->window, style, - "button2", (gchar **) xpm_load); - replace_button_icon(xml, main_wnd->window, style, - "button3", (gchar **) xpm_save); -#endif replace_button_icon(xml, main_wnd->window, style, "button4", (gchar **) xpm_single_view); replace_button_icon(xml, main_wnd->window, style, @@ -184,22 +176,6 @@ void init_main_window(const gchar * glade_file) replace_button_icon(xml, main_wnd->window, style, "button6", (gchar **) xpm_tree_view); -#if 0 - switch (view_mode) { - case SINGLE_VIEW: - widget = glade_xml_get_widget(xml, "button4"); - g_signal_emit_by_name(widget, "clicked"); - break; - case SPLIT_VIEW: - widget = glade_xml_get_widget(xml, "button5"); - g_signal_emit_by_name(widget, "clicked"); - break; - case FULL_VIEW: - widget = glade_xml_get_widget(xml, "button6"); - g_signal_emit_by_name(widget, "clicked"); - break; - } -#endif txtbuf = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w)); tag1 = gtk_text_buffer_create_tag(txtbuf, "mytag1", "foreground", "red", @@ -1498,9 +1474,12 @@ int main(int ac, char *av[]) case 'a': //showAll = 1; break; + case 's': + conf_set_message_callback(NULL); + break; case 'h': case '?': - printf("%s <config>\n", av[0]); + printf("%s [-s] <config>\n", av[0]); exit(0); } name = av[2]; diff --git a/scripts/kconfig/list.h b/scripts/kconfig/list.h index 685d80e..2cf23f0 100644 --- a/scripts/kconfig/list.h +++ b/scripts/kconfig/list.h @@ -34,7 +34,7 @@ struct list_head { * list_entry - get the struct for this entry * @ptr: the &struct list_head pointer. * @type: the type of the struct this is embedded in. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. */ #define list_entry(ptr, type, member) \ container_of(ptr, type, member) @@ -43,7 +43,7 @@ struct list_head { * list_for_each_entry - iterate over list of given type * @pos: the type * to use as a loop cursor. * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. */ #define list_for_each_entry(pos, head, member) \ for (pos = list_entry((head)->next, typeof(*pos), member); \ @@ -55,7 +55,7 @@ struct list_head { * @pos: the type * to use as a loop cursor. * @n: another type * to use as temporary storage * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. */ #define list_for_each_entry_safe(pos, n, head, member) \ for (pos = list_entry((head)->next, typeof(*pos), member), \ diff --git a/scripts/kconfig/lkc.h b/scripts/kconfig/lkc.h index d5daa7a..91ca126 100644 --- a/scripts/kconfig/lkc.h +++ b/scripts/kconfig/lkc.h @@ -21,9 +21,7 @@ static inline char *bind_textdomain_codeset(const char *dn, char *c) { return c; extern "C" { #endif -#define P(name,type,arg) extern type name arg #include "lkc_proto.h" -#undef P #define SRCTREE "srctree" @@ -70,9 +68,6 @@ struct kconf_id { enum symbol_type stype; }; -extern int zconfdebug; - -int zconfparse(void); void zconfdump(FILE *out); void zconf_starthelp(void); FILE *zconf_fopen(const char *name); @@ -90,11 +85,6 @@ void sym_add_change_count(int count); bool conf_set_all_new_symbols(enum conf_def_mode mode); void set_all_choice_values(struct symbol *csym); -struct conf_printer { - void (*print_symbol)(FILE *, struct symbol *, const char *, void *); - void (*print_comment)(FILE *, const char *, void *); -}; - /* confdata.c and expr.c */ static inline void xfwrite(const void *str, size_t len, size_t count, FILE *out) { @@ -113,7 +103,6 @@ void menu_add_entry(struct symbol *sym); void menu_end_entry(void); void menu_add_dep(struct expr *dep); void menu_add_visibility(struct expr *dep); -struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep); struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep); void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep); void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep); @@ -137,7 +126,6 @@ struct gstr { int max_width; }; struct gstr str_new(void); -struct gstr str_assign(const char *s); void str_free(struct gstr *gs); void str_append(struct gstr *gs, const char *s); void str_printf(struct gstr *gs, const char *fmt, ...); @@ -148,8 +136,6 @@ extern struct expr *sym_env_list; void sym_init(void); void sym_clear_all_valid(void); -void sym_set_all_changed(void); -void sym_set_changed(struct symbol *sym); struct symbol *sym_choice_default(struct symbol *sym); const char *sym_get_string_default(struct symbol *sym); struct symbol *sym_check_deps(struct symbol *sym); diff --git a/scripts/kconfig/lkc_proto.h b/scripts/kconfig/lkc_proto.h index ecdb965..d539871 100644 --- a/scripts/kconfig/lkc_proto.h +++ b/scripts/kconfig/lkc_proto.h @@ -1,57 +1,52 @@ #include <stdarg.h> /* confdata.c */ -P(conf_parse,void,(const char *name)); -P(conf_read,int,(const char *name)); -P(conf_read_simple,int,(const char *name, int)); -P(conf_write_defconfig,int,(const char *name)); -P(conf_write,int,(const char *name)); -P(conf_write_autoconf,int,(void)); -P(conf_get_changed,bool,(void)); -P(conf_set_changed_callback, void,(void (*fn)(void))); -P(conf_set_message_callback, void,(void (*fn)(const char *fmt, va_list ap))); +void conf_parse(const char *name); +int conf_read(const char *name); +int conf_read_simple(const char *name, int); +int conf_write_defconfig(const char *name); +int conf_write(const char *name); +int conf_write_autoconf(void); +bool conf_get_changed(void); +void conf_set_changed_callback(void (*fn)(void)); +void conf_set_message_callback(void (*fn)(const char *fmt, va_list ap)); /* menu.c */ -P(rootmenu,struct menu,); +extern struct menu rootmenu; -P(menu_is_empty, bool, (struct menu *menu)); -P(menu_is_visible, bool, (struct menu *menu)); -P(menu_has_prompt, bool, (struct menu *menu)); -P(menu_get_prompt,const char *,(struct menu *menu)); -P(menu_get_root_menu,struct menu *,(struct menu *menu)); -P(menu_get_parent_menu,struct menu *,(struct menu *menu)); -P(menu_has_help,bool,(struct menu *menu)); -P(menu_get_help,const char *,(struct menu *menu)); -P(get_symbol_str, void, (struct gstr *r, struct symbol *sym, struct list_head - *head)); -P(get_relations_str, struct gstr, (struct symbol **sym_arr, struct list_head - *head)); -P(menu_get_ext_help,void,(struct menu *menu, struct gstr *help)); +bool menu_is_empty(struct menu *menu); +bool menu_is_visible(struct menu *menu); +bool menu_has_prompt(struct menu *menu); +const char * menu_get_prompt(struct menu *menu); +struct menu * menu_get_root_menu(struct menu *menu); +struct menu * menu_get_parent_menu(struct menu *menu); +bool menu_has_help(struct menu *menu); +const char * menu_get_help(struct menu *menu); +struct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head); +void menu_get_ext_help(struct menu *menu, struct gstr *help); /* symbol.c */ -P(symbol_hash,struct symbol *,[SYMBOL_HASHSIZE]); +extern struct symbol * symbol_hash[SYMBOL_HASHSIZE]; -P(sym_lookup,struct symbol *,(const char *name, int flags)); -P(sym_find,struct symbol *,(const char *name)); -P(sym_expand_string_value,const char *,(const char *in)); -P(sym_escape_string_value, const char *,(const char *in)); -P(sym_re_search,struct symbol **,(const char *pattern)); -P(sym_type_name,const char *,(enum symbol_type type)); -P(sym_calc_value,void,(struct symbol *sym)); -P(sym_get_type,enum symbol_type,(struct symbol *sym)); -P(sym_tristate_within_range,bool,(struct symbol *sym,tristate tri)); -P(sym_set_tristate_value,bool,(struct symbol *sym,tristate tri)); -P(sym_toggle_tristate_value,tristate,(struct symbol *sym)); -P(sym_string_valid,bool,(struct symbol *sym, const char *newval)); -P(sym_string_within_range,bool,(struct symbol *sym, const char *str)); -P(sym_set_string_value,bool,(struct symbol *sym, const char *newval)); -P(sym_is_changable,bool,(struct symbol *sym)); -P(sym_get_choice_prop,struct property *,(struct symbol *sym)); -P(sym_get_default_prop,struct property *,(struct symbol *sym)); -P(sym_get_string_value,const char *,(struct symbol *sym)); +struct symbol * sym_lookup(const char *name, int flags); +struct symbol * sym_find(const char *name); +const char * sym_expand_string_value(const char *in); +const char * sym_escape_string_value(const char *in); +struct symbol ** sym_re_search(const char *pattern); +const char * sym_type_name(enum symbol_type type); +void sym_calc_value(struct symbol *sym); +enum symbol_type sym_get_type(struct symbol *sym); +bool sym_tristate_within_range(struct symbol *sym,tristate tri); +bool sym_set_tristate_value(struct symbol *sym,tristate tri); +tristate sym_toggle_tristate_value(struct symbol *sym); +bool sym_string_valid(struct symbol *sym, const char *newval); +bool sym_string_within_range(struct symbol *sym, const char *str); +bool sym_set_string_value(struct symbol *sym, const char *newval); +bool sym_is_changable(struct symbol *sym); +struct property * sym_get_choice_prop(struct symbol *sym); +const char * sym_get_string_value(struct symbol *sym); -P(prop_get_type_name,const char *,(enum prop_type type)); +const char * prop_get_type_name(enum prop_type type); /* expr.c */ -P(expr_compare_type,int,(enum expr_type t1, enum expr_type t2)); -P(expr_print,void,(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken)); +void expr_print(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken); diff --git a/scripts/kconfig/lxdialog/check-lxdialog.sh b/scripts/kconfig/lxdialog/check-lxdialog.sh index 9d2a4c5..5075ebf 100755 --- a/scripts/kconfig/lxdialog/check-lxdialog.sh +++ b/scripts/kconfig/lxdialog/check-lxdialog.sh @@ -21,7 +21,11 @@ ldflags() # Where is ncurses.h? ccflags() { - if [ -f /usr/include/ncursesw/curses.h ]; then + if pkg-config --cflags ncursesw 2>/dev/null; then + echo '-DCURSES_LOC="<ncurses.h>" -DNCURSES_WIDECHAR=1' + elif pkg-config --cflags ncurses 2>/dev/null; then + echo '-DCURSES_LOC="<ncurses.h>"' + elif [ -f /usr/include/ncursesw/curses.h ]; then echo '-I/usr/include/ncursesw -DCURSES_LOC="<curses.h>"' echo ' -DNCURSES_WIDECHAR=1' elif [ -f /usr/include/ncurses/ncurses.h ]; then diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c index 14cea74..315ce2c 100644 --- a/scripts/kconfig/mconf.c +++ b/scripts/kconfig/mconf.c @@ -279,6 +279,7 @@ static int child_count; static int single_menu_mode; static int show_all_options; static int save_and_exit; +static int silent; static void conf(struct menu *menu, struct menu *active_menu); static void conf_choice(struct menu *menu); @@ -330,10 +331,10 @@ static void set_subtitle(void) list_for_each_entry(sp, &trail, entries) { if (sp->text) { if (pos) { - pos->next = xcalloc(sizeof(*pos), 1); + pos->next = xcalloc(1, sizeof(*pos)); pos = pos->next; } else { - subtitles = pos = xcalloc(sizeof(*pos), 1); + subtitles = pos = xcalloc(1, sizeof(*pos)); } pos->text = sp->text; } @@ -777,10 +778,12 @@ static void conf_message_callback(const char *fmt, va_list ap) char buf[PATH_MAX+1]; vsnprintf(buf, sizeof(buf), fmt, ap); - if (save_and_exit) - printf("%s", buf); - else + if (save_and_exit) { + if (!silent) + printf("%s", buf); + } else { show_textbox(NULL, buf, 6, 60); + } } static void show_help(struct menu *menu) @@ -977,16 +980,18 @@ static int handle_exit(void) } /* fall through */ case -1: - printf(_("\n\n" - "*** End of the configuration.\n" - "*** Execute 'make' to start the build or try 'make help'." - "\n\n")); + if (!silent) + printf(_("\n\n" + "*** End of the configuration.\n" + "*** Execute 'make' to start the build or try 'make help'." + "\n\n")); res = 0; break; default: - fprintf(stderr, _("\n\n" - "Your configuration changes were NOT saved." - "\n\n")); + if (!silent) + fprintf(stderr, _("\n\n" + "Your configuration changes were NOT saved." + "\n\n")); if (res != KEY_ESC) res = 0; } @@ -1010,6 +1015,12 @@ int main(int ac, char **av) signal(SIGINT, sig_handler); + if (ac > 1 && strcmp(av[1], "-s") == 0) { + silent = 1; + /* Silence conf_read() until the real callback is set up */ + conf_set_message_callback(NULL); + av++; + } conf_parse(av[1]); conf_read(NULL); diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c index 72c9dba..b05cc3d 100644 --- a/scripts/kconfig/menu.c +++ b/scripts/kconfig/menu.c @@ -125,7 +125,7 @@ void menu_set_type(int type) sym_type_name(sym->type), sym_type_name(type)); } -struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep) +static struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep) { struct property *prop = prop_alloc(type, current_entry->sym); @@ -615,7 +615,7 @@ static struct property *get_symbol_prop(struct symbol *sym) /* * head is optional and may be NULL */ -void get_symbol_str(struct gstr *r, struct symbol *sym, +static void get_symbol_str(struct gstr *r, struct symbol *sym, struct list_head *head) { bool hit; diff --git a/scripts/kconfig/merge_config.sh b/scripts/kconfig/merge_config.sh index efa4733..ec8e203 100755 --- a/scripts/kconfig/merge_config.sh +++ b/scripts/kconfig/merge_config.sh @@ -35,7 +35,7 @@ usage() { echo " -O dir to put generated output files" } -MAKE=true +RUNMAKE=true ALLTARGET=alldefconfig WARNREDUN=false OUTPUT=. @@ -48,7 +48,7 @@ while true; do continue ;; "-m") - MAKE=false + RUNMAKE=false shift continue ;; @@ -77,9 +77,19 @@ while true; do esac done +if [ "$#" -lt 2 ] ; then + usage + exit +fi + INITFILE=$1 shift; +if [ ! -r "$INITFILE" ]; then + echo "The base file '$INITFILE' does not exist. Exit." >&2 + exit 1 +fi + MERGE_LIST=$* SED_CONFIG_EXP="s/^\(# \)\{0,1\}\(CONFIG_[a-zA-Z0-9_]*\)[= ].*/\2/p" TMP_FILE=$(mktemp ./.tmp.config.XXXXXXXXXX) @@ -93,25 +103,23 @@ for MERGE_FILE in $MERGE_LIST ; do CFG_LIST=$(sed -n "$SED_CONFIG_EXP" $MERGE_FILE) for CFG in $CFG_LIST ; do - grep -q -w $CFG $TMP_FILE - if [ $? -eq 0 ] ; then - PREV_VAL=$(grep -w $CFG $TMP_FILE) - NEW_VAL=$(grep -w $CFG $MERGE_FILE) - if [ "x$PREV_VAL" != "x$NEW_VAL" ] ; then + grep -q -w $CFG $TMP_FILE || continue + PREV_VAL=$(grep -w $CFG $TMP_FILE) + NEW_VAL=$(grep -w $CFG $MERGE_FILE) + if [ "x$PREV_VAL" != "x$NEW_VAL" ] ; then echo Value of $CFG is redefined by fragment $MERGE_FILE: echo Previous value: $PREV_VAL echo New value: $NEW_VAL echo - elif [ "$WARNREDUN" = "true" ]; then + elif [ "$WARNREDUN" = "true" ]; then echo Value of $CFG is redundant by fragment $MERGE_FILE: - fi - sed -i "/$CFG[ =]/d" $TMP_FILE fi + sed -i "/$CFG[ =]/d" $TMP_FILE done cat $MERGE_FILE >> $TMP_FILE done -if [ "$MAKE" = "false" ]; then +if [ "$RUNMAKE" = "false" ]; then cp $TMP_FILE $OUTPUT/.config echo "#" echo "# merged configuration written to $OUTPUT/.config (needs make)" diff --git a/scripts/kconfig/nconf.c b/scripts/kconfig/nconf.c index 984489e..d42d534 100644 --- a/scripts/kconfig/nconf.c +++ b/scripts/kconfig/nconf.c @@ -1482,6 +1482,11 @@ int main(int ac, char **av) bindtextdomain(PACKAGE, LOCALEDIR); textdomain(PACKAGE); + if (ac > 1 && strcmp(av[1], "-s") == 0) { + /* Silence conf_read() until the real callback is set up */ + conf_set_message_callback(NULL); + av++; + } conf_parse(av[1]); conf_read(NULL); diff --git a/scripts/kconfig/qconf.cc b/scripts/kconfig/qconf.cc index 9d3b04b..c3bb7fe 100644 --- a/scripts/kconfig/qconf.cc +++ b/scripts/kconfig/qconf.cc @@ -1746,7 +1746,7 @@ static const char *progname; static void usage(void) { - printf(_("%s <config>\n"), progname); + printf(_("%s [-s] <config>\n"), progname); exit(0); } @@ -1762,6 +1762,9 @@ int main(int ac, char** av) configApp = new QApplication(ac, av); if (ac > 1 && av[1][0] == '-') { switch (av[1][1]) { + case 's': + conf_set_message_callback(NULL); + break; case 'h': case '?': usage(); diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c index ab339eb..550e1d7 100644 --- a/scripts/kconfig/symbol.c +++ b/scripts/kconfig/symbol.c @@ -112,7 +112,7 @@ struct property *sym_get_env_prop(struct symbol *sym) return NULL; } -struct property *sym_get_default_prop(struct symbol *sym) +static struct property *sym_get_default_prop(struct symbol *sym) { struct property *prop; @@ -186,6 +186,26 @@ static void sym_validate_range(struct symbol *sym) sym->curr.val = strdup(str); } +static void sym_set_changed(struct symbol *sym) +{ + struct property *prop; + + sym->flags |= SYMBOL_CHANGED; + for (prop = sym->prop; prop; prop = prop->next) { + if (prop->menu) + prop->menu->flags |= MENU_CHANGED; + } +} + +static void sym_set_all_changed(void) +{ + struct symbol *sym; + int i; + + for_all_symbols(i, sym) + sym_set_changed(sym); +} + static void sym_calc_visibility(struct symbol *sym) { struct property *prop; @@ -451,26 +471,6 @@ void sym_clear_all_valid(void) sym_calc_value(modules_sym); } -void sym_set_changed(struct symbol *sym) -{ - struct property *prop; - - sym->flags |= SYMBOL_CHANGED; - for (prop = sym->prop; prop; prop = prop->next) { - if (prop->menu) - prop->menu->flags |= MENU_CHANGED; - } -} - -void sym_set_all_changed(void) -{ - struct symbol *sym; - int i; - - for_all_symbols(i, sym) - sym_set_changed(sym); -} - bool sym_tristate_within_range(struct symbol *sym, tristate val) { int type = sym_get_type(sym); diff --git a/scripts/kconfig/util.c b/scripts/kconfig/util.c index 94f9c83..0e76042 100644 --- a/scripts/kconfig/util.c +++ b/scripts/kconfig/util.c @@ -88,16 +88,6 @@ struct gstr str_new(void) return gs; } -/* Allocate and assign growable string */ -struct gstr str_assign(const char *s) -{ - struct gstr gs; - gs.s = strdup(s); - gs.len = strlen(s) + 1; - gs.max_width = 0; - return gs; -} - /* Free storage for growable string */ void str_free(struct gstr *gs) { diff --git a/tools/.gitignore b/tools/.gitignore index 9bc9fec..eb1a27e 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -11,7 +11,6 @@ /mkenvimage /mkimage /mkexynosspl -/mpc86x_clk /mxsboot /mksunxiboot /ncb diff --git a/tools/Makefile b/tools/Makefile index db55bcf..f673258 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -167,10 +167,6 @@ HOSTCFLAGS_md5.o := -pedantic HOSTCFLAGS_sha1.o := -pedantic HOSTCFLAGS_sha256.o := -pedantic -# Don't build by default -#hostprogs-$(CONFIG_PPC) += mpc86x_clk -#HOSTCFLAGS_mpc86x_clk.o := -pedantic - quiet_cmd_wrap = WRAP $@ cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@ diff --git a/tools/buildman/README b/tools/buildman/README index 8ecdd8f..10c7135 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -318,7 +318,7 @@ settings file to find them. To make this easier, buildman can automatically download and install toolchains from kernel.org. First list the available architectures: -$ ./tools/buildman/buildman sandbox --fetch-arch list +$ ./tools/buildman/buildman --fetch-arch list Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ @@ -329,7 +329,7 @@ sparc sparc64 tilegx x86_64 xtensa Then pick one and download it: -$ ./tools/buildman/buildman sandbox --fetch-arch or32 +$ ./tools/buildman/buildman --fetch-arch or32 Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/ Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/ diff --git a/tools/default_image.c b/tools/default_image.c index cf5c0d4..18940af 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -88,6 +88,9 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, struct image_tool_params *params) { uint32_t checksum; + char *source_date_epoch; + struct tm *time_universal; + time_t time; image_header_t * hdr = (image_header_t *)ptr; @@ -96,9 +99,25 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, sizeof(image_header_t)), sbuf->st_size - sizeof(image_header_t)); + source_date_epoch = getenv("SOURCE_DATE_EPOCH"); + if (source_date_epoch != NULL) { + time = (time_t) strtol(source_date_epoch, NULL, 10); + + time_universal = gmtime(&time); + if (time_universal == NULL) { + fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n", + __func__); + time = 0; + } else { + time = mktime(time_universal); + } + } else { + time = sbuf->st_mtime; + } + /* Build new header */ image_set_magic(hdr, IH_MAGIC); - image_set_time(hdr, sbuf->st_mtime); + image_set_time(hdr, time); image_set_size(hdr, sbuf->st_size - sizeof(image_header_t)); image_set_load(hdr, params->addr); image_set_ep(hdr, params->ep); diff --git a/tools/mpc86x_clk.c b/tools/mpc86x_clk.c deleted file mode 100644 index 9f662f7..0000000 --- a/tools/mpc86x_clk.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2003 Intracom S.A. - * Pantelis Antoniou <panto@intracom.gr> - * - * This little program makes an exhaustive search for the - * correct terms of pdf, mfi, mfn, mfd, s, dbrmo, in PLPRCR. - * The goal is to produce a gclk2 from a xin input, while respecting - * all the restrictions on their combination. - * - * Generaly you select the first row of the produced table. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <stdio.h> -#include <stdlib.h> - -#define DPREF_MIN 10000000 -#define DPREF_MAX 32000000 - -#define DPGDCK_MAX 320000000 -#define DPGDCK_MIN 160000000 - -#define S_MIN 0 -#define S_MAX 2 - -#define MFI_MIN 5 -#define MFI_MAX 15 - -#define MFN_MIN 0 -#define MFN_MAX 15 - -#define MFD_MIN 0 -#define MFD_MAX 31 - -#define MF_MIN 5 -#define MF_MAX 15 - -#define PDF_MIN 0 -#define PDF_MAX 15 - -#define GCLK2_MAX 150000000 - -static int calculate (int xin, int target_clock, - int ppm, int pdf, int mfi, int mfn, int mfd, int s, - int *dprefp, int *dpgdckp, int *jdbckp, - int *gclk2p, int *dbrmop) -{ - unsigned int dpref, dpgdck, jdbck, gclk2, t1, t2, dbrmo; - - /* valid MFI? */ - if (mfi < MFI_MIN) - return -1; - - /* valid num, denum? */ - if (mfn > 0 && mfn >= mfd) - return -1; - - dpref = xin / (pdf + 1); - - /* valid dpef? */ - if (dpref < DPREF_MIN || dpref > DPREF_MAX) - return -1; - - if (mfn == 0) { - dpgdck = (2 * mfi * xin) / (pdf + 1) ; - dbrmo = 0; - } else { - /* 5 <= mfi + (mfn / mfd + 1) <= 15 */ - t1 = mfd + 1; - t2 = mfi * t1 + mfn; - if ( MF_MIN * t1 > t2 || MF_MAX * t1 < t2) - return -1; - - dpgdck = (unsigned int)(2 * (mfi * mfd + mfi + mfn) * - (unsigned int)xin) / - ((mfd + 1) * (pdf + 1)); - - dbrmo = 10 * mfn < (mfd + 1); - } - - /* valid dpgclk? */ - if (dpgdck < DPGDCK_MIN || dpgdck > DPGDCK_MAX) - return -1; - - jdbck = dpgdck >> s; - gclk2 = jdbck / 2; - - /* valid gclk2 */ - if (gclk2 > GCLK2_MAX) - return -1; - - t1 = abs(gclk2 - target_clock); - - /* XXX max 1MHz dev. in clock */ - if (t1 > 1000000) - return -1; - - /* dev within range (XXX gclk2 scaled to avoid overflow) */ - if (t1 * 1000 > (unsigned int)ppm * (gclk2 / 1000)) - return -1; - - *dprefp = dpref; - *dpgdckp = dpgdck; - *jdbckp = jdbck; - *gclk2p = gclk2; - *dbrmop = dbrmo; - - return gclk2; -} - -int conf_clock(int xin, int target_clock, int ppm) -{ - int pdf, s, mfn, mfd, mfi; - int dpref, dpgdck, jdbck, gclk2, xout, dbrmo; - int found = 0; - - /* integer multipliers */ - for (pdf = PDF_MIN; pdf <= PDF_MAX; pdf++) { - for (mfi = MFI_MIN; mfi <= MFI_MAX; mfi++) { - for (s = 0; s <= S_MAX; s++) { - xout = calculate(xin, target_clock, - ppm, pdf, mfi, 0, 0, s, - &dpref, &dpgdck, &jdbck, - &gclk2, &dbrmo); - if (xout < 0) - continue; - - if (found == 0) { - printf("pdf mfi mfn mfd s dbrmo dpref dpgdck jdbck gclk2 exact?\n"); - printf("--- --- --- --- - ----- ----- ------ ----- ----- ------\n"); - } - - printf("%3d %3d --- --- %1d %5d %9d %9d %9d %9d%s\n", - pdf, mfi, s, dbrmo, - dpref, dpgdck, jdbck, gclk2, - gclk2 == target_clock ? " YES" : ""); - - found++; - } - } - } - - /* fractional multipliers */ - for (pdf = PDF_MIN; pdf <= PDF_MAX; pdf++) { - for (mfi = MFI_MIN; mfi <= MFI_MAX; mfi++) { - for (mfn = 1; mfn <= MFN_MAX; mfn++) { - for (mfd = 1; mfd <= MFD_MAX; mfd++) { - for (s = 0; s <= S_MAX; s++) { - xout = calculate(xin, target_clock, - ppm, pdf, mfi, mfn, mfd, s, - &dpref, &dpgdck, &jdbck, - &gclk2, &dbrmo); - if (xout < 0) - continue; - - if (found == 0) { - printf("pdf mfi mfn mfd s dbrmo dpref dpgdck jdbck gclk2 exact?\n"); - printf("--- --- --- --- - ----- ----- ------ ----- ----- ------\n"); - } - - printf("%3d %3d %3d %3d %1d %5d %9d %9d %9d %9d%s\n", - pdf, mfi, mfn, mfd, s, - dbrmo, dpref, dpgdck, jdbck, gclk2, - gclk2 == target_clock ? " YES" : ""); - - found++; - } - } - } - - } - } - - return found; -} - -int main(int argc, char *argv[]) -{ - int xin, want_gclk2, found, ppm = 100; - - if (argc < 3) { - fprintf(stderr, "usage: mpc86x_clk <xin> <want_gclk2> [ppm]\n"); - fprintf(stderr, " default ppm is 100\n"); - return 10; - } - - xin = atoi(argv[1]); - want_gclk2 = atoi(argv[2]); - if (argc >= 4) - ppm = atoi(argv[3]); - - found = conf_clock(xin, want_gclk2, ppm); - if (found <= 0) { - fprintf(stderr, "cannot produce gclk2 %d from xin %d\n", - want_gclk2, xin); - return EXIT_FAILURE; - } - - return EXIT_SUCCESS; -} diff --git a/tools/patman/README b/tools/patman/README index 27ec90a..5bd74c4 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -135,6 +135,17 @@ Similar to the above, but skip the first commit and take the next 5. This is useful if your top commit is for setting up testing. +How to install it +================= + +The most up to date version of patman can be found in the U-boot sources. +However to use it on other projects it may be more convenient to install it as +a standalone application. A distutils installer is included, this can be used +to install patman: + +$ cd tools/patman && python setup.py install + + How to add tags =============== diff --git a/tools/patman/__init__.py b/tools/patman/__init__.py new file mode 100644 index 0000000..7cbe5fa --- /dev/null +++ b/tools/patman/__init__.py @@ -0,0 +1,3 @@ +__all__ = ['checkpatch', 'command', 'commit', 'cros_subprocess', + 'get_maintainer', 'gitutil', 'patchstream', 'project', + 'series', 'settings', 'terminal', 'test'] diff --git a/tools/patman/patman.py b/tools/patman/patman.py index 6c6473e..6fe8fe0 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -14,14 +14,18 @@ import sys import unittest # Our modules -import checkpatch -import command -import gitutil -import patchstream -import project -import settings -import terminal -import test +try: + from patman import checkpatch, command, gitutil, patchstream, \ + project, settings, terminal, test +except ImportError: + import checkpatch + import command + import gitutil + import patchstream + import project + import settings + import terminal + import test parser = OptionParser() @@ -70,8 +74,11 @@ specified by tags you place in the commits. Use -n to do a dry run first.""" settings.Setup(parser, options.project, '') (options, args) = parser.parse_args() +if __name__ != "__main__": + pass + # Run our meagre tests -if options.test: +elif options.test: import doctest sys.argv = [sys.argv[0]] diff --git a/tools/patman/setup.py b/tools/patman/setup.py new file mode 100644 index 0000000..e61804f --- /dev/null +++ b/tools/patman/setup.py @@ -0,0 +1,13 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# +from distutils.core import setup +setup(name='patman', + version='1.0', + license='GPL-2.0+', + scripts=['patman'], + packages=['patman'], + package_dir={'patman': ''}, + package_data={'patman': ['README']}, + classifiers=['Environment :: Console', + 'Topic :: Software Development']) |