diff options
| -rw-r--r-- | arch/arm/dts/tegra186.dtsi | 10 | ||||
| -rw-r--r-- | doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt | 52 | ||||
| -rw-r--r-- | drivers/mailbox/tegra-hsp.c | 47 | ||||
| -rw-r--r-- | include/dt-bindings/mailbox/tegra-hsp.h | 14 | ||||
| -rw-r--r-- | include/dt-bindings/mailbox/tegra186-hsp.h | 19 |
5 files changed, 113 insertions, 29 deletions
diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index 99d4925..650feb6 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -1,7 +1,7 @@ #include "skeleton.dtsi" #include <dt-bindings/gpio/tegra186-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/mailbox/tegra-hsp.h> +#include <dt-bindings/mailbox/tegra186-hsp.h> / { compatible = "nvidia,tegra186"; @@ -45,12 +45,8 @@ compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - nvidia,num-SM = <0x8>; - nvidia,num-AS = <0x2>; - nvidia,num-SS = <0x2>; - nvidia,num-DB = <0x7>; - nvidia,num-SI = <0x8>; - #mbox-cells = <1>; + interrupt-names = "doorbell"; + #mbox-cells = <2>; }; gpio@c2f0000 { diff --git a/doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt b/doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt new file mode 100644 index 0000000..a915238 --- /dev/null +++ b/doc/device-tree-bindings/mailbox/nvidia,tegra186-hsp.txt @@ -0,0 +1,52 @@ +NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +The HSP modules are used for the processors to share resources and communicate +together. It provides a set of hardware synchronization primitives for +interprocessor communication. So the interprocessor communication (IPC) +protocols can use hardware synchronization primitives, when operating between +two processors not in an SMP relationship. + +The features that HSP supported are shared mailboxes, shared semaphores, +arbitrated semaphores and doorbells. + +Required properties: +- name : Should be hsp +- compatible + Array of strings. + one of: + - "nvidia,tegra186-hsp" +- reg : Offset and length of the register set for the device. +- interrupt-names + Array of strings. + Contains a list of names for the interrupts described by the interrupt + property. May contain the following entries, in any order: + - "doorbell" + Users of this binding MUST look up entries in the interrupt property + by name, using this interrupt-names property to do so. +- interrupts + Array of interrupt specifiers. + Must contain one entry per entry in the interrupt-names property, + in a matching order. +- #mbox-cells : Should be 2. + +The mbox specifier of the "mboxes" property in the client node should +contain two data. The first one should be the HSP type and the second +one should be the ID that the client is going to use. Those information +can be found in the following file. + +- <dt-bindings/mailbox/tegra186-hsp.h>. + +Example: + +hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "doorbell"; + #mbox-cells = <2>; +}; + +client { + ... + mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_XXX>; +}; diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 5c781a5..3d0362d 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -8,7 +8,19 @@ #include <asm/io.h> #include <dm.h> #include <mailbox-uclass.h> -#include <dt-bindings/mailbox/tegra-hsp.h> +#include <dt-bindings/mailbox/tegra186-hsp.h> + +#define TEGRA_HSP_INT_DIMENSIONING 0x380 +#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16 +#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12 +#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8 +#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4 +#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0 +#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf #define TEGRA_HSP_DB_REG_TRIGGER 0x0 #define TEGRA_HSP_DB_REG_ENABLE 0x4 @@ -51,7 +63,7 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val, static int tegra_hsp_db_id(ulong chan_id) { switch (chan_id) { - case TEGRA_HSP_MASTER_BPMP: + case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP: return TEGRA_HSP_DB_ID_BPMP; default: debug("Invalid channel ID\n"); @@ -59,6 +71,21 @@ static int tegra_hsp_db_id(ulong chan_id) } } +static int tegra_hsp_of_xlate(struct mbox_chan *chan, + struct fdtdec_phandle_args *args) +{ + debug("%s(chan=%p)\n", __func__, chan); + + if (args->args_count != 2) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + chan->id = (args->args[0] << 16) | args->args[1]; + + return 0; +} + static int tegra_hsp_request(struct mbox_chan *chan) { int db_id; @@ -121,6 +148,7 @@ static int tegra_hsp_bind(struct udevice *dev) static int tegra_hsp_probe(struct udevice *dev) { struct tegra_hsp *thsp = dev_get_priv(dev); + u32 val; int nr_sm, nr_ss, nr_as; debug("%s(dev=%p)\n", __func__, dev); @@ -129,12 +157,14 @@ static int tegra_hsp_probe(struct udevice *dev) if (thsp->regs == FDT_ADDR_T_NONE) return -ENODEV; - nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM", - 0); - nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS", - 0); - nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS", - 0); + val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING); + nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NSM_MASK; + nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NSS_MASK; + nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NAS_MASK; + thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16; return 0; @@ -146,6 +176,7 @@ static const struct udevice_id tegra_hsp_ids[] = { }; struct mbox_ops tegra_hsp_mbox_ops = { + .of_xlate = tegra_hsp_of_xlate, .request = tegra_hsp_request, .free = tegra_hsp_free, .send = tegra_hsp_send, diff --git a/include/dt-bindings/mailbox/tegra-hsp.h b/include/dt-bindings/mailbox/tegra-hsp.h deleted file mode 100644 index e8c23fa..0000000 --- a/include/dt-bindings/mailbox/tegra-hsp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra186-hsp. - * - * The number with TEGRA_HSP_MASTER prefix indicates the bit that is - * associated with a master ID in the doorbell registers. - */ - -#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H -#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H - -#define TEGRA_HSP_MASTER_CCPLEX 17 -#define TEGRA_HSP_MASTER_BPMP 19 - -#endif diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h new file mode 100644 index 0000000..b486432 --- /dev/null +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -0,0 +1,19 @@ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + * + * The number with HSP_DB_MASTER prefix indicates the bit that is + * associated with a master ID in the doorbell registers. + */ + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H + +#define HSP_MBOX_TYPE_DB 0x0 +#define HSP_MBOX_TYPE_SM 0x1 +#define HSP_MBOX_TYPE_SS 0x2 +#define HSP_MBOX_TYPE_AS 0x3 + +#define HSP_DB_MASTER_CCPLEX 17 +#define HSP_DB_MASTER_BPMP 19 + +#endif |