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-rw-r--r--CHANGELOG9
-rw-r--r--cpu/mpc5xxx/fec.c4
-rw-r--r--cpu/mpc5xxx/pci_mpc5200.c4
-rw-r--r--cpu/mpc5xxx/start.S16
-rw-r--r--cpu/mpc824x/interrupts.c11
-rw-r--r--include/asm-ppc/processor.h32
-rw-r--r--include/configs/IceCube.h1
7 files changed, 53 insertions, 24 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 20c6cf2..93e7c7f 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,15 @@
Changes for U-Boot 1.0.0:
======================================================================
+* Patch by Gleb Natapov, 14 Sep 2003:
+ enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+ "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+ fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
* Patch by llandre, 11 Sep 2003:
update configuration for PPChameleonEVB board
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 06dd56f..634698b 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -427,7 +427,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
/*
* Set the auto-negotiation advertisement register bits
*/
+#ifndef CONFIG_FEC_10MBIT
miiphy_write(phyAddr, 0x4, 0x01e1);
+#else
+ miiphy_write(phyAddr, 0x4, 0x061);/* Advertise 10FDX */
+#endif
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index a890a6d..a54c5f4 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -48,9 +48,11 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
{
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
+ udelay(10);
*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+ udelay(10);
return 0;
}
@@ -59,9 +61,11 @@ static int mpc5200_write_config_dword(struct pci_controller *hose,
{
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
+ udelay(10);
out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+ udelay(10);
return 0;
}
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 216c1c8..0557909 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -382,6 +382,14 @@ init_5xxx_core:
mtspr DBAT2L, r0
mtspr DBAT3U, r0
mtspr DBAT3L, r0
+ mtspr DBAT4U, r0
+ mtspr DBAT4L, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT5L, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT6L, r0
+ mtspr DBAT7U, r0
+ mtspr DBAT7L, r0
mtspr IBAT0U, r0
mtspr IBAT0L, r0
mtspr IBAT1U, r0
@@ -390,6 +398,14 @@ init_5xxx_core:
mtspr IBAT2L, r0
mtspr IBAT3U, r0
mtspr IBAT3L, r0
+ mtspr IBAT4U, r0
+ mtspr IBAT4L, r0
+ mtspr IBAT5U, r0
+ mtspr IBAT5L, r0
+ mtspr IBAT6U, r0
+ mtspr IBAT6L, r0
+ mtspr IBAT7U, r0
+ mtspr IBAT7L, r0
SYNC
/* invalidate all tlb's */
diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c
index 753575f..825857b 100644
--- a/cpu/mpc824x/interrupts.c
+++ b/cpu/mpc824x/interrupts.c
@@ -27,6 +27,7 @@
#include <asm/processor.h>
#include <asm/pci_io.h>
#include <commproc.h>
+#include <watchdog.h>
#include "drivers/epic.h"
/****************************************************************************/
@@ -149,15 +150,9 @@ void timer_interrupt (struct pt_regs *regs)
timestamp++;
-#if defined(CONFIG_WATCHDOG)
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
if ((timestamp % (CFG_HZ / 2)) == 0) {
-#if defined(CONFIG_OXC)
- {
- extern void oxc_wdt_reset (void);
-
- oxc_wdt_reset ();
- }
-#endif
+ WATCHDOG_RESET ();
}
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index feaff94..73a8a55 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -95,14 +95,14 @@
#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
-#define SPRN_DBAT4L 0x238 /* Data BAT 4 Lower Register */
-#define SPRN_DBAT4U 0x239 /* Data BAT 4 Upper Register */
-#define SPRN_DBAT5L 0x23A /* Data BAT 5 Lower Register */
-#define SPRN_DBAT5U 0x23B /* Data BAT 5 Upper Register */
-#define SPRN_DBAT6L 0x23C /* Data BAT 6 Lower Register */
-#define SPRN_DBAT6U 0x23D /* Data BAT 6 Upper Register */
-#define SPRN_DBAT7L 0x23E /* Data BAT 7 Lower Register */
-#define SPRN_DBAT7U 0x23F /* Data BAT 7 Lower Register */
+#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
@@ -203,14 +203,14 @@
#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
-#define SPRN_IBAT4L 0x230 /* Instruction BAT 4 Lower Register */
-#define SPRN_IBAT4U 0x231 /* Instruction BAT 4 Upper Register */
-#define SPRN_IBAT5L 0x232 /* Instruction BAT 5 Lower Register */
-#define SPRN_IBAT5U 0x233 /* Instruction BAT 5 Upper Register */
-#define SPRN_IBAT6L 0x234 /* Instruction BAT 6 Lower Register */
-#define SPRN_IBAT6U 0x235 /* Instruction BAT 6 Upper Register */
-#define SPRN_IBAT7L 0x236 /* Instruction BAT 7 Lower Register */
-#define SPRN_IBAT7U 0x237 /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
#define ICCR_NOCACHE 0 /* Noncacheable */
#define ICCR_CACHE 1 /* Cacheable */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index c2c398c..64fc6fe 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -179,6 +179,7 @@
* Ethernet configuration
*/
#define CONFIG_MPC5XXX_FEC 1
+#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
/*
* GPIO configuration
generated by cgit v1.1 at 2024-11-22 16:24:37 +0000