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| author | Ye Li <ye.li@nxp.com> | 2016-10-12 15:45:49 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-10-12 15:45:49 +0800 |
| commit | 92946cba62d23e6ace547a90a0debb1916fa0add (patch) | |
| tree | 5da2474011a0aee68511b52aa7f4d069c82680e9 /post | |
| parent | f6c75d019afb2b4a59b10649b95bde8b7723a30b (diff) | |
| download | u-boot-imx-92946cba62d23e6ace547a90a0debb1916fa0add.zip u-boot-imx-92946cba62d23e6ace547a90a0debb1916fa0add.tar.gz u-boot-imx-92946cba62d23e6ace547a90a0debb1916fa0add.tar.bz2 | |
MLK-13330 mx6sll_arm2: Update LPDDR3 script to v2.2
Changes from v1.2 to v2.2:
Version 2.2
-Issue a Precharge-All command prior to the MRW Reset command.
-setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0
-setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1
Version 2.1
-Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results
-setmem /32 0x021B0848 = 0x3C3A3C3C // [MMDC_MPRDDLCTL]
-setmem /32 0x021B0850 = 0x24293625 // [MMDC_MPWRDLCTL]
Version 1.2.1
-Fix a typo. setmem /32 0x020E052C = 0x00000030
-Fix a typo. setmem /32 0x021B0800 = 0xA1390003
File:
http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1
Test:
Overnight memtester passed on two i.MX6SLL LPDDR3 ARM2 boards.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'post')
0 files changed, 0 insertions, 0 deletions