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authorSergei Poselenov <sposelenov@emcraft.com>2007-07-05 08:17:37 +0200
committerStefan Roese <sr@denx.de>2007-07-05 08:17:37 +0200
commitb44896215a09c60fa40cae906f7ed207bbc2c492 (patch)
treef3c10a507342d083a17dbd7f98e5c662a8f2432e /post/cpu/mpc8xx
parentf780b83316d9af1f61d71cc88b1917b387b9b995 (diff)
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Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Diffstat (limited to 'post/cpu/mpc8xx')
-rw-r--r--post/cpu/mpc8xx/Makefile2
-rw-r--r--post/cpu/mpc8xx/cache.c81
2 files changed, 82 insertions, 1 deletions
diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile
index 9dd3f0f..f871cba 100644
--- a/post/cpu/mpc8xx/Makefile
+++ b/post/cpu/mpc8xx/Makefile
@@ -24,6 +24,6 @@
LIB = libpostmpc8xx.a
AOBJS = cache_8xx.o
-COBJS = ether.o spr.o uart.o usb.o watchdog.o
+COBJS = cache.o ether.o spr.o uart.o usb.o watchdog.o
include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/mpc8xx/cache.c b/post/cpu/mpc8xx/cache.c
new file mode 100644
index 0000000..501465c
--- /dev/null
+++ b/post/cpu/mpc8xx/cache.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Cache test
+ *
+ * This test verifies the CPU data and instruction cache using
+ * several test scenarios.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CFG_POST_CACHE
+
+#define CACHE_POST_SIZE 1024
+
+extern int cache_post_test1 (char *, unsigned int);
+extern int cache_post_test2 (char *, unsigned int);
+extern int cache_post_test3 (char *, unsigned int);
+extern int cache_post_test4 (char *, unsigned int);
+extern int cache_post_test5 (void);
+extern int cache_post_test6 (void);
+
+int cache_post_test (int flags)
+{
+ int ints = disable_interrupts ();
+ int res = 0;
+ static char ta[CACHE_POST_SIZE + 0xf];
+ char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf);
+
+ WATCHDOG_RESET ();
+ if (res == 0)
+ res = cache_post_test1 (testarea, CACHE_POST_SIZE);
+ WATCHDOG_RESET ();
+ if (res == 0)
+ res = cache_post_test2 (testarea, CACHE_POST_SIZE);
+ WATCHDOG_RESET ();
+ if (res == 0)
+ res = cache_post_test3 (testarea, CACHE_POST_SIZE);
+ WATCHDOG_RESET ();
+ if (res == 0)
+ res = cache_post_test4 (testarea, CACHE_POST_SIZE);
+ WATCHDOG_RESET ();
+ if (res == 0)
+ res = cache_post_test5 ();
+ WATCHDOG_RESET ();
+ if (res == 0)
+ res = cache_post_test6 ();
+
+ WATCHDOG_RESET ();
+ if (ints)
+ enable_interrupts ();
+ return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_CACHE */
+#endif /* CONFIG_POST */