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| author | Stephen Warren <swarren@nvidia.com> | 2015-10-05 16:58:52 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-11-12 09:21:04 -0700 |
| commit | dfa551e49c072b9f4e1b0486a4091cd80733733b (patch) | |
| tree | 05c8b22da5b2a9a4f7251948d98cdecb0b0886ec /post/Makefile | |
| parent | 038be18fd95aa6283eafb85ceabc0b880976424b (diff) | |
| download | u-boot-imx-dfa551e49c072b9f4e1b0486a4091cd80733733b.zip u-boot-imx-dfa551e49c072b9f4e1b0486a4091cd80733733b.tar.gz u-boot-imx-dfa551e49c072b9f4e1b0486a4091cd80733733b.tar.bz2 | |
ARM: tegra210: implement PLLE init procedure from TRM
Implement the procedure that the TRM mandates to initialize PLLREFE and
PLLE. This makes the PLL actually lock.
Note that this section of the TRM is being cleaned up to remove some
confusion. The set of register accesses in this patch should be final,
although the step numbers/descriptions might still change.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'post/Makefile')
0 files changed, 0 insertions, 0 deletions