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authorScott Wood <scottwood@freescale.com>2009-01-20 11:56:11 -0600
committerKim Phillips <kim.phillips@freescale.com>2009-01-21 18:43:57 -0600
commit6677876181cc8772bca8a372479a500d160f3993 (patch)
tree47919055c6d6de9e7a0a84c922a13d0161c394b2 /nand_spl
parent8b34557c546e5e9f34ebf83c93413dad973d93df (diff)
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83xx: Use the proper sequence for updating IMMR.
This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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