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| author | Scott Wood <scottwood@freescale.com> | 2009-01-20 11:56:11 -0600 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-01-21 18:43:57 -0600 |
| commit | 6677876181cc8772bca8a372479a500d160f3993 (patch) | |
| tree | 47919055c6d6de9e7a0a84c922a13d0161c394b2 /nand_spl | |
| parent | 8b34557c546e5e9f34ebf83c93413dad973d93df (diff) | |
| download | u-boot-imx-6677876181cc8772bca8a372479a500d160f3993.zip u-boot-imx-6677876181cc8772bca8a372479a500d160f3993.tar.gz u-boot-imx-6677876181cc8772bca8a372479a500d160f3993.tar.bz2 | |
83xx: Use the proper sequence for updating IMMR.
This ensures that subsequent accesses properly hit the new window.
The dcbi during the NAND loop was accidentally working around this;
it's no longer necessary, as the cache is not enabled.
Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'nand_spl')
0 files changed, 0 insertions, 0 deletions