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authorHung-ying Tyan <tyanh@chromium.org>2013-05-15 18:27:30 +0800
committerTom Rini <trini@ti.com>2013-06-26 10:13:24 -0400
commitf3424c554c572761f35b00988deb8ed35d1870e3 (patch)
treebd4d66a127bb045d1c4968fde86d3c25e1f0ddb1 /include
parent78764a4e11dd40005ba2b36848de407070ccc1a7 (diff)
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cros: exynos: add SPI support for cros_ec
This patch adds SPI support for carrying out the cros_ec protocol. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r--include/spi.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/include/spi.h b/include/spi.h
index 1638b50..e8e6544 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -247,4 +247,20 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
return ret < 0 ? ret : din[1];
}
+/**
+ * Set up a SPI slave for a particular device tree node
+ *
+ * This calls spi_setup_slave() with the correct bus number. Call
+ * spi_free_slave() to free it later.
+ *
+ * @param blob Device tree blob
+ * @param node SPI peripheral node to use
+ * @param cs Chip select to use
+ * @param max_hz Maximum SCK rate in Hz (0 for default)
+ * @param mode Clock polarity, clock phase and other parameters
+ * @return pointer to new spi_slave structure
+ */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
+ unsigned int cs, unsigned int max_hz, unsigned int mode);
+
#endif /* _SPI_H_ */