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authorWolfgang Denk <wd@denx.de>2009-12-15 23:38:34 +0100
committerWolfgang Denk <wd@denx.de>2009-12-15 23:38:34 +0100
commitbb3bcfa2426cc6a0aecec7270e3ee67ca843a125 (patch)
tree0314e3d8e8d9e4d568a496fca27db33d66e68bb4 /include
parenta200a7c04d89853d2a1395b96d8ca5e3dd754551 (diff)
parent4b142febff71eabdb7ddbb125c7b583b24ddc434 (diff)
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Merge branch 'next' of ../next
Diffstat (limited to 'include')
-rw-r--r--include/4xx_i2c.h38
-rw-r--r--include/asm-arm/arch-a320/a320.h35
-rw-r--r--include/asm-arm/arch-a320/ftpmu010.h146
-rw-r--r--include/asm-arm/arch-a320/ftsdmc020.h103
-rw-r--r--include/asm-arm/arch-a320/ftsmc020.h79
-rw-r--r--include/asm-arm/arch-a320/fttmr010.h73
-rw-r--r--include/asm-arm/arch-davinci/hardware.h237
-rw-r--r--include/asm-arm/arch-davinci/i2c_defs.h5
-rw-r--r--include/asm-arm/arch-omap24xx/i2c.h53
-rw-r--r--include/asm-arm/arch-omap3/cpu.h1
-rw-r--r--include/asm-arm/arch-omap3/i2c.h49
-rw-r--r--include/asm-arm/arch-omap3/mem.h102
-rw-r--r--include/asm-arm/arch-s3c24x0/s3c2400.h (renamed from include/s3c2400.h)18
-rw-r--r--include/asm-arm/arch-s3c24x0/s3c2410.h (renamed from include/s3c2410.h)19
-rw-r--r--include/asm-arm/arch-s3c24x0/s3c24x0.h652
-rw-r--r--include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h27
-rw-r--r--include/asm-arm/arch-s3c64xx/s3c6400.h (renamed from include/s3c6400.h)0
-rw-r--r--include/asm-arm/arch-s3c64xx/s3c64x0.h (renamed from include/s3c64x0.h)0
-rw-r--r--include/asm-arm/mach-types.h1976
-rw-r--r--include/asm-blackfin/delay.h2
-rw-r--r--include/asm-i386/interrupt.h27
-rw-r--r--include/asm-i386/u-boot-i386.h23
-rw-r--r--include/asm-ppc/4xx_pci.h8
-rw-r--r--include/common.h15
-rw-r--r--include/configs/ASH405.h2
-rw-r--r--include/configs/CMS700.h2
-rw-r--r--include/configs/DU440.h5
-rw-r--r--include/configs/HH405.h2
-rw-r--r--include/configs/HUB405.h2
-rw-r--r--include/configs/IDS8247.h2
-rw-r--r--include/configs/MPC8313ERDB.h1
-rw-r--r--include/configs/MPC8315ERDB.h1
-rw-r--r--include/configs/MPC8360ERDK.h1
-rw-r--r--include/configs/MPC837XEMDS.h3
-rw-r--r--include/configs/MPC837XERDB.h3
-rw-r--r--include/configs/MPC8536DS.h4
-rw-r--r--include/configs/MPC8540ADS.h3
-rw-r--r--include/configs/MPC8541CDS.h3
-rw-r--r--include/configs/MPC8544DS.h3
-rw-r--r--include/configs/MPC8548CDS.h3
-rw-r--r--include/configs/MPC8555CDS.h3
-rw-r--r--include/configs/MPC8560ADS.h3
-rw-r--r--include/configs/MPC8568MDS.h3
-rw-r--r--include/configs/MPC8569MDS.h3
-rw-r--r--include/configs/MPC8572DS.h3
-rw-r--r--include/configs/MPC8610HPCD.h3
-rw-r--r--include/configs/MPC8641HPCN.h4
-rw-r--r--include/configs/P1_P2_RDB.h3
-rw-r--r--include/configs/P2020DS.h3
-rw-r--r--include/configs/PLU405.h22
-rw-r--r--include/configs/PMC440.h5
-rw-r--r--include/configs/PPChameleonEVB.h2
-rw-r--r--include/configs/SIMPC8313.h1
-rw-r--r--include/configs/TQM8272.h2
-rw-r--r--include/configs/TQM85xx.h2
-rw-r--r--include/configs/VCMA9.h7
-rw-r--r--include/configs/VOH405.h2
-rw-r--r--include/configs/WUH405.h2
-rw-r--r--include/configs/XPEDITE5170.h3
-rw-r--r--include/configs/XPEDITE5200.h3
-rw-r--r--include/configs/XPEDITE5370.h3
-rw-r--r--include/configs/a320evb.h222
-rw-r--r--include/configs/acadia.h2
-rw-r--r--include/configs/afeb9260.h1
-rw-r--r--include/configs/alpr.h2
-rw-r--r--include/configs/apollon.h4
-rw-r--r--include/configs/aria.h2
-rw-r--r--include/configs/at91cap9adk.h1
-rw-r--r--include/configs/at91sam9260ek.h1
-rw-r--r--include/configs/at91sam9261ek.h1
-rw-r--r--include/configs/at91sam9263ek.h1
-rw-r--r--include/configs/at91sam9m10g45ek.h2
-rw-r--r--include/configs/at91sam9rlek.h1
-rw-r--r--include/configs/bfin_adi_common.h3
-rw-r--r--include/configs/cpu9260.h1
-rw-r--r--include/configs/da830evm.h243
-rw-r--r--include/configs/davinci_dm355evm.h1
-rw-r--r--include/configs/davinci_dm355leopard.h1
-rw-r--r--include/configs/davinci_dm365evm.h1
-rw-r--r--include/configs/davinci_dm6467evm.h1
-rw-r--r--include/configs/davinci_dvevm.h1
-rw-r--r--include/configs/davinci_schmoogie.h1
-rw-r--r--include/configs/davinci_sffsdr.h1
-rw-r--r--include/configs/davinci_sonata.h1
-rw-r--r--include/configs/delta.h2
-rw-r--r--include/configs/devkit8000.h5
-rw-r--r--include/configs/eNET.h8
-rw-r--r--include/configs/imx27lite.h1
-rw-r--r--include/configs/ipek01.h408
-rw-r--r--include/configs/katmai.h9
-rw-r--r--include/configs/keymile-common.h2
-rw-r--r--include/configs/kilauea.h2
-rw-r--r--include/configs/korat.h2
-rw-r--r--include/configs/lwmon5.h12
-rw-r--r--include/configs/manroland/common.h3
-rw-r--r--include/configs/mecp5123.h2
-rw-r--r--include/configs/meesc.h1
-rw-r--r--include/configs/mpc5121ads.h2
-rw-r--r--include/configs/netstar.h2
-rw-r--r--include/configs/nhk8815.h1
-rw-r--r--include/configs/omap3_beagle.h5
-rw-r--r--include/configs/omap3_evm.h5
-rw-r--r--include/configs/omap3_overo.h5
-rw-r--r--include/configs/omap3_pandora.h6
-rw-r--r--include/configs/omap3_sdp3430.h3
-rw-r--r--include/configs/omap3_zoom1.h6
-rw-r--r--include/configs/omap3_zoom2.h5
-rw-r--r--include/configs/openrd_base.h1
-rw-r--r--include/configs/pdnb3.h1
-rw-r--r--include/configs/pm9261.h3
-rw-r--r--include/configs/pm9263.h1
-rw-r--r--include/configs/quad100hd.h1
-rw-r--r--include/configs/rd6281a.h1
-rw-r--r--include/configs/sbc2410x.h7
-rw-r--r--include/configs/sbc35_a9g20.h1
-rw-r--r--include/configs/sbc8641d.h3
-rw-r--r--include/configs/sc3.h7
-rw-r--r--include/configs/sc520_cdp.h2
-rw-r--r--include/configs/sc520_spunk.h2
-rw-r--r--include/configs/sequoia.h1
-rw-r--r--include/configs/sheevaplug.h1
-rw-r--r--include/configs/smdk2400.h7
-rw-r--r--include/configs/smdk2410.h7
-rw-r--r--include/configs/smdk6400.h4
-rw-r--r--include/configs/smdkc100.h2
-rw-r--r--include/configs/socrates.h9
-rw-r--r--include/configs/tny_a9260.h1
-rw-r--r--include/configs/trab.h9
-rw-r--r--include/configs/vct.h6
-rw-r--r--include/configs/yucca.h8
-rw-r--r--include/configs/zylonite.h2
-rw-r--r--include/exports.h2
-rw-r--r--include/image.h1
-rw-r--r--include/linux/lzo.h4
-rw-r--r--include/linux/mtd/mtd-abi.h2
-rw-r--r--include/linux/mtd/nand.h2
-rw-r--r--include/linux/mtd/onenand.h16
-rw-r--r--include/linux/mtd/onenand_regs.h18
-rw-r--r--include/linux/mtd/partitions.h4
-rw-r--r--include/mb862xx.h5
-rw-r--r--include/onenand_uboot.h10
-rw-r--r--include/pca9564.h50
-rw-r--r--include/ppc405.h19
-rw-r--r--include/ppc440.h22
-rw-r--r--include/ppc4xx.h6
-rw-r--r--include/s3c24x0.h656
146 files changed, 4626 insertions, 1080 deletions
diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h
index 070657f..0c6c926 100644
--- a/include/4xx_i2c.h
+++ b/include/4xx_i2c.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -52,22 +52,26 @@
#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
#endif
-#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
-#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
-#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+struct ppc4xx_i2c {
+ u8 mdbuf;
+ u8 res1;
+ u8 sdbuf;
+ u8 res2;
+ u8 lmadr;
+ u8 hmadr;
+ u8 cntl;
+ u8 mdcntl;
+ u8 sts;
+ u8 extsts;
+ u8 lsadr;
+ u8 hsadr;
+ u8 clkdiv;
+ u8 intrmsk;
+ u8 xfrcnt;
+ u8 xtcntlss;
+ u8 directcntl;
+ u8 intr;
+};
/* MDCNTL Register Bit definition */
#define IIC_MDCNTL_HSCL 0x01
diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h
new file mode 100644
index 0000000..5c0a097
--- /dev/null
+++ b/include/asm-arm/arch-a320/a320.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __A320_H
+#define __A320_H
+
+/*
+ * Hardware register bases
+ */
+#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
+#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
+#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
+#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
+#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
+#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
+#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
+
+#endif /* __A320_H */
+
diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h
new file mode 100644
index 0000000..8ef7a37
--- /dev/null
+++ b/include/asm-arm/arch-a320/ftpmu010.h
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU010_H
+#define __FTPMU010_H
+
+struct ftpmu010 {
+ unsigned int IDNMBR0; /* 0x00 */
+ unsigned int reserved0; /* 0x04 */
+ unsigned int OSCC; /* 0x08 */
+ unsigned int PMODE; /* 0x0C */
+ unsigned int PMCR; /* 0x10 */
+ unsigned int PED; /* 0x14 */
+ unsigned int PEDSR; /* 0x18 */
+ unsigned int reserved1; /* 0x1C */
+ unsigned int PMSR; /* 0x20 */
+ unsigned int PGSR; /* 0x24 */
+ unsigned int MFPSR; /* 0x28 */
+ unsigned int MISC; /* 0x2C */
+ unsigned int PDLLCR0; /* 0x30 */
+ unsigned int PDLLCR1; /* 0x34 */
+ unsigned int AHBMCLKOFF; /* 0x38 */
+ unsigned int APBMCLKOFF; /* 0x3C */
+ unsigned int DCSRCR0; /* 0x40 */
+ unsigned int DCSRCR1; /* 0x44 */
+ unsigned int DCSRCR2; /* 0x48 */
+ unsigned int SDRAMHTC; /* 0x4C */
+ unsigned int PSPR0; /* 0x50 */
+ unsigned int PSPR1; /* 0x54 */
+ unsigned int PSPR2; /* 0x58 */
+ unsigned int PSPR3; /* 0x5C */
+ unsigned int PSPR4; /* 0x60 */
+ unsigned int PSPR5; /* 0x64 */
+ unsigned int PSPR6; /* 0x68 */
+ unsigned int PSPR7; /* 0x6C */
+ unsigned int PSPR8; /* 0x70 */
+ unsigned int PSPR9; /* 0x74 */
+ unsigned int PSPR10; /* 0x78 */
+ unsigned int PSPR11; /* 0x7C */
+ unsigned int PSPR12; /* 0x80 */
+ unsigned int PSPR13; /* 0x84 */
+ unsigned int PSPR14; /* 0x88 */
+ unsigned int PSPR15; /* 0x8C */
+ unsigned int AHBDMA_RACCS; /* 0x90 */
+ unsigned int reserved2; /* 0x94 */
+ unsigned int reserved3; /* 0x98 */
+ unsigned int JSS; /* 0x9C */
+ unsigned int CFC_RACC; /* 0xA0 */
+ unsigned int SSP1_RACC; /* 0xA4 */
+ unsigned int UART1TX_RACC; /* 0xA8 */
+ unsigned int UART1RX_RACC; /* 0xAC */
+ unsigned int UART2TX_RACC; /* 0xB0 */
+ unsigned int UART2RX_RACC; /* 0xB4 */
+ unsigned int SDC_RACC; /* 0xB8 */
+ unsigned int I2SAC97_RACC; /* 0xBC */
+ unsigned int IRDATX_RACC; /* 0xC0 */
+ unsigned int reserved4; /* 0xC4 */
+ unsigned int USBD_RACC; /* 0xC8 */
+ unsigned int IRDARX_RACC; /* 0xCC */
+ unsigned int IRDA_RACC; /* 0xD0 */
+ unsigned int ED0_RACC; /* 0xD4 */
+ unsigned int ED1_RACC; /* 0xD8 */
+};
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU010_ID_A320A 0x03200000
+#define FTPMU010_ID_A320C 0x03200010
+#define FTPMU010_ID_A320D 0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
+#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
+#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
+
+#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
+#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
+#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
+#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
+#define FTPMU010_PMODE_FCS (1 << 2)
+#define FTPMU010_PMODE_TURBO (1 << 1)
+#define FTPMU010_PMODE_SLEEP (1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU010_PMSR_SMR (1 << 10)
+
+#define FTPMU010_PMSR_RDH (1 << 2)
+#define FTPMU010_PMSR_PH (1 << 1)
+#define FTPMU010_PMSR_CKEHLOW (1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
+#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
+
+/*
+ * PLL/DLL Control Register 0
+ */
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
+#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
+#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
+#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
+#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
+#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
+#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
+#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
+
+#endif /* __FTPMU010_H */
diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h
new file mode 100644
index 0000000..0699772
--- /dev/null
+++ b/include/asm-arm/arch-a320/ftsdmc020.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC020_H
+#define __FTSDMC020_H
+
+#define FTSDMC020_OFFSET_TP0 0x00
+#define FTSDMC020_OFFSET_TP1 0x04
+#define FTSDMC020_OFFSET_CR 0x08
+#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
+#define FTSDMC020_OFFSET_BANK1_BSR 0x10
+#define FTSDMC020_OFFSET_BANK2_BSR 0x14
+#define FTSDMC020_OFFSET_BANK3_BSR 0x18
+#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
+#define FTSDMC020_OFFSET_BANK5_BSR 0x20
+#define FTSDMC020_OFFSET_BANK6_BSR 0x24
+#define FTSDMC020_OFFSET_BANK7_BSR 0x28
+#define FTSDMC020_OFFSET_ACR 0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
+#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
+#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
+#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
+#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
+#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
+#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC020_CR_SREF (1 << 0)
+#define FTSDMC020_CR_PWDN (1 << 1)
+#define FTSDMC020_CR_ISMR (1 << 2)
+#define FTSDMC020_CR_IREF (1 << 3)
+#define FTSDMC020_CR_IPREC (1 << 4)
+#define FTSDMC020_CR_REFTYPE (1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC020_BANK_ENABLE (1 << 28)
+
+#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
+
+#define FTSDMC020_BANK_DDW_X4 (0 << 12)
+#define FTSDMC020_BANK_DDW_X8 (1 << 12)
+#define FTSDMC020_BANK_DDW_X16 (2 << 12)
+#define FTSDMC020_BANK_DDW_X32 (3 << 12)
+
+#define FTSDMC020_BANK_DSZ_16M (0 << 8)
+#define FTSDMC020_BANK_DSZ_64M (1 << 8)
+#define FTSDMC020_BANK_DSZ_128M (2 << 8)
+#define FTSDMC020_BANK_DSZ_256M (3 << 8)
+
+#define FTSDMC020_BANK_MBW_8 (0 << 4)
+#define FTSDMC020_BANK_MBW_16 (1 << 4)
+#define FTSDMC020_BANK_MBW_32 (2 << 4)
+
+#define FTSDMC020_BANK_SIZE_1M 0x0
+#define FTSDMC020_BANK_SIZE_2M 0x1
+#define FTSDMC020_BANK_SIZE_4M 0x2
+#define FTSDMC020_BANK_SIZE_8M 0x3
+#define FTSDMC020_BANK_SIZE_16M 0x4
+#define FTSDMC020_BANK_SIZE_32M 0x5
+#define FTSDMC020_BANK_SIZE_64M 0x6
+#define FTSDMC020_BANK_SIZE_128M 0x7
+#define FTSDMC020_BANK_SIZE_256M 0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
+#define FTSDMC020_ACR_TOE (1 << 8)
+
+#endif /* __FTSDMC020_H */
diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h
new file mode 100644
index 0000000..95d9500
--- /dev/null
+++ b/include/asm-arm/arch-a320/ftsmc020.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC020_H
+#define __FTSMC020_H
+
+#ifndef __ASSEMBLY__
+
+struct ftsmc020 {
+ struct {
+ unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
+ unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
+ } bank[4];
+ unsigned int pad[8]; /* 0x20 - 0x3c */
+ unsigned int ssr; /* 0x40 */
+};
+
+void ftsmc020_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC020_BANK_ENABLE (1 << 28)
+#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
+
+#define FTSMC020_BANK_WPROT (1 << 11)
+
+#define FTSMC020_BANK_SIZE_32K (0xb << 4)
+#define FTSMC020_BANK_SIZE_64K (0xc << 4)
+#define FTSMC020_BANK_SIZE_128K (0xd << 4)
+#define FTSMC020_BANK_SIZE_256K (0xe << 4)
+#define FTSMC020_BANK_SIZE_512K (0xf << 4)
+#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
+#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
+#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
+#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
+#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
+#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
+
+#define FTSMC020_BANK_MBW_8 (0x0 << 0)
+#define FTSMC020_BANK_MBW_16 (0x1 << 0)
+#define FTSMC020_BANK_MBW_32 (0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
+#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
+#define FTSMC020_TPR_RBE (1 << 20)
+#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
+#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
+#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
+#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
+#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
+#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
+#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
+
+#endif /* __FTSMC020_H */
diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h
new file mode 100644
index 0000000..72abcb3
--- /dev/null
+++ b/include/asm-arm/arch-a320/fttmr010.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR010_H
+#define __FTTMR010_H
+
+struct fttmr010 {
+ unsigned int timer1_counter; /* 0x00 */
+ unsigned int timer1_load; /* 0x04 */
+ unsigned int timer1_match1; /* 0x08 */
+ unsigned int timer1_match2; /* 0x0c */
+ unsigned int timer2_counter; /* 0x10 */
+ unsigned int timer2_load; /* 0x14 */
+ unsigned int timer2_match1; /* 0x18 */
+ unsigned int timer2_match2; /* 0x1c */
+ unsigned int timer3_counter; /* 0x20 */
+ unsigned int timer3_load; /* 0x24 */
+ unsigned int timer3_match1; /* 0x28 */
+ unsigned int timer3_match2; /* 0x2c */
+ unsigned int cr; /* 0x30 */
+ unsigned int interrupt_state; /* 0x34 */
+ unsigned int interrupt_mask; /* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR010_TM3_UPDOWN (1 << 11)
+#define FTTMR010_TM2_UPDOWN (1 << 10)
+#define FTTMR010_TM1_UPDOWN (1 << 9)
+#define FTTMR010_TM3_OFENABLE (1 << 8)
+#define FTTMR010_TM3_CLOCK (1 << 7)
+#define FTTMR010_TM3_ENABLE (1 << 6)
+#define FTTMR010_TM2_OFENABLE (1 << 5)
+#define FTTMR010_TM2_CLOCK (1 << 4)
+#define FTTMR010_TM2_ENABLE (1 << 3)
+#define FTTMR010_TM1_OFENABLE (1 << 2)
+#define FTTMR010_TM1_CLOCK (1 << 1)
+#define FTTMR010_TM1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR010_TM3_OVERFLOW (1 << 8)
+#define FTTMR010_TM3_MATCH2 (1 << 7)
+#define FTTMR010_TM3_MATCH1 (1 << 6)
+#define FTTMR010_TM2_OVERFLOW (1 << 5)
+#define FTTMR010_TM2_MATCH2 (1 << 4)
+#define FTTMR010_TM2_MATCH1 (1 << 3)
+#define FTTMR010_TM1_OVERFLOW (1 << 2)
+#define FTTMR010_TM1_MATCH2 (1 << 1)
+#define FTTMR010_TM1_MATCH1 (1 << 0)
+
+#endif /* __FTTMR010_H */
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index acf12ea..81cc8ab 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -49,6 +49,8 @@ typedef volatile unsigned int * dv_reg_p;
* on other DaVinci chips. Double check them before you try
* using the addresses ... or PSC module identifiers, etc.
*/
+#ifndef CONFIG_SOC_DA8XX
+
#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
@@ -116,10 +118,46 @@ typedef volatile unsigned int * dv_reg_p;
#endif
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE 0x01c42000
+#define DAVINCI_UART1_BASE 0x01d0c000
+#define DAVINCI_UART2_BASE 0x01d0d000
+#define DAVINCI_I2C0_BASE 0x01c22000
+#define DAVINCI_I2C1_BASE 0x01e28000
+#define DAVINCI_TIMER0_BASE 0x01c20000
+#define DAVINCI_TIMER1_BASE 0x01c21000
+#define DAVINCI_WDOG_BASE 0x01c21000
+#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
+#define DAVINCI_PSC0_BASE 0x01c10000
+#define DAVINCI_PSC1_BASE 0x01e27000
+#define DAVINCI_SPI0_BASE 0x01c41000
+#define DAVINCI_USB_OTG_BASE 0x01e00000
+#define DAVINCI_SPI1_BASE 0x01e12000
+#define DAVINCI_GPIO_BASE 0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
+#define DAVINCI_INTC_BASE 0xfffee000
+#define DAVINCI_BOOTCFG_BASE 0x01c14000
+
+#endif /* CONFIG_SOC_DA8XX */
+
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
+#ifndef CONFIG_SOC_DA8XX
+
#define DAVINCI_LPSC_VPSSMSTR 0
#define DAVINCI_LPSC_VPSSSLV 1
#define DAVINCI_LPSC_TPCC 2
@@ -166,6 +204,52 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DM646X_LPSC_UART0 26
#define DAVINCI_DM646X_LPSC_I2C 31
+#else /* CONFIG_SOC_DA8XX */
+
+enum davinci_lpsc_ids {
+ DAVINCI_LPSC_TPCC = 0,
+ DAVINCI_LPSC_TPTC0,
+ DAVINCI_LPSC_TPTC1,
+ DAVINCI_LPSC_AEMIF,
+ DAVINCI_LPSC_SPI0,
+ DAVINCI_LPSC_MMC_SD,
+ DAVINCI_LPSC_AINTC,
+ DAVINCI_LPSC_ARM_RAM_ROM,
+ DAVINCI_LPSC_SECCTL_KEYMGR,
+ DAVINCI_LPSC_UART0,
+ DAVINCI_LPSC_SCR0,
+ DAVINCI_LPSC_SCR1,
+ DAVINCI_LPSC_SCR2,
+ DAVINCI_LPSC_DMAX,
+ DAVINCI_LPSC_ARM,
+ DAVINCI_LPSC_GEM,
+ /* for LPSCs in PSC1, offset from 32 for differentiation */
+ DAVINCI_LPSC_PSC1_BASE = 32,
+ DAVINCI_LPSC_USB11,
+ DAVINCI_LPSC_USB20,
+ DAVINCI_LPSC_GPIO,
+ DAVINCI_LPSC_UHPI,
+ DAVINCI_LPSC_EMAC,
+ DAVINCI_LPSC_DDR_EMIF,
+ DAVINCI_LPSC_McASP0,
+ DAVINCI_LPSC_McASP1,
+ DAVINCI_LPSC_McASP2,
+ DAVINCI_LPSC_SPI1,
+ DAVINCI_LPSC_I2C1,
+ DAVINCI_LPSC_UART1,
+ DAVINCI_LPSC_UART2,
+ DAVINCI_LPSC_LCDC,
+ DAVINCI_LPSC_ePWM,
+ DAVINCI_LPSC_eCAP,
+ DAVINCI_LPSC_eQEP,
+ DAVINCI_LPSC_SCR_P0,
+ DAVINCI_LPSC_SCR_P1,
+ DAVINCI_LPSC_CR_P3,
+ DAVINCI_LPSC_L3_CBA_RAM
+};
+
+#endif /* CONFIG_SOC_DA8XX */
+
void lpsc_on(unsigned int id);
void dsp_on(void);
@@ -174,6 +258,8 @@ void davinci_enable_emac(void);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);
+#ifndef CONFIG_SOC_DA8XX
+
/* Some PSC defines */
#define PSC_CHP_SHRTSW (0x01c40038)
#define PSC_GBLCTL (0x01c41010)
@@ -194,6 +280,39 @@ void davinci_errata_workarounds(void);
#define PSC_SILVER_BULLET (0x01c41a20)
+#else /* CONFIG_SOC_DA8XX */
+
+#define PSC_PSC0_MODULE_ID_CNT 16
+#define PSC_PSC1_MODULE_ID_CNT 32
+
+struct davinci_psc_regs {
+ dv_reg revid;
+ dv_reg rsvd0[71];
+ dv_reg ptcmd;
+ dv_reg rsvd1;
+ dv_reg ptstat;
+ dv_reg rsvd2[437];
+ union {
+ struct {
+ dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
+ dv_reg rsvd3[112];
+ dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
+ } psc0;
+ struct {
+ dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
+ dv_reg rsvd3[96];
+ dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
+ } psc1;
+ };
+};
+
+#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
+#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#ifndef CONFIG_SOC_DA8XX
+
/* Miscellania... */
#define VBPR (0x20000020)
@@ -206,4 +325,122 @@ void davinci_errata_workarounds(void);
#define PINMUX3 0x01c4000c
#define PINMUX4 0x01c40010
+#else /* CONFIG_SOC_DA8XX */
+
+struct davinci_pllc_regs {
+ dv_reg revid;
+ dv_reg rsvd1[56];
+ dv_reg rstype;
+ dv_reg rsvd2[6];
+ dv_reg pllctl;
+ dv_reg ocsel;
+ dv_reg rsvd3[2];
+ dv_reg pllm;
+ dv_reg prediv;
+ dv_reg plldiv1;
+ dv_reg plldiv2;
+ dv_reg plldiv3;
+ dv_reg oscdiv;
+ dv_reg postdiv;
+ dv_reg rsvd4[3];
+ dv_reg pllcmd;
+ dv_reg pllstat;
+ dv_reg alnctl;
+ dv_reg dchange;
+ dv_reg cken;
+ dv_reg ckstat;
+ dv_reg systat;
+ dv_reg rsvd5[3];
+ dv_reg plldiv4;
+ dv_reg plldiv5;
+ dv_reg plldiv6;
+ dv_reg plldiv7;
+ dv_reg rsvd6[32];
+ dv_reg emucnt0;
+ dv_reg emucnt1;
+};
+
+#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define DAVINCI_PLLC_DIV_MASK 0x1f
+
+/* Clock IDs */
+enum davinci_clk_ids {
+ DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART2_CLKID = 2,
+ DAVINCI_MDIO_CLKID = 4,
+ DAVINCI_ARM_CLKID = 6,
+ DAVINCI_PLLM_CLKID = 0xff,
+ DAVINCI_PLLC_CLKID = 0x100,
+ DAVINCI_AUXCLK_CLKID = 0x101
+};
+
+int clk_get(enum davinci_clk_ids id);
+
+/* Boot config */
+struct davinci_syscfg_regs {
+ dv_reg revid;
+ dv_reg rsvd[71];
+ dv_reg pinmux[20];
+ dv_reg suspsrc;
+ dv_reg chipsig;
+ dv_reg chipsig_clr;
+ dv_reg cfgchip0;
+ dv_reg cfgchip1;
+ dv_reg cfgchip2;
+ dv_reg cfgchip3;
+ dv_reg cfgchip4;
+};
+
+#define davinci_syscfg_regs \
+ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+
+/* Emulation suspend bits */
+#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
+#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
+
+/* Interrupt controller */
+struct davinci_aintc_regs {
+ dv_reg revid;
+ dv_reg cr;
+ dv_reg dummy0[2];
+ dv_reg ger;
+ dv_reg dummy1[219];
+ dv_reg ecr1;
+ dv_reg ecr2;
+ dv_reg ecr3;
+ dv_reg dummy2[1117];
+ dv_reg hier;
+};
+
+#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
+
+struct davinci_uart_ctrl_regs {
+ dv_reg revid1;
+ dv_reg revid2;
+ dv_reg pwremu_mgmt;
+ dv_reg mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
+
+#define davinci_uart0_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
+#define davinci_uart1_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
+#define davinci_uart2_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
+#endif /* CONFIG_SOC_DA8XX */
+
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h
index 2e902e1..24cd268 100644
--- a/include/asm-arm/arch-davinci/i2c_defs.h
+++ b/include/asm-arm/arch-davinci/i2c_defs.h
@@ -28,7 +28,11 @@
#define I2C_WRITE 0
#define I2C_READ 1
+#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
+#else
+#define I2C_BASE 0x01c22000
+#endif
#define I2C_OA (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
@@ -88,6 +92,7 @@
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
+#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h
index 44db7a2..19046aa 100644
--- a/include/asm-arm/arch-omap24xx/i2c.h
+++ b/include/asm-arm/arch-omap24xx/i2c.h
@@ -23,24 +23,45 @@
#ifndef _OMAP24XX_I2C_H_
#define _OMAP24XX_I2C_H_
-#define I2C_BASE 0x48070000
+#define I2C_BASE1 0x48070000
#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */
-#define I2C_REV (I2C_BASE + 0x00)
-#define I2C_IE (I2C_BASE + 0x04)
-#define I2C_STAT (I2C_BASE + 0x08)
-#define I2C_IV (I2C_BASE + 0x0c)
-#define I2C_BUF (I2C_BASE + 0x14)
-#define I2C_CNT (I2C_BASE + 0x18)
-#define I2C_DATA (I2C_BASE + 0x1c)
-#define I2C_SYSC (I2C_BASE + 0x20)
-#define I2C_CON (I2C_BASE + 0x24)
-#define I2C_OA (I2C_BASE + 0x28)
-#define I2C_SA (I2C_BASE + 0x2c)
-#define I2C_PSC (I2C_BASE + 0x30)
-#define I2C_SCLL (I2C_BASE + 0x34)
-#define I2C_SCLH (I2C_BASE + 0x38)
-#define I2C_SYSTEST (I2C_BASE + 0x3c)
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short rev; /* 0x00 */
+ unsigned short res1;
+ unsigned short ie; /* 0x04 */
+ unsigned short res2;
+ unsigned short stat; /* 0x08 */
+ unsigned short res3;
+ unsigned short iv; /* 0x0C */
+ unsigned short res4[3];
+ unsigned short buf; /* 0x14 */
+ unsigned short res5;
+ unsigned short cnt; /* 0x18 */
+ unsigned short res6;
+ unsigned short data; /* 0x1C */
+ unsigned short res7;
+ unsigned short sysc; /* 0x20 */
+ unsigned short res8;
+ unsigned short con; /* 0x24 */
+ unsigned short res9;
+ unsigned short oa; /* 0x28 */
+ unsigned short res10;
+ unsigned short sa; /* 0x2C */
+ unsigned short res11;
+ unsigned short psc; /* 0x30 */
+ unsigned short res12;
+ unsigned short scll; /* 0x34 */
+ unsigned short res13;
+ unsigned short sclh; /* 0x38 */
+ unsigned short res14;
+ unsigned short systest; /* 0x3c */
+ unsigned short res15;
+};
+
+#define I2C_BUS_MAX 2
/* I2C masks */
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index 8ab2e39..e51c4f3 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -222,6 +222,7 @@ struct sdrc {
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
+#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)
diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h
index 8b339cc..490e03b 100644
--- a/include/asm-arm/arch-omap3/i2c.h
+++ b/include/asm-arm/arch-omap3/i2c.h
@@ -25,21 +25,40 @@
#define I2C_DEFAULT_BASE I2C_BASE1
-#define I2C_REV (I2C_DEFAULT_BASE + 0x00)
-#define I2C_IE (I2C_DEFAULT_BASE + 0x04)
-#define I2C_STAT (I2C_DEFAULT_BASE + 0x08)
-#define I2C_IV (I2C_DEFAULT_BASE + 0x0c)
-#define I2C_BUF (I2C_DEFAULT_BASE + 0x14)
-#define I2C_CNT (I2C_DEFAULT_BASE + 0x18)
-#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c)
-#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20)
-#define I2C_CON (I2C_DEFAULT_BASE + 0x24)
-#define I2C_OA (I2C_DEFAULT_BASE + 0x28)
-#define I2C_SA (I2C_DEFAULT_BASE + 0x2c)
-#define I2C_PSC (I2C_DEFAULT_BASE + 0x30)
-#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34)
-#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38)
-#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c)
+struct i2c {
+ unsigned short rev; /* 0x00 */
+ unsigned short res1;
+ unsigned short ie; /* 0x04 */
+ unsigned short res2;
+ unsigned short stat; /* 0x08 */
+ unsigned short res3;
+ unsigned short iv; /* 0x0C */
+ unsigned short res4[3];
+ unsigned short buf; /* 0x14 */
+ unsigned short res5;
+ unsigned short cnt; /* 0x18 */
+ unsigned short res6;
+ unsigned short data; /* 0x1C */
+ unsigned short res7;
+ unsigned short sysc; /* 0x20 */
+ unsigned short res8;
+ unsigned short con; /* 0x24 */
+ unsigned short res9;
+ unsigned short oa; /* 0x28 */
+ unsigned short res10;
+ unsigned short sa; /* 0x2C */
+ unsigned short res11;
+ unsigned short psc; /* 0x30 */
+ unsigned short res12;
+ unsigned short scll; /* 0x34 */
+ unsigned short res13;
+ unsigned short sclh; /* 0x38 */
+ unsigned short res14;
+ unsigned short systest; /* 0x3c */
+ unsigned short res15;
+};
+
+#define I2C_BUS_MAX 3
/* I2C masks */
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 5b9ac75..9439758 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -40,11 +40,8 @@ enum {
#define EARLY_INIT 1
/* Slower full frequency range default timings for x32 operation*/
-#define SDP_SDRC_SHARING 0x00000100
-#define SDP_SDRC_MR_0_SDR 0x00000031
-
-/* optimized timings good for current shipping parts */
-#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDRC_SHARING 0x00000100
+#define SDRC_MR_0_SDR 0x00000031
#define DLL_OFFSET 0
#define DLL_WRITEDDRCLKX2DIS 1
@@ -71,29 +68,78 @@ enum {
* TCKE = 2
* XSR = 120/6 = 20
*/
-#define TDAL_165 6
-#define TDPL_165 3
-#define TRRD_165 2
-#define TRCD_165 3
-#define TRP_165 3
-#define TRAS_165 7
-#define TRC_165 10
-#define TRFC_165 21
-#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
- (TRAS_165 << 18) | (TRP_165 << 15) | \
- (TRCD_165 << 12) | (TRRD_165 << 9) | \
- (TDPL_165 << 6) | (TDAL_165))
-
-#define TWTR_165 1
-#define TCKE_165 1
-#define TXP_165 5
-#define XSR_165 23
-#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
- (TXP_165 << 8) | (TWTR_165 << 16))
-
-#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
-#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
+#define INFINEON_TDAL_165 6
+#define INFINEON_TDPL_165 3
+#define INFINEON_TRRD_165 2
+#define INFINEON_TRCD_165 3
+#define INFINEON_TRP_165 3
+#define INFINEON_TRAS_165 7
+#define INFINEON_TRC_165 10
+#define INFINEON_TRFC_165 12
+#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
+ (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
+ (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
+ (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
+ (INFINEON_TDAL_165))
+
+#define INFINEON_TWTR_165 1
+#define INFINEON_TCKE_165 2
+#define INFINEON_TXP_165 2
+#define INFINEON_XSR_165 20
+#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
+ (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
+ (INFINEON_TWTR_165 << 16))
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 18/6 = 3
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 125/6 = 21
+ * ACTIMB
+ * TWTR = 1
+ * TCKE = 1
+ * TXSR = 138/6 = 23
+ * TXP = 25/6 = 4.1 ~5
+ */
+#define MICRON_TDAL_165 6
+#define MICRON_TDPL_165 3
+#define MICRON_TRRD_165 2
+#define MICRON_TRCD_165 3
+#define MICRON_TRP_165 3
+#define MICRON_TRAS_165 7
+#define MICRON_TRC_165 10
+#define MICRON_TRFC_165 21
+#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
+ (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
+ (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
+ (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
+ (MICRON_TDAL_165))
+
+#define MICRON_TWTR_165 1
+#define MICRON_TCKE_165 1
+#define MICRON_XSR_165 23
+#define MICRON_TXP_165 5
+#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
+ (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
+ (MICRON_TWTR_165 << 16))
+
+#ifdef CONFIG_OMAP3_INFINEON_DDR
+#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#endif
+#ifdef CONFIG_OMAP3_MICRON_DDR
+#define V_ACTIMA_165 MICRON_V_ACTIMA_165
+#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#endif
+
+#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
+#error "Please choose the right DDR type in config header"
+#endif
/*
* GPMC settings -
diff --git a/include/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h
index 062259d..2678be1 100644
--- a/include/s3c2400.h
+++ b/include/asm-arm/arch-s3c24x0/s3c2400.h
@@ -60,74 +60,90 @@ enum s3c24x0_uarts_nr {
#define S3C2400_MMC_BASE 0x15A00000
/* include common stuff */
-#include <s3c24x0.h>
+#include <asm/arch/s3c24x0.h>
static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
+
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
+
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
+
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
+
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
+
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
+
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
+
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
+
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
+
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
+
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
+
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
+
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
+
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
+
static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
{
return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
}
+
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
+
static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
{
return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
diff --git a/include/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h
index 03b33b4..0543fe1 100644
--- a/include/s3c2410.h
+++ b/include/asm-arm/arch-s3c24x0/s3c2410.h
@@ -66,78 +66,95 @@ enum s3c24x0_uarts_nr {
/* include common stuff */
-#include <s3c24x0.h>
+#include <asm/arch/s3c24x0.h>
static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
+
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
+
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
+
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
+
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
+
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
+
static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
{
return (struct s3c2410_nand *)S3C2410_NAND_BASE;
}
+
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
+
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
+
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
+
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
+
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
+
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
+
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
+
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
+
static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
{
return (struct s3c2410_adc *)S3C2410_ADC_BASE;
}
+
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
+
static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
{
return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h
new file mode 100644
index 0000000..15f53dd
--- /dev/null
+++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h
@@ -0,0 +1,652 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c24x0.h
+ * Version : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C24X0 SoC
+ ************************************************/
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+/* Memory controller (see manual chapter 5) */
+struct s3c24x0_memctl {
+ u32 BWSCON;
+ u32 BANKCON[8];
+ u32 REFRESH;
+ u32 BANKSIZE;
+ u32 MRSRB6;
+ u32 MRSRB7;
+};
+
+
+/* USB HOST (see manual chapter 12) */
+struct s3c24x0_usb_host {
+ u32 HcRevision;
+ u32 HcControl;
+ u32 HcCommonStatus;
+ u32 HcInterruptStatus;
+ u32 HcInterruptEnable;
+ u32 HcInterruptDisable;
+ u32 HcHCCA;
+ u32 HcPeriodCuttendED;
+ u32 HcControlHeadED;
+ u32 HcControlCurrentED;
+ u32 HcBulkHeadED;
+ u32 HcBuldCurrentED;
+ u32 HcDoneHead;
+ u32 HcRmInterval;
+ u32 HcFmRemaining;
+ u32 HcFmNumber;
+ u32 HcPeriodicStart;
+ u32 HcLSThreshold;
+ u32 HcRhDescriptorA;
+ u32 HcRhDescriptorB;
+ u32 HcRhStatus;
+ u32 HcRhPortStatus1;
+ u32 HcRhPortStatus2;
+};
+
+
+/* INTERRUPT (see manual chapter 14) */
+struct s3c24x0_interrupt {
+ u32 SRCPND;
+ u32 INTMOD;
+ u32 INTMSK;
+ u32 PRIORITY;
+ u32 INTPND;
+ u32 INTOFFSET;
+#ifdef CONFIG_S3C2410
+ u32 SUBSRCPND;
+ u32 INTSUBMSK;
+#endif
+};
+
+
+/* DMAS (see manual chapter 8) */
+struct s3c24x0_dma {
+ u32 DISRC;
+#ifdef CONFIG_S3C2410
+ u32 DISRCC;
+#endif
+ u32 DIDST;
+#ifdef CONFIG_S3C2410
+ u32 DIDSTC;
+#endif
+ u32 DCON;
+ u32 DSTAT;
+ u32 DCSRC;
+ u32 DCDST;
+ u32 DMASKTRIG;
+#ifdef CONFIG_S3C2400
+ u32 res[1];
+#endif
+#ifdef CONFIG_S3C2410
+ u32 res[7];
+#endif
+};
+
+struct s3c24x0_dmas {
+ struct s3c24x0_dma dma[4];
+};
+
+
+/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
+/* (see S3C2410 manual chapter 7) */
+struct s3c24x0_clock_power {
+ u32 LOCKTIME;
+ u32 MPLLCON;
+ u32 UPLLCON;
+ u32 CLKCON;
+ u32 CLKSLOW;
+ u32 CLKDIVN;
+};
+
+
+/* LCD CONTROLLER (see manual chapter 15) */
+struct s3c24x0_lcd {
+ u32 LCDCON1;
+ u32 LCDCON2;
+ u32 LCDCON3;
+ u32 LCDCON4;
+ u32 LCDCON5;
+ u32 LCDSADDR1;
+ u32 LCDSADDR2;
+ u32 LCDSADDR3;
+ u32 REDLUT;
+ u32 GREENLUT;
+ u32 BLUELUT;
+ u32 res[8];
+ u32 DITHMODE;
+ u32 TPAL;
+#ifdef CONFIG_S3C2410
+ u32 LCDINTPND;
+ u32 LCDSRCPND;
+ u32 LCDINTMSK;
+ u32 LPCSEL;
+#endif
+};
+
+
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+struct s3c2410_nand {
+ u32 NFCONF;
+ u32 NFCMD;
+ u32 NFADDR;
+ u32 NFDATA;
+ u32 NFSTAT;
+ u32 NFECC;
+};
+
+
+/* UART (see manual chapter 11) */
+struct s3c24x0_uart {
+ u32 ULCON;
+ u32 UCON;
+ u32 UFCON;
+ u32 UMCON;
+ u32 UTRSTAT;
+ u32 UERSTAT;
+ u32 UFSTAT;
+ u32 UMSTAT;
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 UTXH;
+ u8 res2[3];
+ u8 URXH;
+#else /* Little Endian */
+ u8 UTXH;
+ u8 res1[3];
+ u8 URXH;
+ u8 res2[3];
+#endif
+ u32 UBRDIV;
+};
+
+
+/* PWM TIMER (see manual chapter 10) */
+struct s3c24x0_timer {
+ u32 TCNTB;
+ u32 TCMPB;
+ u32 TCNTO;
+};
+
+struct s3c24x0_timers {
+ u32 TCFG0;
+ u32 TCFG1;
+ u32 TCON;
+ struct s3c24x0_timer ch[4];
+ u32 TCNTB4;
+ u32 TCNTO4;
+};
+
+
+/* USB DEVICE (see manual chapter 13) */
+struct s3c24x0_usb_dev_fifos {
+#ifdef __BIG_ENDIAN
+ u8 res[3];
+ u8 EP_FIFO_REG;
+#else /* little endian */
+ u8 EP_FIFO_REG;
+ u8 res[3];
+#endif
+};
+
+struct s3c24x0_usb_dev_dmas {
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 EP_DMA_CON;
+ u8 res2[3];
+ u8 EP_DMA_UNIT;
+ u8 res3[3];
+ u8 EP_DMA_FIFO;
+ u8 res4[3];
+ u8 EP_DMA_TTC_L;
+ u8 res5[3];
+ u8 EP_DMA_TTC_M;
+ u8 res6[3];
+ u8 EP_DMA_TTC_H;
+#else /* little endian */
+ u8 EP_DMA_CON;
+ u8 res1[3];
+ u8 EP_DMA_UNIT;
+ u8 res2[3];
+ u8 EP_DMA_FIFO;
+ u8 res3[3];
+ u8 EP_DMA_TTC_L;
+ u8 res4[3];
+ u8 EP_DMA_TTC_M;
+ u8 res5[3];
+ u8 EP_DMA_TTC_H;
+ u8 res6[3];
+#endif
+};
+
+struct s3c24x0_usb_device {
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 FUNC_ADDR_REG;
+ u8 res2[3];
+ u8 PWR_REG;
+ u8 res3[3];
+ u8 EP_INT_REG;
+ u8 res4[15];
+ u8 USB_INT_REG;
+ u8 res5[3];
+ u8 EP_INT_EN_REG;
+ u8 res6[15];
+ u8 USB_INT_EN_REG;
+ u8 res7[3];
+ u8 FRAME_NUM1_REG;
+ u8 res8[3];
+ u8 FRAME_NUM2_REG;
+ u8 res9[3];
+ u8 INDEX_REG;
+ u8 res10[7];
+ u8 MAXP_REG;
+ u8 res11[3];
+ u8 EP0_CSR_IN_CSR1_REG;
+ u8 res12[3];
+ u8 IN_CSR2_REG;
+ u8 res13[7];
+ u8 OUT_CSR1_REG;
+ u8 res14[3];
+ u8 OUT_CSR2_REG;
+ u8 res15[3];
+ u8 OUT_FIFO_CNT1_REG;
+ u8 res16[3];
+ u8 OUT_FIFO_CNT2_REG;
+#else /* little endian */
+ u8 FUNC_ADDR_REG;
+ u8 res1[3];
+ u8 PWR_REG;
+ u8 res2[3];
+ u8 EP_INT_REG;
+ u8 res3[15];
+ u8 USB_INT_REG;
+ u8 res4[3];
+ u8 EP_INT_EN_REG;
+ u8 res5[15];
+ u8 USB_INT_EN_REG;
+ u8 res6[3];
+ u8 FRAME_NUM1_REG;
+ u8 res7[3];
+ u8 FRAME_NUM2_REG;
+ u8 res8[3];
+ u8 INDEX_REG;
+ u8 res9[7];
+ u8 MAXP_REG;
+ u8 res10[7];
+ u8 EP0_CSR_IN_CSR1_REG;
+ u8 res11[3];
+ u8 IN_CSR2_REG;
+ u8 res12[3];
+ u8 OUT_CSR1_REG;
+ u8 res13[7];
+ u8 OUT_CSR2_REG;
+ u8 res14[3];
+ u8 OUT_FIFO_CNT1_REG;
+ u8 res15[3];
+ u8 OUT_FIFO_CNT2_REG;
+ u8 res16[3];
+#endif /* __BIG_ENDIAN */
+ struct s3c24x0_usb_dev_fifos fifo[5];
+ struct s3c24x0_usb_dev_dmas dma[5];
+};
+
+
+/* WATCH DOG TIMER (see manual chapter 18) */
+struct s3c24x0_watchdog {
+ u32 WTCON;
+ u32 WTDAT;
+ u32 WTCNT;
+};
+
+
+/* IIC (see manual chapter 20) */
+struct s3c24x0_i2c {
+ u32 IICCON;
+ u32 IICSTAT;
+ u32 IICADD;
+ u32 IICDS;
+};
+
+
+/* IIS (see manual chapter 21) */
+struct s3c24x0_i2s {
+#ifdef __BIG_ENDIAN
+ u16 res1;
+ u16 IISCON;
+ u16 res2;
+ u16 IISMOD;
+ u16 res3;
+ u16 IISPSR;
+ u16 res4;
+ u16 IISFCON;
+ u16 res5;
+ u16 IISFIFO;
+#else /* little endian */
+ u16 IISCON;
+ u16 res1;
+ u16 IISMOD;
+ u16 res2;
+ u16 IISPSR;
+ u16 res3;
+ u16 IISFCON;
+ u16 res4;
+ u16 IISFIFO;
+ u16 res5;
+#endif
+};
+
+
+/* I/O PORT (see manual chapter 9) */
+struct s3c24x0_gpio {
+#ifdef CONFIG_S3C2400
+ u32 PACON;
+ u32 PADAT;
+
+ u32 PBCON;
+ u32 PBDAT;
+ u32 PBUP;
+
+ u32 PCCON;
+ u32 PCDAT;
+ u32 PCUP;
+
+ u32 PDCON;
+ u32 PDDAT;
+ u32 PDUP;
+
+ u32 PECON;
+ u32 PEDAT;
+ u32 PEUP;
+
+ u32 PFCON;
+ u32 PFDAT;
+ u32 PFUP;
+
+ u32 PGCON;
+ u32 PGDAT;
+ u32 PGUP;
+
+ u32 OPENCR;
+
+ u32 MISCCR;
+ u32 EXTINT;
+#endif
+#ifdef CONFIG_S3C2410
+ u32 GPACON;
+ u32 GPADAT;
+ u32 res1[2];
+ u32 GPBCON;
+ u32 GPBDAT;
+ u32 GPBUP;
+ u32 res2;
+ u32 GPCCON;
+ u32 GPCDAT;
+ u32 GPCUP;
+ u32 res3;
+ u32 GPDCON;
+ u32 GPDDAT;
+ u32 GPDUP;
+ u32 res4;
+ u32 GPECON;
+ u32 GPEDAT;
+ u32 GPEUP;
+ u32 res5;
+ u32 GPFCON;
+ u32 GPFDAT;
+ u32 GPFUP;
+ u32 res6;
+ u32 GPGCON;
+ u32 GPGDAT;
+ u32 GPGUP;
+ u32 res7;
+ u32 GPHCON;
+ u32 GPHDAT;
+ u32 GPHUP;
+ u32 res8;
+
+ u32 MISCCR;
+ u32 DCLKCON;
+ u32 EXTINT0;
+ u32 EXTINT1;
+ u32 EXTINT2;
+ u32 EINTFLT0;
+ u32 EINTFLT1;
+ u32 EINTFLT2;
+ u32 EINTFLT3;
+ u32 EINTMASK;
+ u32 EINTPEND;
+ u32 GSTATUS0;
+ u32 GSTATUS1;
+ u32 GSTATUS2;
+ u32 GSTATUS3;
+ u32 GSTATUS4;
+#endif
+};
+
+
+/* RTC (see manual chapter 17) */
+struct s3c24x0_rtc {
+#ifdef __BIG_ENDIAN
+ u8 res1[67];
+ u8 RTCCON;
+ u8 res2[3];
+ u8 TICNT;
+ u8 res3[11];
+ u8 RTCALM;
+ u8 res4[3];
+ u8 ALMSEC;
+ u8 res5[3];
+ u8 ALMMIN;
+ u8 res6[3];
+ u8 ALMHOUR;
+ u8 res7[3];
+ u8 ALMDATE;
+ u8 res8[3];
+ u8 ALMMON;
+ u8 res9[3];
+ u8 ALMYEAR;
+ u8 res10[3];
+ u8 RTCRST;
+ u8 res11[3];
+ u8 BCDSEC;
+ u8 res12[3];
+ u8 BCDMIN;
+ u8 res13[3];
+ u8 BCDHOUR;
+ u8 res14[3];
+ u8 BCDDATE;
+ u8 res15[3];
+ u8 BCDDAY;
+ u8 res16[3];
+ u8 BCDMON;
+ u8 res17[3];
+ u8 BCDYEAR;
+#else /* little endian */
+ u8 res0[64];
+ u8 RTCCON;
+ u8 res1[3];
+ u8 TICNT;
+ u8 res2[11];
+ u8 RTCALM;
+ u8 res3[3];
+ u8 ALMSEC;
+ u8 res4[3];
+ u8 ALMMIN;
+ u8 res5[3];
+ u8 ALMHOUR;
+ u8 res6[3];
+ u8 ALMDATE;
+ u8 res7[3];
+ u8 ALMMON;
+ u8 res8[3];
+ u8 ALMYEAR;
+ u8 res9[3];
+ u8 RTCRST;
+ u8 res10[3];
+ u8 BCDSEC;
+ u8 res11[3];
+ u8 BCDMIN;
+ u8 res12[3];
+ u8 BCDHOUR;
+ u8 res13[3];
+ u8 BCDDATE;
+ u8 res14[3];
+ u8 BCDDAY;
+ u8 res15[3];
+ u8 BCDMON;
+ u8 res16[3];
+ u8 BCDYEAR;
+ u8 res17[3];
+#endif
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2400_adc {
+ u32 ADCCON;
+ u32 ADCDAT;
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2410_adc {
+ u32 ADCCON;
+ u32 ADCTSC;
+ u32 ADCDLY;
+ u32 ADCDAT0;
+ u32 ADCDAT1;
+};
+
+
+/* SPI (see manual chapter 22) */
+struct s3c24x0_spi_channel {
+ u8 SPCON;
+ u8 res1[3];
+ u8 SPSTA;
+ u8 res2[3];
+ u8 SPPIN;
+ u8 res3[3];
+ u8 SPPRE;
+ u8 res4[3];
+ u8 SPTDAT;
+ u8 res5[3];
+ u8 SPRDAT;
+ u8 res6[3];
+ u8 res7[16];
+};
+
+struct s3c24x0_spi {
+ struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
+};
+
+
+/* MMC INTERFACE (see S3C2400 manual chapter 19) */
+struct s3c2400_mmc {
+#ifdef __BIG_ENDIAN
+ u8 res1[3];
+ u8 MMCON;
+ u8 res2[3];
+ u8 MMCRR;
+ u8 res3[3];
+ u8 MMFCON;
+ u8 res4[3];
+ u8 MMSTA;
+ u16 res5;
+ u16 MMFSTA;
+ u8 res6[3];
+ u8 MMPRE;
+ u16 res7;
+ u16 MMLEN;
+ u8 res8[3];
+ u8 MMCR7;
+ u32 MMRSP[4];
+ u8 res9[3];
+ u8 MMCMD0;
+ u32 MMCMD1;
+ u16 res10;
+ u16 MMCR16;
+ u8 res11[3];
+ u8 MMDAT;
+#else
+ u8 MMCON;
+ u8 res1[3];
+ u8 MMCRR;
+ u8 res2[3];
+ u8 MMFCON;
+ u8 res3[3];
+ u8 MMSTA;
+ u8 res4[3];
+ u16 MMFSTA;
+ u16 res5;
+ u8 MMPRE;
+ u8 res6[3];
+ u16 MMLEN;
+ u16 res7;
+ u8 MMCR7;
+ u8 res8[3];
+ u32 MMRSP[4];
+ u8 MMCMD0;
+ u8 res9[3];
+ u32 MMCMD1;
+ u16 MMCR16;
+ u16 res10;
+ u8 MMDAT;
+ u8 res11[3];
+#endif
+};
+
+
+/* SD INTERFACE (see S3C2410 manual chapter 19) */
+struct s3c2410_sdi {
+ u32 SDICON;
+ u32 SDIPRE;
+ u32 SDICARG;
+ u32 SDICCON;
+ u32 SDICSTA;
+ u32 SDIRSP0;
+ u32 SDIRSP1;
+ u32 SDIRSP2;
+ u32 SDIRSP3;
+ u32 SDIDTIMER;
+ u32 SDIBSIZE;
+ u32 SDIDCON;
+ u32 SDIDCNT;
+ u32 SDIDSTA;
+ u32 SDIFSTA;
+#ifdef __BIG_ENDIAN
+ u8 res[3];
+ u8 SDIDAT;
+#else
+ u8 SDIDAT;
+ u8 res[3];
+#endif
+ u32 SDIIMSK;
+};
+
+#endif /*__S3C24X0_H__*/
diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h
new file mode 100644
index 0000000..c37d4a1
--- /dev/null
+++ b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef CONFIG_S3C2400
+ #include <asm/arch/s3c2400.h>
+#elif defined CONFIG_S3C2410
+ #include <asm/arch/s3c2410.h>
+#else
+ #error Please define the s3c24x0 cpu type
+#endif
diff --git a/include/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h
index e527c08..e527c08 100644
--- a/include/s3c6400.h
+++ b/include/asm-arm/arch-s3c64xx/s3c6400.h
diff --git a/include/s3c64x0.h b/include/asm-arm/arch-s3c64xx/s3c64x0.h
index 0bbf1d0..0bbf1d0 100644
--- a/include/s3c64x0.h
+++ b/include/asm-arm/arch-s3c64xx/s3c64x0.h
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 6c1f5ac..f1f7d93 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -1,9 +1,6 @@
/*
- * This was automagically generated from mach-types!
+ * This was automagically generated from arch/arm/tools/mach-types!
* Do NOT edit
- *
- * Last update: Fri Sep 4 22:16:22 2009
- *
*/
#ifndef __ASM_ARM_MACH_TYPE_H
@@ -1637,7 +1634,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_AML_M8050 1644
#define MACH_TYPE_MX35_3DS 1645
#define MACH_TYPE_MARS 1646
-#define MACH_TYPE_NTOSD_644XA 1647
+#define MACH_TYPE_NEUROS_OSD2 1647
#define MACH_TYPE_BADGER 1648
#define MACH_TYPE_TRIZEPS4WL 1649
#define MACH_TYPE_TRIZEPS5 1650
@@ -1653,7 +1650,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_ZORAN43XX 1660
#define MACH_TYPE_SONIX926 1661
#define MACH_TYPE_CELESTIALSEMI 1662
-#define MACH_TYPE_CC9M2443 1663
+#define MACH_TYPE_CC9M2443JS 1663
#define MACH_TYPE_TW5334 1664
#define MACH_TYPE_HTCARTEMIS 1665
#define MACH_TYPE_NAL_HLITE 1666
@@ -1775,6 +1772,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_WDG002 1785
#define MACH_TYPE_SG560ADSL 1786
#define MACH_TYPE_NEXTIO_N2800_ICA 1787
+#define MACH_TYPE_MACH_MARVELL_NEW1 1788
#define MACH_TYPE_MARVELL_NEWDB 1789
#define MACH_TYPE_VANDIHUD 1790
#define MACH_TYPE_MAGX_E8 1791
@@ -1801,7 +1799,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_RD88F5181L_GE 1812
#define MACH_TYPE_SIFMAIN 1813
#define MACH_TYPE_SAM9_L9261 1814
-#define MACH_TYPE_CC9M2443JS 1815
+#define MACH_TYPE_CC9M2443 1815
#define MACH_TYPE_XARIA300 1816
#define MACH_TYPE_IT9200 1817
#define MACH_TYPE_RD88F5181L_FXO 1818
@@ -2401,6 +2399,154 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_MULTIBUS_MASTER 2416
#define MACH_TYPE_MULTIBUS_PBK 2417
#define MACH_TYPE_TNETV107X 2418
+#define MACH_TYPE_SNAKE 2419
+#define MACH_TYPE_CWMX27 2420
+#define MACH_TYPE_SCH_M480 2421
+#define MACH_TYPE_PLATYPUS 2422
+#define MACH_TYPE_PSS2 2423
+#define MACH_TYPE_DAVINCI_APM150 2424
+#define MACH_TYPE_STR9100 2425
+#define MACH_TYPE_NET5BIG 2426
+#define MACH_TYPE_SEABED9263 2427
+#define MACH_TYPE_MX51_M2ID 2428
+#define MACH_TYPE_OCTVOCPLUS_EB 2429
+#define MACH_TYPE_KLK_FIREFOX 2430
+#define MACH_TYPE_KLK_WIRMA_MODULE 2431
+#define MACH_TYPE_KLK_WIRMA_MMI 2432
+#define MACH_TYPE_SUPERSONIC 2433
+#define MACH_TYPE_LIBERTY 2434
+#define MACH_TYPE_MH355 2435
+#define MACH_TYPE_PC7802 2436
+#define MACH_TYPE_GNET_SGC 2437
+#define MACH_TYPE_EINSTEIN15 2438
+#define MACH_TYPE_CMPD 2439
+#define MACH_TYPE_DAVINCI_HASE1 2440
+#define MACH_TYPE_LGEINCITEPHONE 2441
+#define MACH_TYPE_EA313X 2442
+#define MACH_TYPE_FWBD_39064 2443
+#define MACH_TYPE_FWBD_390128 2444
+#define MACH_TYPE_PELCO_MOE 2445
+#define MACH_TYPE_MINIMIX27 2446
+#define MACH_TYPE_OMAP3_THUNDER 2447
+#define MACH_TYPE_PASSIONC 2448
+#define MACH_TYPE_MX27AMATA 2449
+#define MACH_TYPE_BGAT1 2450
+#define MACH_TYPE_BUZZ 2451
+#define MACH_TYPE_MB9G20 2452
+#define MACH_TYPE_YUSHAN 2453
+#define MACH_TYPE_LIZARD 2454
+#define MACH_TYPE_OMAP3POLYCOM 2455
+#define MACH_TYPE_SMDKV210 2456
+#define MACH_TYPE_BRAVO 2457
+#define MACH_TYPE_SIOGENTOO1 2458
+#define MACH_TYPE_SIOGENTOO2 2459
+#define MACH_TYPE_SM3K 2460
+#define MACH_TYPE_ACER_TEMPO_F900 2461
+#define MACH_TYPE_SST61VC010_DEV 2462
+#define MACH_TYPE_GLITTERTIND 2463
+#define MACH_TYPE_OMAP_ZOOM3 2464
+#define MACH_TYPE_OMAP_3630SDP 2465
+#define MACH_TYPE_CYBOOK2440 2466
+#define MACH_TYPE_TORINO_S 2467
+#define MACH_TYPE_HAVANA 2468
+#define MACH_TYPE_BEAUMONT_11 2469
+#define MACH_TYPE_VANGUARD 2470
+#define MACH_TYPE_S5PC110_DRACO 2471
+#define MACH_TYPE_CARTESIO_TWO 2472
+#define MACH_TYPE_ASTER 2473
+#define MACH_TYPE_VOGUESV210 2474
+#define MACH_TYPE_ACM500X 2475
+#define MACH_TYPE_KM9260 2476
+#define MACH_TYPE_NIDEFLEXG1 2477
+#define MACH_TYPE_CTERA_PLUG_IO 2478
+#define MACH_TYPE_SMARTQ7 2479
+#define MACH_TYPE_AT91SAM9G10EK2 2480
+#define MACH_TYPE_ASUSP527 2481
+#define MACH_TYPE_AT91SAM9G20MPM2 2482
+#define MACH_TYPE_TOPASA900 2483
+#define MACH_TYPE_ELECTRUM_100 2484
+#define MACH_TYPE_MX51GRB 2485
+#define MACH_TYPE_XEA300 2486
+#define MACH_TYPE_HTCSTARTREK 2487
+#define MACH_TYPE_LIMA 2488
+#define MACH_TYPE_CSB740 2489
+#define MACH_TYPE_USB_S8815 2490
+#define MACH_TYPE_WATSON_EFM_PLUGIN 2491
+#define MACH_TYPE_MILKYWAY 2492
+#define MACH_TYPE_G4EVM 2493
+#define MACH_TYPE_PICOMOD6 2494
+#define MACH_TYPE_OMAPL138_HAWKBOARD 2495
+#define MACH_TYPE_IP6000 2496
+#define MACH_TYPE_IP6010 2497
+#define MACH_TYPE_UTM400 2498
+#define MACH_TYPE_OMAP3_ZYBEX 2499
+#define MACH_TYPE_WIRELESS_SPACE 2500
+#define MACH_TYPE_SX560 2501
+#define MACH_TYPE_TS41X 2502
+#define MACH_TYPE_ELPHEL10373 2503
+#define MACH_TYPE_RHOBOT 2504
+#define MACH_TYPE_MX51_REFRESH 2505
+#define MACH_TYPE_LS9260 2506
+#define MACH_TYPE_SHANK 2507
+#define MACH_TYPE_QSD8X50_ST1 2508
+#define MACH_TYPE_AT91SAM9M10EKES 2509
+#define MACH_TYPE_HIRAM 2510
+#define MACH_TYPE_PHY3250 2511
+#define MACH_TYPE_EA3250 2512
+#define MACH_TYPE_FDI3250 2513
+#define MACH_TYPE_WHITESTONE 2514
+#define MACH_TYPE_AT91SAM9263NIT 2515
+#define MACH_TYPE_CCMX51 2516
+#define MACH_TYPE_CCMX51JS 2517
+#define MACH_TYPE_CCWMX51 2518
+#define MACH_TYPE_CCWMX51JS 2519
+#define MACH_TYPE_MINI6410 2520
+#define MACH_TYPE_TINY6410 2521
+#define MACH_TYPE_NANO6410 2522
+#define MACH_TYPE_AT572D940HFNLDB 2523
+#define MACH_TYPE_HTCLEO 2524
+#define MACH_TYPE_AVP13 2525
+#define MACH_TYPE_XXSVIDEOD 2526
+#define MACH_TYPE_VPNEXT 2527
+#define MACH_TYPE_SWARCO_ITC3 2528
+#define MACH_TYPE_TX51 2529
+#define MACH_TYPE_DOLBY_CAT1021 2530
+#define MACH_TYPE_MX28EVK 2531
+#define MACH_TYPE_PHOENIX260 2532
+#define MACH_TYPE_UVACA_STORK 2533
+#define MACH_TYPE_SMARTQ5 2534
+#define MACH_TYPE_ALL3078 2535
+#define MACH_TYPE_CTERA_2BAY_DS 2536
+#define MACH_TYPE_SIOGENTOO3 2537
+#define MACH_TYPE_EPB5000 2538
+#define MACH_TYPE_HY9263 2539
+#define MACH_TYPE_ACER_TEMPO_M900 2540
+#define MACH_TYPE_ACER_TEMPO_DX900 2541
+#define MACH_TYPE_ACER_TEMPO_X960 2542
+#define MACH_TYPE_ACER_ETEN_V900 2543
+#define MACH_TYPE_ACER_ETEN_X900 2544
+#define MACH_TYPE_BONNELL 2545
+#define MACH_TYPE_OHT_MX27 2546
+#define MACH_TYPE_HTCQUARTZ 2547
+#define MACH_TYPE_DAVINCI_DM6467TEVM 2548
+#define MACH_TYPE_C3AX03 2549
+#define MACH_TYPE_MXT_TD60 2550
+#define MACH_TYPE_ESYX 2551
+#define MACH_TYPE_DOVE_DB 2552
+#define MACH_TYPE_BULLDOG 2553
+#define MACH_TYPE_DERELL_ME2000 2554
+#define MACH_TYPE_BCMRING_BASE 2555
+#define MACH_TYPE_BCMRING_EVM 2556
+#define MACH_TYPE_BCMRING_EVM_JAZZ 2557
+#define MACH_TYPE_BCMRING_SP 2558
+#define MACH_TYPE_BCMRING_SV 2559
+#define MACH_TYPE_BCMRING_SV_JAZZ 2560
+#define MACH_TYPE_BCMRING_TABLET 2561
+#define MACH_TYPE_BCMRING_VP 2562
+#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563
+#define MACH_TYPE_BCMRING_SP_WQVGA 2564
+#define MACH_TYPE_BCMRING_CUSTOM 2565
+#define MACH_TYPE_ACER_S200 2566
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -13353,9 +13499,9 @@ extern unsigned int __machine_arch_type;
# else
# define machine_arch_type MACH_TYPE_REA_2D
# endif
-# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D)
+# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D)
#else
-# define machine_is_rea_2d() (0)
+# define machine_is_rea_cpu2() (0)
#endif
#ifdef CONFIG_MACH_TI3E524
@@ -21866,16 +22012,16 @@ extern unsigned int __machine_arch_type;
# define machine_is_mars() (0)
#endif
-#ifdef CONFIG_MACH_NTOSD_644XA
+#ifdef CONFIG_MACH_NEUROS_OSD2
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_NTOSD_644XA
+# define machine_arch_type MACH_TYPE_NEUROS_OSD2
# endif
-# define machine_is_ntosd_644xa() (machine_arch_type == MACH_TYPE_NTOSD_644XA)
+# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2)
#else
-# define machine_is_ntosd_644xa() (0)
+# define machine_is_neuros_osd2() (0)
#endif
#ifdef CONFIG_MACH_BADGER
@@ -22058,16 +22204,16 @@ extern unsigned int __machine_arch_type;
# define machine_is_celestialsemi() (0)
#endif
-#ifdef CONFIG_MACH_CC9M2443
+#ifdef CONFIG_MACH_CC9M2443JS
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CC9M2443
+# define machine_arch_type MACH_TYPE_CC9M2443JS
# endif
-# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443)
+# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS)
#else
-# define machine_is_cc9m2443() (0)
+# define machine_is_cc9m2443js() (0)
#endif
#ifdef CONFIG_MACH_TW5334
@@ -23522,6 +23668,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_nextio_n2800_ica() (0)
#endif
+#ifdef CONFIG_MACH_MACH_MARVELL_NEW1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MACH_MARVELL_NEW1
+# endif
+# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_MACH_MARVELL_NEW1)
+#else
+# define machine_is_dove_db() (0)
+#endif
+
#ifdef CONFIG_MACH_MARVELL_NEWDB
# ifdef machine_arch_type
# undef machine_arch_type
@@ -23834,16 +23992,16 @@ extern unsigned int __machine_arch_type;
# define machine_is_sam9_l9261() (0)
#endif
-#ifdef CONFIG_MACH_CC9M2443JS
+#ifdef CONFIG_MACH_CC9M2443
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_CC9M2443JS
+# define machine_arch_type MACH_TYPE_CC9M2443
# endif
-# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS)
+# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443)
#else
-# define machine_is_cc9m2443js() (0)
+# define machine_is_cc9m2443() (0)
#endif
#ifdef CONFIG_MACH_XARIA300
@@ -31034,6 +31192,1782 @@ extern unsigned int __machine_arch_type;
# define machine_is_tnetv107x() (0)
#endif
+#ifdef CONFIG_MACH_SNAKE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SNAKE
+# endif
+# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE)
+#else
+# define machine_is_snake() (0)
+#endif
+
+#ifdef CONFIG_MACH_CWMX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CWMX27
+# endif
+# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27)
+#else
+# define machine_is_cwmx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_SCH_M480
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SCH_M480
+# endif
+# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480)
+#else
+# define machine_is_sch_m480() (0)
+#endif
+
+#ifdef CONFIG_MACH_PLATYPUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PLATYPUS
+# endif
+# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS)
+#else
+# define machine_is_platypus() (0)
+#endif
+
+#ifdef CONFIG_MACH_PSS2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PSS2
+# endif
+# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2)
+#else
+# define machine_is_pss2() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_APM150
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_APM150
+# endif
+# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150)
+#else
+# define machine_is_davinci_apm150() (0)
+#endif
+
+#ifdef CONFIG_MACH_STR9100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STR9100
+# endif
+# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100)
+#else
+# define machine_is_str9100() (0)
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NET5BIG
+# endif
+# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG)
+#else
+# define machine_is_net5big() (0)
+#endif
+
+#ifdef CONFIG_MACH_SEABED9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SEABED9263
+# endif
+# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263)
+#else
+# define machine_is_seabed9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_M2ID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_M2ID
+# endif
+# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID)
+#else
+# define machine_is_mx51_m2id() (0)
+#endif
+
+#ifdef CONFIG_MACH_OCTVOCPLUS_EB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB
+# endif
+# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB)
+#else
+# define machine_is_octvocplus_eb() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_FIREFOX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_FIREFOX
+# endif
+# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX)
+#else
+# define machine_is_klk_firefox() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_WIRMA_MODULE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE
+# endif
+# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE)
+#else
+# define machine_is_klk_wirma_module() (0)
+#endif
+
+#ifdef CONFIG_MACH_KLK_WIRMA_MMI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI
+# endif
+# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI)
+#else
+# define machine_is_klk_wirma_mmi() (0)
+#endif
+
+#ifdef CONFIG_MACH_SUPERSONIC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SUPERSONIC
+# endif
+# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC)
+#else
+# define machine_is_supersonic() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIBERTY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIBERTY
+# endif
+# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY)
+#else
+# define machine_is_liberty() (0)
+#endif
+
+#ifdef CONFIG_MACH_MH355
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MH355
+# endif
+# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355)
+#else
+# define machine_is_mh355() (0)
+#endif
+
+#ifdef CONFIG_MACH_PC7802
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PC7802
+# endif
+# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802)
+#else
+# define machine_is_pc7802() (0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GNET_SGC
+# endif
+# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC)
+#else
+# define machine_is_gnet_sgc() (0)
+#endif
+
+#ifdef CONFIG_MACH_EINSTEIN15
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EINSTEIN15
+# endif
+# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15)
+#else
+# define machine_is_einstein15() (0)
+#endif
+
+#ifdef CONFIG_MACH_CMPD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CMPD
+# endif
+# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD)
+#else
+# define machine_is_cmpd() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_HASE1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_HASE1
+# endif
+# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1)
+#else
+# define machine_is_davinci_hase1() (0)
+#endif
+
+#ifdef CONFIG_MACH_LGEINCITEPHONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LGEINCITEPHONE
+# endif
+# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE)
+#else
+# define machine_is_lgeincitephone() (0)
+#endif
+
+#ifdef CONFIG_MACH_EA313X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EA313X
+# endif
+# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X)
+#else
+# define machine_is_ea313x() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_39064
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_39064
+# endif
+# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064)
+#else
+# define machine_is_fwbd_39064() (0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_390128
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FWBD_390128
+# endif
+# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128)
+#else
+# define machine_is_fwbd_390128() (0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_MOE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PELCO_MOE
+# endif
+# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE)
+#else
+# define machine_is_pelco_moe() (0)
+#endif
+
+#ifdef CONFIG_MACH_MINIMIX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MINIMIX27
+# endif
+# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27)
+#else
+# define machine_is_minimix27() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_THUNDER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_THUNDER
+# endif
+# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER)
+#else
+# define machine_is_omap3_thunder() (0)
+#endif
+
+#ifdef CONFIG_MACH_PASSIONC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PASSIONC
+# endif
+# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC)
+#else
+# define machine_is_passionc() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX27AMATA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX27AMATA
+# endif
+# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA)
+#else
+# define machine_is_mx27amata() (0)
+#endif
+
+#ifdef CONFIG_MACH_BGAT1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BGAT1
+# endif
+# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1)
+#else
+# define machine_is_bgat1() (0)
+#endif
+
+#ifdef CONFIG_MACH_BUZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BUZZ
+# endif
+# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ)
+#else
+# define machine_is_buzz() (0)
+#endif
+
+#ifdef CONFIG_MACH_MB9G20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MB9G20
+# endif
+# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20)
+#else
+# define machine_is_mb9g20() (0)
+#endif
+
+#ifdef CONFIG_MACH_YUSHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_YUSHAN
+# endif
+# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN)
+#else
+# define machine_is_yushan() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIZARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIZARD
+# endif
+# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD)
+#else
+# define machine_is_lizard() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3POLYCOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3POLYCOM
+# endif
+# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM)
+#else
+# define machine_is_omap3polycom() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKV210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMDKV210
+# endif
+# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210)
+#else
+# define machine_is_smdkv210() (0)
+#endif
+
+#ifdef CONFIG_MACH_BRAVO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BRAVO
+# endif
+# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO)
+#else
+# define machine_is_bravo() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO1
+# endif
+# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1)
+#else
+# define machine_is_siogentoo1() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO2
+# endif
+# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2)
+#else
+# define machine_is_siogentoo2() (0)
+#endif
+
+#ifdef CONFIG_MACH_SM3K
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SM3K
+# endif
+# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K)
+#else
+# define machine_is_sm3k() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_F900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900
+# endif
+# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900)
+#else
+# define machine_is_acer_tempo_f900() (0)
+#endif
+
+#ifdef CONFIG_MACH_SST61VC010_DEV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SST61VC010_DEV
+# endif
+# define machine_is_sst61vc010_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV)
+#else
+# define machine_is_sst61vc010_dev() (0)
+#endif
+
+#ifdef CONFIG_MACH_GLITTERTIND
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GLITTERTIND
+# endif
+# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND)
+#else
+# define machine_is_glittertind() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_ZOOM3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_ZOOM3
+# endif
+# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3)
+#else
+# define machine_is_omap_zoom3() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_3630SDP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_3630SDP
+# endif
+# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP)
+#else
+# define machine_is_omap_3630sdp() (0)
+#endif
+
+#ifdef CONFIG_MACH_CYBOOK2440
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CYBOOK2440
+# endif
+# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440)
+#else
+# define machine_is_cybook2440() (0)
+#endif
+
+#ifdef CONFIG_MACH_TORINO_S
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TORINO_S
+# endif
+# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S)
+#else
+# define machine_is_torino_s() (0)
+#endif
+
+#ifdef CONFIG_MACH_HAVANA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HAVANA
+# endif
+# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA)
+#else
+# define machine_is_havana() (0)
+#endif
+
+#ifdef CONFIG_MACH_BEAUMONT_11
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BEAUMONT_11
+# endif
+# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11)
+#else
+# define machine_is_beaumont_11() (0)
+#endif
+
+#ifdef CONFIG_MACH_VANGUARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VANGUARD
+# endif
+# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD)
+#else
+# define machine_is_vanguard() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5PC110_DRACO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5PC110_DRACO
+# endif
+# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO)
+#else
+# define machine_is_s5pc110_draco() (0)
+#endif
+
+#ifdef CONFIG_MACH_CARTESIO_TWO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CARTESIO_TWO
+# endif
+# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO)
+#else
+# define machine_is_cartesio_two() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASTER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASTER
+# endif
+# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER)
+#else
+# define machine_is_aster() (0)
+#endif
+
+#ifdef CONFIG_MACH_VOGUESV210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VOGUESV210
+# endif
+# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210)
+#else
+# define machine_is_voguesv210() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACM500X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACM500X
+# endif
+# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X)
+#else
+# define machine_is_acm500x() (0)
+#endif
+
+#ifdef CONFIG_MACH_KM9260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KM9260
+# endif
+# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260)
+#else
+# define machine_is_km9260() (0)
+#endif
+
+#ifdef CONFIG_MACH_NIDEFLEXG1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NIDEFLEXG1
+# endif
+# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1)
+#else
+# define machine_is_nideflexg1() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_PLUG_IO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO
+# endif
+# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO)
+#else
+# define machine_is_ctera_plug_io() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ7
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQ7
+# endif
+# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7)
+#else
+# define machine_is_smartq7() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G10EK2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2
+# endif
+# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2)
+#else
+# define machine_is_at91sam9g10ek2() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASUSP527
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASUSP527
+# endif
+# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527)
+#else
+# define machine_is_asusp527() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20MPM2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2
+# endif
+# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2)
+#else
+# define machine_is_at91sam9g20mpm2() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOPASA900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOPASA900
+# endif
+# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900)
+#else
+# define machine_is_topasa900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELECTRUM_100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELECTRUM_100
+# endif
+# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100)
+#else
+# define machine_is_electrum_100() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51GRB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51GRB
+# endif
+# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB)
+#else
+# define machine_is_mx51grb() (0)
+#endif
+
+#ifdef CONFIG_MACH_XEA300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_XEA300
+# endif
+# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300)
+#else
+# define machine_is_xea300() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCSTARTREK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCSTARTREK
+# endif
+# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK)
+#else
+# define machine_is_htcstartrek() (0)
+#endif
+
+#ifdef CONFIG_MACH_LIMA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LIMA
+# endif
+# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA)
+#else
+# define machine_is_lima() (0)
+#endif
+
+#ifdef CONFIG_MACH_CSB740
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CSB740
+# endif
+# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740)
+#else
+# define machine_is_csb740() (0)
+#endif
+
+#ifdef CONFIG_MACH_USB_S8815
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_USB_S8815
+# endif
+# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815)
+#else
+# define machine_is_usb_s8815() (0)
+#endif
+
+#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN
+# endif
+# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN)
+#else
+# define machine_is_watson_efm_plugin() (0)
+#endif
+
+#ifdef CONFIG_MACH_MILKYWAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MILKYWAY
+# endif
+# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY)
+#else
+# define machine_is_milkyway() (0)
+#endif
+
+#ifdef CONFIG_MACH_G4EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_G4EVM
+# endif
+# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM)
+#else
+# define machine_is_g4evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_PICOMOD6
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PICOMOD6
+# endif
+# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6)
+#else
+# define machine_is_picomod6() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD
+# endif
+# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD)
+#else
+# define machine_is_omapl138_hawkboard() (0)
+#endif
+
+#ifdef CONFIG_MACH_IP6000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IP6000
+# endif
+# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000)
+#else
+# define machine_is_ip6000() (0)
+#endif
+
+#ifdef CONFIG_MACH_IP6010
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IP6010
+# endif
+# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010)
+#else
+# define machine_is_ip6010() (0)
+#endif
+
+#ifdef CONFIG_MACH_UTM400
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UTM400
+# endif
+# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400)
+#else
+# define machine_is_utm400() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_ZYBEX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX
+# endif
+# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX)
+#else
+# define machine_is_omap3_zybex() (0)
+#endif
+
+#ifdef CONFIG_MACH_WIRELESS_SPACE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WIRELESS_SPACE
+# endif
+# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE)
+#else
+# define machine_is_wireless_space() (0)
+#endif
+
+#ifdef CONFIG_MACH_SX560
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SX560
+# endif
+# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560)
+#else
+# define machine_is_sx560() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS41X
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS41X
+# endif
+# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X)
+#else
+# define machine_is_ts41x() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELPHEL10373
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELPHEL10373
+# endif
+# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373)
+#else
+# define machine_is_elphel10373() (0)
+#endif
+
+#ifdef CONFIG_MACH_RHOBOT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RHOBOT
+# endif
+# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT)
+#else
+# define machine_is_rhobot() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_REFRESH
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_REFRESH
+# endif
+# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH)
+#else
+# define machine_is_mx51_refresh() (0)
+#endif
+
+#ifdef CONFIG_MACH_LS9260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LS9260
+# endif
+# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260)
+#else
+# define machine_is_ls9260() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHANK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHANK
+# endif
+# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK)
+#else
+# define machine_is_shank() (0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_ST1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QSD8X50_ST1
+# endif
+# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1)
+#else
+# define machine_is_qsd8x50_st1() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9M10EKES
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES
+# endif
+# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES)
+#else
+# define machine_is_at91sam9m10ekes() (0)
+#endif
+
+#ifdef CONFIG_MACH_HIRAM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HIRAM
+# endif
+# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM)
+#else
+# define machine_is_hiram() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHY3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHY3250
+# endif
+# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250)
+#else
+# define machine_is_phy3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_EA3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EA3250
+# endif
+# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250)
+#else
+# define machine_is_ea3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_FDI3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_FDI3250
+# endif
+# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250)
+#else
+# define machine_is_fdi3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_WHITESTONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WHITESTONE
+# endif
+# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE)
+#else
+# define machine_is_whitestone() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263NIT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263NIT
+# endif
+# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT)
+#else
+# define machine_is_at91sam9263nit() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCMX51
+# endif
+# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51)
+#else
+# define machine_is_ccmx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX51JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCMX51JS
+# endif
+# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS)
+#else
+# define machine_is_ccmx51js() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51
+# endif
+# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51)
+#else
+# define machine_is_ccwmx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51JS
+# endif
+# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS)
+#else
+# define machine_is_ccwmx51js() (0)
+#endif
+
+#ifdef CONFIG_MACH_MINI6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MINI6410
+# endif
+# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410)
+#else
+# define machine_is_mini6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_TINY6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TINY6410
+# endif
+# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410)
+#else
+# define machine_is_tiny6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_NANO6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NANO6410
+# endif
+# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410)
+#else
+# define machine_is_nano6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT572D940HFNLDB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT572D940HFNLDB
+# endif
+# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB)
+#else
+# define machine_is_at572d940hfnldb() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCLEO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCLEO
+# endif
+# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO)
+#else
+# define machine_is_htcleo() (0)
+#endif
+
+#ifdef CONFIG_MACH_AVP13
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AVP13
+# endif
+# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13)
+#else
+# define machine_is_avp13() (0)
+#endif
+
+#ifdef CONFIG_MACH_XXSVIDEOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_XXSVIDEOD
+# endif
+# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD)
+#else
+# define machine_is_xxsvideod() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPNEXT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPNEXT
+# endif
+# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT)
+#else
+# define machine_is_vpnext() (0)
+#endif
+
+#ifdef CONFIG_MACH_SWARCO_ITC3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SWARCO_ITC3
+# endif
+# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3)
+#else
+# define machine_is_swarco_itc3() (0)
+#endif
+
+#ifdef CONFIG_MACH_TX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TX51
+# endif
+# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51)
+#else
+# define machine_is_tx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOLBY_CAT1021
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOLBY_CAT1021
+# endif
+# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021)
+#else
+# define machine_is_dolby_cat1021() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX28EVK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX28EVK
+# endif
+# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK)
+#else
+# define machine_is_mx28evk() (0)
+#endif
+
+#ifdef CONFIG_MACH_PHOENIX260
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PHOENIX260
+# endif
+# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260)
+#else
+# define machine_is_phoenix260() (0)
+#endif
+
+#ifdef CONFIG_MACH_UVACA_STORK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UVACA_STORK
+# endif
+# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK)
+#else
+# define machine_is_uvaca_stork() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMARTQ5
+# endif
+# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5)
+#else
+# define machine_is_smartq5() (0)
+#endif
+
+#ifdef CONFIG_MACH_ALL3078
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ALL3078
+# endif
+# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078)
+#else
+# define machine_is_all3078() (0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_2BAY_DS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS
+# endif
+# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS)
+#else
+# define machine_is_ctera_2bay_ds() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIOGENTOO3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIOGENTOO3
+# endif
+# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3)
+#else
+# define machine_is_siogentoo3() (0)
+#endif
+
+#ifdef CONFIG_MACH_EPB5000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EPB5000
+# endif
+# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000)
+#else
+# define machine_is_epb5000() (0)
+#endif
+
+#ifdef CONFIG_MACH_HY9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HY9263
+# endif
+# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263)
+#else
+# define machine_is_hy9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_M900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900
+# endif
+# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900)
+#else
+# define machine_is_acer_tempo_m900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_DX900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900
+# endif
+# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900)
+#else
+# define machine_is_acer_tempo_dx650() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_TEMPO_X960
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960
+# endif
+# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960)
+#else
+# define machine_is_acer_tempo_x960() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_ETEN_V900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_ETEN_V900
+# endif
+# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900)
+#else
+# define machine_is_acer_eten_v900() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_ETEN_X900
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_ETEN_X900
+# endif
+# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900)
+#else
+# define machine_is_acer_eten_x900() (0)
+#endif
+
+#ifdef CONFIG_MACH_BONNELL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BONNELL
+# endif
+# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL)
+#else
+# define machine_is_bonnell() (0)
+#endif
+
+#ifdef CONFIG_MACH_OHT_MX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OHT_MX27
+# endif
+# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27)
+#else
+# define machine_is_oht_mx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCQUARTZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCQUARTZ
+# endif
+# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ)
+#else
+# define machine_is_htcquartz() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM
+# endif
+# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM)
+#else
+# define machine_is_davinci_dm6467tevm() (0)
+#endif
+
+#ifdef CONFIG_MACH_C3AX03
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_C3AX03
+# endif
+# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03)
+#else
+# define machine_is_c3ax03() (0)
+#endif
+
+#ifdef CONFIG_MACH_MXT_TD60
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MXT_TD60
+# endif
+# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60)
+#else
+# define machine_is_mxt_td60() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESYX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESYX
+# endif
+# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX)
+#else
+# define machine_is_esyx() (0)
+#endif
+
+#ifdef CONFIG_MACH_DOVE_DB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DOVE_DB
+# endif
+# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB)
+#else
+# define machine_is_dove_db2() (0)
+#endif
+
+#ifdef CONFIG_MACH_BULLDOG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BULLDOG
+# endif
+# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG)
+#else
+# define machine_is_bulldog() (0)
+#endif
+
+#ifdef CONFIG_MACH_DERELL_ME2000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DERELL_ME2000
+# endif
+# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000)
+#else
+# define machine_is_derell_me2000() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_BASE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_BASE
+# endif
+# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE)
+#else
+# define machine_is_bcmring_base() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM
+# endif
+# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM)
+#else
+# define machine_is_bcmring_evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ
+# endif
+# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ)
+#else
+# define machine_is_bcmring_evm_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SP
+# endif
+# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP)
+#else
+# define machine_is_bcmring_sp() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SV
+# endif
+# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV)
+#else
+# define machine_is_bcmring_sv() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SV_JAZZ
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ
+# endif
+# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ)
+#else
+# define machine_is_bcmring_sv_jazz() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_TABLET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_TABLET
+# endif
+# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET)
+#else
+# define machine_is_bcmring_tablet() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_VP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_VP
+# endif
+# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP)
+#else
+# define machine_is_bcmring_vp() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR
+# endif
+# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR)
+#else
+# define machine_is_bcmring_evm_seikor() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_SP_WQVGA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA
+# endif
+# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA)
+#else
+# define machine_is_bcmring_sp_wqvga() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_CUSTOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM
+# endif
+# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM)
+#else
+# define machine_is_bcmring_custom() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_S200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_S200
+# endif
+# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200)
+#else
+# define machine_is_acer_s200() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index ea0b366..3af6ad3 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -47,7 +47,7 @@ extern __inline__ void __delay(unsigned long loops)
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
-extern __inline__ void udelay(unsigned long usecs)
+extern __inline__ void __udelay(unsigned long usecs)
{
__delay(usecs);
}
diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h
index 7f408cb..3e2674a 100644
--- a/include/asm-i386/interrupt.h
+++ b/include/asm-i386/interrupt.h
@@ -43,31 +43,4 @@ extern char exception_stack[];
#define __isr__ void __attribute__ ((regparm(0)))
-#define DECLARE_INTERRUPT(x) \
- asm(".globl irq_"#x"\n" \
- "irq_"#x":\n" \
- "pusha \n" \
- "pushl $"#x"\n" \
- "pushl $irq_return\n" \
- "jmp do_irq\n"); \
- __isr__ irq_##x(void)
-
-#define DECLARE_EXCEPTION(x, f) \
- asm(".globl exp_"#x"\n" \
- "exp_"#x":\n" \
- "pusha \n" \
- "movl %esp, %ebx\n" \
- "movl $exception_stack, %eax\n" \
- "movl %eax, %esp \n" \
- "pushl %ebx\n" \
- "movl 32(%esp), %ebx\n" \
- "xorl %edx, %edx\n" \
- "movw 36(%esp), %dx\n" \
- "pushl %edx\n" \
- "pushl %ebx\n" \
- "pushl $"#x"\n" \
- "pushl $exp_return\n" \
- "jmp "#f"\n"); \
- __isr__ exp_##x(void)
-
#endif
diff --git a/include/asm-i386/u-boot-i386.h b/include/asm-i386/u-boot-i386.h
index 3921e01..7c99c8c 100644
--- a/include/asm-i386/u-boot-i386.h
+++ b/include/asm-i386/u-boot-i386.h
@@ -24,25 +24,9 @@
#ifndef _U_BOOT_I386_H_
#define _U_BOOT_I386_H_ 1
-/* for the following variables, see start.S */
-extern ulong i386boot_start; /* code start (in flash) */
-extern ulong i386boot_end; /* code end (in flash) */
-extern ulong i386boot_romdata_start;/* datasegment in flash (also code+rodata end) */
-extern ulong i386boot_romdata_dest; /* data location segment in ram */
-extern ulong i386boot_romdata_size; /* size of data segment */
-extern ulong i386boot_bss_start; /* bss start */
-extern ulong i386boot_bss_size; /* bss size */
-extern ulong i386boot_stack_end; /* first usable RAM address after bss and stack */
-extern ulong i386boot_ram_end; /* end of ram */
-
-extern ulong i386boot_realmode; /* start of realmode entry code */
-extern ulong i386boot_realmode_size;/* size of realmode entry code */
-extern ulong i386boot_bios; /* start of BIOS emulation code */
-extern ulong i386boot_bios_size; /* size of BIOS emulation code */
-
-
/* cpu/.../cpu.c */
-int cpu_init(void);
+int cpu_init_r(void);
+int cpu_init_f(void);
/* cpu/.../timer.c */
void timer_isr(void *);
@@ -55,9 +39,6 @@ int timer_init(void);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
-/* cpu/.../exceptions.c */
-int cpu_init_exceptions(void);
-
/* board/.../... */
int board_init(void);
int dram_init(void);
diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h
index 30125a1..f686e7c 100644
--- a/include/asm-ppc/4xx_pci.h
+++ b/include/asm-ppc/4xx_pci.h
@@ -1,6 +1,8 @@
#ifndef _405GP_PCI_H
#define _405GP_PCI_H
+#include <pci.h>
+
/*----------------------------------------------------------------------------+
| 405GP PCI core memory map defines.
+----------------------------------------------------------------------------*/
@@ -49,4 +51,10 @@
#define PCIDEVID_405GP 0x0
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
+int pci_arbiter_enabled(void);
+int __pci_pre_init(struct pci_controller *hose);
+void __pci_target_init(struct pci_controller *hose);
+void __pci_master_init(struct pci_controller *hose);
+
#endif
diff --git a/include/common.h b/include/common.h
index f7c93bf..00b5434 100644
--- a/include/common.h
+++ b/include/common.h
@@ -107,6 +107,9 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
#include <part.h>
#include <flash.h>
@@ -495,8 +498,9 @@ int prt_mpc8220_clks (void);
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
- defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)
+#if defined(CONFIG_S3C24X0) || \
+ defined(CONFIG_LH7A40X) || \
+ defined(CONFIG_S3C6400)
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);
@@ -603,16 +607,17 @@ unsigned long long get_ticks(void);
void wait_ticks (unsigned long);
/* lib_$(ARCH)/time.c */
-void udelay (unsigned long);
+void __udelay (unsigned long);
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
int init_timebase (void);
+/* lib_generic/time.c */
+void udelay (unsigned long);
+
/* lib_generic/vsprintf.c */
ulong simple_strtoul(const char *cp,char **endp,unsigned int base);
-#ifdef CONFIG_SYS_64BIT_VSPRINTF
unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
-#endif
long simple_strtol(const char *cp,char **endp,unsigned int base);
void panic(const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 694a87b..5cb0f1e 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -160,8 +160,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 2384925..ae8494d 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -165,8 +165,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index e9ea1bf..65dc235 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -60,8 +60,9 @@
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-#define CONFIG_SYS_PCI_IOBASE 0xe8000000
-
+#define CONFIG_SYS_PCI_IOBASE 0xe8000000
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 1a2266f..9233523 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -219,8 +219,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 518d94d..ea502d4 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -160,8 +160,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 147a8b2..71bb7b4 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -263,8 +263,6 @@
#define CONFIG_SYS_NAND0_BASE 0xE1000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#endif /* CONFIG_CMD_NAND */
/*-----------------------------------------------------------------------
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 5927e76..0a4ba29 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -236,7 +236,6 @@
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 8eaff5d..79376b3 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -228,7 +228,6 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 6cee78a..1d1f94f 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -213,7 +213,6 @@
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index abeb6a2..63f1d85 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -321,9 +321,6 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 7ef92f7..913184c 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -343,9 +343,6 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 46d6e9d..87901b3 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -433,10 +433,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
-
/*
* I2C
*/
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 4af599b..78bb74b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -260,9 +260,6 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index f41fe30..e945da2 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -286,9 +286,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b7d3553..799d946 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -242,9 +242,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 53de56d..3eb0049 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -309,9 +309,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index abbfd47..07a8e61 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -284,9 +284,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index df59aca..4a4a9ed 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -253,9 +253,6 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 426b933..128a7e1 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -270,9 +270,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index b87f375..1e659e2 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -247,9 +247,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 0e7745c..41e4a6e 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -367,9 +367,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 7cb4ccd..1d2d659 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -251,9 +251,6 @@
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a46f7c8..12a8f60 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -301,10 +301,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index e2930c1..ddfe7aa 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -310,9 +310,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 9574fca..df9ab34 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -401,9 +401,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 2f84f7f..3d59454 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -99,8 +99,6 @@
#define CONFIG_SUPPORT_VFAT
-#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
@@ -183,8 +181,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* PCI stuff
*/
@@ -266,10 +262,10 @@
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFA0000
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
/*
* Environment Variable setup
@@ -428,4 +424,14 @@
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_USB_STORAGE 1
+/*
+ * UBI
+ */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
#endif /* __CONFIG_H */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index d6e2f6b..6310cfc 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -351,7 +351,6 @@
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_DIAG
@@ -359,7 +358,6 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
@@ -435,11 +433,14 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
+/* for weak __pci_target_init() */
+#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 6fba0ca..8e9d928 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -211,8 +211,6 @@
*-----------------------------------------------------------------------
*/
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* nand device 1 on dave (PPChameleonEVB) needs more time,
* so we just introduce additional wait in nand_wait(),
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index f68d834..36e952e 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -132,7 +132,6 @@
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 6eaa61d..12a7eda 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -442,8 +442,6 @@
WRITE_NAND(d, addr); \
} while(0)
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#endif /* CONFIG_CMD_NAND */
#define CONFIG_PCI
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 1fbf4bf..d44fb07 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -372,8 +372,6 @@
#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#endif /* CONFIG_NAND */
/*
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 618b7f0..ebc81c4 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -33,9 +33,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 17397e8..38a1d0d 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -169,8 +169,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index dbfa1aa..5c281a1 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -157,8 +157,6 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 1a810e4..c63fd42 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -239,9 +239,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 3f73780..1a56c60 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -213,9 +213,6 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 7782df3..7fd3668 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -244,9 +244,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
new file mode 100644
index 0000000..fcc5563
--- /dev/null
+++ b/include/configs/a320evb.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Configuation settings for the Faraday A320 board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/a320.h>
+
+/*-----------------------------------------------------------------------
+ * CPU and Board Configuration Options
+ */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*-----------------------------------------------------------------------
+ * Timer
+ */
+#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*-----------------------------------------------------------------------
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 0x98200000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 18432000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*-----------------------------------------------------------------------
+ * SDRAM controller configuration
+ */
+#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
+ FTSDMC020_TP0_TRP(1) | \
+ FTSDMC020_TP0_TRCD(1) | \
+ FTSDMC020_TP0_TRF(3) | \
+ FTSDMC020_TP0_TWR(1) | \
+ FTSDMC020_TP0_TCL(2))
+
+#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
+ FTSDMC020_TP1_INI_REFT(8) | \
+ FTSDMC020_TP1_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
+ FTSDMC020_BANK_DDW_X16 | \
+ FTSDMC020_BANK_DSZ_256M | \
+ FTSDMC020_BANK_MBW_32 | \
+ FTSDMC020_BANK_SIZE_64M)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x12000000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x13F00000
+
+/*-----------------------------------------------------------------------
+ * Static memory controller configuration
+ */
+
+#include <asm/arch/ftsmc020.h>
+
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_1M | \
+ FTSMC020_BANK_MBW_8)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* support JEDEC */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+#define PHYS_FLASH_1 0x00000000
+#define PHYS_FLASH_2 0x00400000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR 0x00060000
+#define CONFIG_ENV_SIZE 0x20000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 2fb48b6..bd3388f 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -266,8 +266,6 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 74677d8..58b8c8c 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -107,7 +107,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index e6248e9..964630f 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -231,13 +231,11 @@
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index 575f60e..adab454 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -76,6 +76,7 @@
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE_FLEX SZ_256K
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
/* bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
@@ -255,8 +256,7 @@
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_ADDR 0x00020000
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_ENV_ADDR_FLEX 0x00040000
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
diff --git a/include/configs/aria.h b/include/configs/aria.h
index 2938eac..f89fc57 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -251,8 +251,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* Configuration parameters for MPC5121 NAND driver
*/
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index cc194d8..322718f 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -131,7 +131,6 @@
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 3507de2..0509011 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -123,7 +123,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index f86698f..fbf7389 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -133,7 +133,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* NOR flash - no real flash on this board */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index a1582fc..571351c 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -267,7 +267,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index b460188..06184e7 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -118,7 +118,6 @@
/* NOR flash, if populated */
#ifndef CONFIG_CMD_NAND
#define CONFIG_SYS_NO_FLASH 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#else
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
@@ -142,7 +141,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index b83266d..6fad75d 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -119,7 +119,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet - not present */
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 0b87418..0fbd8f4 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -87,9 +87,6 @@
# define CONFIG_CMD_SPIBOOTLDR
# endif
#endif
-#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_64BIT_VSPRINTF
-#endif
/*
* Console Settings
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index de8cfb7..4ef8566 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -295,7 +295,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
new file mode 100644
index 0000000..38e2ce1
--- /dev/null
+++ b/include/configs/da830evm.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+
+/*
+ * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
+#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+#define DEF_BOOTM ""
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_SYS_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_OFFSET (256 << 10)
+#define CONFIG_ENV_SECT_SIZE 4096
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+
+/*
+ * U-Boot general configuration
+ */
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#undef CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "DA830-evm > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_EEPROM
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+#define CONFIG_CMD_USB /* include support for usb */
+#define CONFIG_CMD_STORAGE /* include support for usb */
+#define CONFIG_CMD_FAT /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index ea40df0..d092fb8 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -69,7 +69,6 @@
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index 5db720e..ca3dea4 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -114,7 +114,6 @@
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#endif
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index 53a105b..4916077 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -77,7 +77,6 @@
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index 6617941..ce2d7c4 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -77,7 +77,6 @@
#define CONFIG_NAND_DAVINCI
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
#define CONFIG_SYS_NAND_HW_ECC
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index b045e80..f7d2399 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -138,7 +138,6 @@
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 9384cdd..47db2aa 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -92,7 +92,6 @@
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*=====================*/
/* Board related stuff */
/*=====================*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 71d48fb..f24eb7a 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -87,7 +87,6 @@
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 9138b2b..5a55c56 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -125,7 +125,6 @@
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define DEF_BOOTM ""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 95e04f9..9c46c5b 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -226,8 +226,6 @@
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* nand timeout values */
#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
#define CONFIG_SYS_NAND_OTHER_TO 100
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index bd5037e..e81da67 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -66,6 +66,9 @@
/* Hardware drivers */
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* DM9000 */
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 20
@@ -129,8 +132,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 243a554..6a68bf4 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -28,6 +28,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_RELOC_FIXUP_WORKS
+
/*
* Stuff still to be dealt with -
*/
@@ -61,7 +63,7 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
@@ -234,8 +236,8 @@
#ifndef __ASSEMBLER__
extern unsigned long ip;
-#define PRINTIP asm ("call next_line\n" \
- "next_line:\n" \
+#define PRINTIP asm ("call 0\n" \
+ "0:\n" \
"pop %%eax\n" \
"movl %%eax, %0\n" \
:"=r"(ip) \
diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
index c639e5b..ee749ec 100644
--- a/include/configs/imx27lite.h
+++ b/include/configs/imx27lite.h
@@ -157,6 +157,7 @@
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* SD/MMC
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
new file mode 100644
index 0000000..d9028fa
--- /dev/null
+++ b/include/configs/ipek01.h
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
+#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+#define CONFIG_IPEK01 /* Motherboard is ipek01 */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+
+/*
+ * Video configuration for LIME GDC
+ */
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+/* Lime clock frequency */
+#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
+#endif
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CONFIG_EEPRO100 1
+#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP /* BMP support */
+#endif
+#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_IDE /* IDE harddisk support */
+#define CONFIG_CMD_IRQ /* irqinfo */
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_PCI /* pciinfo */
+#define CONFIG_CMD_USB /* USB Support */
+
+#define CONFIG_SYS_LOWBOOT 1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyPSC0\0" \
+ "hostname=ipek01\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} " \
+ "console=${consoledev},${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} - ${fdtaddr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
+ "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
+ "run nfsargs addip addtty;" \
+ "bootm ${loadaddr} - ${fdtaddr}\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "bootfile=ipek01/uImage\0" \
+ "load=tftp 100000 ipek01/u-boot.bin\0" \
+ "update=protect off FC000000 +60000; era FC000000 +60000; " \
+ "cp.b 100000 FC000000 ${filesize}\0" \
+ "upd=run load;run update\0" \
+ "fdtaddr=800000\0" \
+ "loadaddr=400000\0" \
+ "fdtfile=ipek01/ipek01.dtb\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
+/* PCI clock must be 33, because board will not boot */
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
+
+/*
+ * Open firmware flat tree support
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
+
+/* use CFI flash driver */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xf0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+#define CONFIG_SYS_SRAM_BASE 0xF1000000
+#define CONFIG_SYS_SRAM_SIZE 0x00200000
+#define CONFIG_SYS_LIME_BASE 0xE4000000
+#define CONFIG_SYS_LIME_SIZE 0x04000000
+#define CONFIG_SYS_FPGA_BASE 0xC0000000
+#define CONFIG_SYS_FPGA_SIZE 0x10000000
+#define CONFIG_SYS_MPEG_BASE 0xe2000000
+#define CONFIG_SYS_MPEG_SIZE 0x01000000
+#define CONFIG_SYS_CF_BASE 0xe1000000
+#define CONFIG_SYS_CF_SIZE 0x01000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+
+
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+#else
+#define CONFIG_SYS_HID0_INIT 0
+#define CONFIG_SYS_HID0_FINAL 0
+#endif
+
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
+#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
+#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
+#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
+#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
+#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
+
+#ifdef CONFIG_SYS_PCISPEED_66
+#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
+#define CONFIG_SYS_CS1_CFG 0x0004FB00
+#define CONFIG_SYS_CS2_CFG 0x0006F900
+#else
+#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
+#define CONFIG_SYS_CS1_CFG 0x0001FB00
+#define CONFIG_SYS_CS2_CFG 0x0002F90C
+#endif
+
+/*
+ * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
+ * waitstates, writeswap and readswap enabled
+ */
+#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
+#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
+#define CONFIG_SYS_CS7_CFG 0x4040751C
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
+
+#define CONFIG_SYS_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 3840267..c013ac4 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -140,6 +140,11 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
+
/* I2C RTC */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
@@ -194,8 +199,10 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index 80c41a4..2ef6a35 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -127,8 +127,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for UBI/UBIFS */
-
/* UBI Support for all Keymile boards */
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 965599c..8d4ce8d 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -217,8 +217,6 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
diff --git a/include/configs/korat.h b/include/configs/korat.h
index ea6ba89..026dd08 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -69,6 +69,7 @@
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
/* Don't change either of these */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
@@ -359,6 +360,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 777a4d6..011dd5c 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -344,10 +344,12 @@
/* Video console */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
@@ -495,8 +497,6 @@
/*-----------------------------------------------------------------------
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
/* Lime Clock frequency is to set 100MHz */
#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
#if 0
@@ -504,15 +504,15 @@
#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
#endif
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
and pixel flare on display when 133MHz was configured. According to
SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3
+#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
+#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
#else
-#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2
+#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
+#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index c0122b7..c04830b 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -125,6 +125,9 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_COMMAND_HISTORY 1
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index e194c8f..cccc31d 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -177,8 +177,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* Configuration parameters for MPC5121 NAND driver
*/
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index b996854..ab5cbca 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -121,7 +121,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index ebc518c..fb49388 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -239,8 +239,6 @@
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/*
* Configuration parameters for MPC5121 NAND driver
*/
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 7bddf24..20b423b 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -111,8 +111,6 @@
#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index a00c2fb..2b640dc 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -91,7 +91,6 @@
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
-#define CONFIG_SYS_64BIT_VSPRINTF /* mtd desires this */
#define BOARD_LATE_INIT /* call board_late_init during start up */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 19a5ec9..a6fe5e1 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -97,6 +97,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
@@ -148,8 +151,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index a5514ae..00093f8 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -101,6 +101,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
@@ -143,8 +146,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index ffb515d..0c12b9f 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -89,6 +89,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
@@ -134,8 +137,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 6f21af3..154c0f4 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -92,6 +92,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
@@ -137,9 +140,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 229dc5e..d91c8ff 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -137,6 +137,9 @@
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
+/* DDR - I use Infineon DDR */
+#define CONFIG_OMAP3_INFINEON_DDR 1
+
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index da4b677..ef7a28b 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -98,6 +98,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* commands to include */
#include <config_cmd_default.h>
@@ -144,9 +147,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 32cd6fd..2b07666 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -98,6 +98,9 @@
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
@@ -164,8 +167,6 @@
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* Environment information */
#define CONFIG_BOOTDELAY 10
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index 2aba0cb..88f27ba 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -114,7 +114,6 @@
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 2612165..220f686 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -266,7 +266,6 @@
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 9bf49ba..399d15f 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -236,9 +236,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
-
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 6761c18..0af1280 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -259,7 +259,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_CMD_JFFS2 1
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index d63c43e..b08dcd4 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -226,7 +226,6 @@
#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3f4d42c..3d8e25c 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -107,7 +107,6 @@
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index e6886cf..025ad09 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -43,9 +43,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index 7a2dcd8..f4b3477 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -161,7 +161,6 @@
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 682d241..315eebe 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -285,9 +285,6 @@
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 5763760..a5eca39 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -376,11 +376,6 @@
* CONFIG_SYS_FLASH_BASE -> start address of internal flash
* CONFIG_SYS_MONITOR_BASE -> start of u-boot
*/
-#ifndef __ASSEMBLER__
-extern unsigned long offsetOfBigFlash;
-extern unsigned long offsetOfEnvironment;
-#endif
-
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
@@ -427,8 +422,6 @@ extern unsigned long offsetOfEnvironment;
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x77D00000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
/* No command line, one static partition */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 214a9af..2f1dae7 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -65,7 +65,7 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index f3fc960..cf5633c 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -63,7 +63,7 @@
/*
* Size of malloc() pool
*/
-#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_BAUDRATE 9600
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 9605ce2..5788d58 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -364,6 +364,7 @@
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 1f95a3c..fc401a8 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -107,7 +107,6 @@
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index a1beb65..fd51219 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -34,9 +34,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T core */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
-#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
+#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index c57751b..f9d1e55 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -33,9 +33,10 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
-#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index f6e1221..f04feae 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -49,8 +49,6 @@
#define CONFIG_ENABLE_MMU
#endif
-#define CONFIG_MEMORY_UPPER_CODE
-
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
@@ -270,8 +268,6 @@
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* Boot configuration (define only one of next 3) */
#define CONFIG_BOOT_NAND
/* None of these are currently implemented. Left from the original Samsung
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 8c472af..bf0ee67 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -213,8 +213,6 @@
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
#define CONFIG_IDENT_STRING " for SMDKC100"
-#define CONFIG_SYS_64BIT_VSPRINTF
-
#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 35feed0..9641041 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -188,8 +188,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
@@ -198,11 +196,13 @@
#define CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_SW_CURSOR
@@ -210,6 +210,11 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF 0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
+
/* Serial Port */
#define CONFIG_CONS_INDEX 1
diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h
index 5b70a7b..4ad081b 100644
--- a/include/configs/tny_a9260.h
+++ b/include/configs/tny_a9260.h
@@ -138,7 +138,6 @@
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 97f30ce..9827195 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -40,10 +40,11 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
-#define CONFIG_TRAB 1 /* on a TRAB Board */
-#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
+#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
+#define CONFIG_TRAB 1 /* on a TRAB Board */
+#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
/* automatic software updates (see board/trab/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 20bf481..1b894a6 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -284,12 +284,6 @@ int vct_gpio_get(int pin);
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/*
- * Needed for 64bit printf format
- */
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
-/*
* UBI configuration
*/
#if defined(CONFIG_VCT_ONENAND)
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index b165bd7..42f8807 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -389,6 +389,11 @@
#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
+#define FPGA_REG1A_GLED_ENCODE(n) (FPGA_REG1A_PE0_GLED >> (n))
+#define FPGA_REG1A_YLED_ENCODE(n) (FPGA_REG1A_PE0_YLED >> (n))
+#define FPGA_REG1A_PWRON_ENCODE(n) (FPGA_REG1A_PE0_PWRON >> (n))
+#define FPGA_REG1A_REFCLK_ENCODE(n) (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
+
/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
@@ -407,6 +412,9 @@
#define FPGA_REG1C_PE1_PERST 0x0008
#define FPGA_REG1C_PE2_PERST 0x0004
+#define FPGA_REG1C_ROOTPOINT_ENCODE(n) (FPGA_REG1C_PE0_ROOTPOINT >> (n))
+#define FPGA_REG1C_PERST_ENCODE(n) (FPGA_REG1C_PE0_PERST >> (n))
+
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 36c341e..d0fc138 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -205,8 +205,6 @@
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-
/* NAND Timing Parameters (in ns) */
#define NAND_TIMING_tCH 10
#define NAND_TIMING_tCS 0
diff --git a/include/exports.h b/include/exports.h
index 2e8fd8b..c3a5d2f 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -16,7 +16,7 @@ void install_hdlr(int, interrupt_handler_t*, void*);
void free_hdlr(int);
void *malloc(size_t);
void free(void*);
-void udelay(unsigned long);
+void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
void vprintf(const char *, va_list);
void do_reset (void);
diff --git a/include/image.h b/include/image.h
index 04b62d1..d2e78fe 100644
--- a/include/image.h
+++ b/include/image.h
@@ -164,6 +164,7 @@
#define IH_COMP_GZIP 1 /* gzip Compression Used */
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
#define IH_COMP_LZMA 3 /* lzma Compression Used */
+#define IH_COMP_LZO 4 /* lzo Compression Used */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
diff --git a/include/linux/lzo.h b/include/linux/lzo.h
index d793497..88687fa 100644
--- a/include/linux/lzo.h
+++ b/include/linux/lzo.h
@@ -27,6 +27,10 @@ int lzo1x_1_compress(const unsigned char *src, size_t src_len,
int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
unsigned char *dst, size_t *dst_len);
+/* decompress lzop format */
+int lzop_decompress(const unsigned char *src, size_t src_len,
+ unsigned char *dst, size_t *dst_len);
+
/*
* Return values (< 0 = Error)
*/
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 410c5dd..8d5f60c 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -123,7 +123,7 @@ struct nand_oobfree {
*/
struct nand_ecclayout {
uint32_t eccbytes;
- uint32_t eccpos[64];
+ uint32_t eccpos[128];
uint32_t oobavail;
struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
};
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index cb7c19a..94ad0c0 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -397,7 +397,7 @@ struct nand_chip {
int bbt_erase_shift;
int chip_shift;
int numchips;
- unsigned long chipsize;
+ uint64_t chipsize;
int pagemask;
int pagebuf;
int subpagesize;
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index 9a6f317..68e174e 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -20,8 +20,9 @@
#include <linux/mtd/compat.h>
#include <linux/mtd/bbm.h>
+#define MAX_DIES 2
#define MAX_BUFFERRAM 2
-#define MAX_ONENAND_PAGESIZE (2048 + 64)
+#define MAX_ONENAND_PAGESIZE (4096 + 128)
/* Scan and identify a OneNAND device */
extern int onenand_scan (struct mtd_info *mtd, int max_chips);
@@ -39,9 +40,14 @@ struct onenand_bufferram {
/**
* struct onenand_chip - OneNAND Private Flash Chip Data
* @param base [BOARDSPECIFIC] address to access OneNAND
+ * @dies: [INTERN][FLEXONENAND] number of dies on chip
+ * @boundary: [INTERN][FLEXONENAND] Boundary of the dies
+ * @diesize: [INTERN][FLEXONENAND] Size of the dies
* @param chipsize [INTERN] the size of one chip for multichip arrays
* @param device_id [INTERN] device ID
* @param verstion_id [INTERN] version ID
+ * @technology [INTERN] describes the internal NAND array technology such as SLC or MLC.
+ * @density_mask: [INTERN] chip density, used for DDP devices
* @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
* @param erase_shift [INTERN] number of address bits in a block
* @param page_shift [INTERN] number of address bits in a page
@@ -64,9 +70,13 @@ struct onenand_bufferram {
*/
struct onenand_chip {
void __iomem *base;
+ unsigned int dies;
+ unsigned int boundary[MAX_DIES];
+ unsigned int diesize[MAX_DIES];
unsigned int chipsize;
unsigned int device_id;
unsigned int version_id;
+ unsigned int technology;
unsigned int density_mask;
unsigned int options;
@@ -124,6 +134,8 @@ struct onenand_chip {
#define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0)
#define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1)
+#define FLEXONENAND(this) (this->device_id & DEVICE_IS_FLEXONENAND)
+#define ONENAND_IS_MLC(this) (this->technology & ONENAND_TECHNOLOGY_IS_MLC)
#define ONENAND_IS_DDP(this) \
(this->device_id & ONENAND_DEVICE_IS_DDP)
@@ -157,4 +169,6 @@ struct onenand_manufacturers {
int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops);
+unsigned int onenand_block(struct onenand_chip *this, loff_t addr);
+int flexonenand_region(struct mtd_info *mtd, loff_t addr);
#endif /* __LINUX_MTD_ONENAND_H */
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index 07fed1c..8449a3c 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -67,6 +67,9 @@
/*
* Device ID Register F001h (R)
*/
+#define DEVICE_IS_FLEXONENAND (1 << 9)
+#define FLEXONENAND_PI_MASK (0x3ff)
+#define FLEXONENAND_PI_UNLOCK_SHIFT (14)
#define ONENAND_DEVICE_DENSITY_MASK (0xf)
#define ONENAND_DEVICE_DENSITY_SHIFT (4)
#define ONENAND_DEVICE_IS_DDP (1 << 3)
@@ -84,6 +87,11 @@
#define ONENAND_VERSION_PROCESS_SHIFT (8)
/*
+ * Technology Register F006h (R)
+ */
+#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0)
+
+/*
* Start Address 1 F100h (R/W)
*/
#define ONENAND_DDP_SHIFT (15)
@@ -93,7 +101,7 @@
/*
* Start Address 8 F107h (R/W)
*/
-#define ONENAND_FPA_MASK (0x3f)
+#define ONENAND_FPA_MASK (0x7f)
#define ONENAND_FPA_SHIFT (2)
#define ONENAND_FSA_MASK (0x03)
@@ -105,7 +113,7 @@
#define ONENAND_BSA_BOOTRAM (0 << 2)
#define ONENAND_BSA_DATARAM0 (2 << 2)
#define ONENAND_BSA_DATARAM1 (3 << 2)
-#define ONENAND_BSC_MASK (0x03)
+#define ONENAND_BSC_MASK (0x07)
/*
* Command Register F220h (R/W)
@@ -125,9 +133,14 @@
#define ONENAND_CMD_ERASE_VERIFY (0x71)
#define ONENAND_CMD_RESET (0xF0)
#define ONENAND_CMD_READID (0x90)
+#define FLEXONENAND_CMD_RESET (0xF3)
+#define FLEXONENAND_CMD_PI_UPDATE (0x05)
+#define FLEXONENAND_CMD_PI_ACCESS (0x66)
+#define FLEXONENAND_CMD_RECOVER_LSB (0x05)
/* NOTE: Those are not *REAL* commands */
#define ONENAND_CMD_BUFFERRAM (0x1978)
+#define FLEXONENAND_CMD_READ_PI (0x1985)
/*
* System Configuration 1 Register F221h (R, R/W)
@@ -190,5 +203,6 @@
#define ONENAND_ECC_2BIT (1 << 1)
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
+#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
#endif /* __ONENAND_REG_H */
diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h
index 1016675..d1d9a96 100644
--- a/include/linux/mtd/partitions.h
+++ b/include/linux/mtd/partitions.h
@@ -38,8 +38,8 @@
struct mtd_partition {
char *name; /* identifier string */
- u_int32_t size; /* partition size */
- u_int32_t offset; /* offset within the master MTD space */
+ uint64_t size; /* partition size */
+ uint64_t offset; /* offset within the master MTD space */
u_int32_t mask_flags; /* master MTD flags to mask out for this partition */
struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/
struct mtd_info **mtdp; /* pointer to store the MTD object */
diff --git a/include/mb862xx.h b/include/mb862xx.h
index 43f01e7..009da03 100644
--- a/include/mb862xx.h
+++ b/include/mb862xx.h
@@ -32,6 +32,8 @@
#define PCI_DEVICE_ID_CORAL_P 0x2019
#define PCI_DEVICE_ID_CORAL_PA 0x201E
+#define MB862XX_TYPE_LIME 0x1
+
#define GC_HOST_BASE 0x01fc0000
#define GC_DISP_BASE 0x01fd0000
#define GC_DRAW_BASE 0x01ff0000
@@ -39,6 +41,7 @@
/* Host interface registers */
#define GC_SRST 0x0000002c
#define GC_CCF 0x00000038
+#define GC_CID 0x000000f0
#define GC_MMR 0x0000fffc
/*
@@ -99,6 +102,7 @@
#define GC_FC 0x00000480
#define GC_BC 0x00000484
#define GC_FIFO 0x000004a0
+#define GC_REV 0x00008084
#define GC_GEO_FIFO 0x00008400
typedef struct {
@@ -106,6 +110,7 @@ typedef struct {
unsigned int value;
} gdc_regs;
+int mb862xx_probe(unsigned int addr);
const gdc_regs *board_get_regs (void);
unsigned int board_video_init (void);
void board_backlight_switch(int);
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index 49da9d0..92279d5 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -23,6 +23,7 @@ struct erase_info;
struct onenand_chip;
extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
/* board */
extern void onenand_board_init(struct mtd_info *);
@@ -38,6 +39,15 @@ extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
extern char *onenand_print_device_info(int device, int version);
+extern unsigned onenand_block(struct onenand_chip *this, loff_t addr);
+
+extern loff_t onenand_addr(struct onenand_chip *this, int block);
+
+extern int flexonenand_region(struct mtd_info *mtd, loff_t addr);
+
+extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
+ int boundary, int lock);
+
/* S3C64xx */
extern void s3c64xx_onenand_init(struct mtd_info *);
extern void s3c64xx_set_width_regs(struct onenand_chip *);
diff --git a/include/pca9564.h b/include/pca9564.h
new file mode 100644
index 0000000..3e75259
--- /dev/null
+++ b/include/pca9564.h
@@ -0,0 +1,50 @@
+/*
+ * File: include/pca9564.h
+ * Author:
+ *
+ * Created: 2009-06-23
+ * Description: PCA9564 i2c bridge driver
+ *
+ * Modified:
+ * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ *
+ * Bugs:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PCA9564_H
+#define _PCA9564_H
+
+/* Clock speeds for the bus */
+#define PCA_CON_330kHz 0x00
+#define PCA_CON_288kHz 0x01
+#define PCA_CON_217kHz 0x02
+#define PCA_CON_146kHz 0x03
+#define PCA_CON_88kHz 0x04
+#define PCA_CON_59kHz 0x05
+#define PCA_CON_44kHz 0x06
+#define PCA_CON_36kHz 0x07
+
+#define PCA_CON_AA 0x80 /* Assert Acknowledge */
+#define PCA_CON_ENSIO 0x40 /* Enable */
+#define PCA_CON_STA 0x20 /* Start */
+#define PCA_CON_STO 0x10 /* Stop */
+#define PCA_CON_SI 0x08 /* Serial Interrupt */
+#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */
+
+#endif
+
diff --git a/include/ppc405.h b/include/ppc405.h
index 508c77b..bc2d051 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -566,25 +566,6 @@
#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IIC0_CLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
-/*-----------------------------------------------------------------------------
| UART Register Offsets
'----------------------------------------------------------------------------*/
#define DATA_REG 0x00
diff --git a/include/ppc440.h b/include/ppc440.h
index e54a977..e60fa13 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1276,7 +1276,8 @@
#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
#endif /* defined(CONFIG_440GP) */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
@@ -1713,25 +1714,6 @@
#endif
/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IIC0_CLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
-/*-----------------------------------------------------------------------------
| PCI Internal Registers et. al. (accessed via plb)
+----------------------------------------------------------------------------*/
#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 5024db4..ee30a4c 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -100,12 +100,6 @@
#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
#if defined(CONFIG_440)
-/*
- * Enable long long (%ll ...) printf format on 440 PPC's since most of
- * them support 36bit physical addressing
- */
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
#include <ppc440.h>
#else
#include <ppc405.h>
diff --git a/include/s3c24x0.h b/include/s3c24x0.h
deleted file mode 100644
index 56a551a..0000000
--- a/include/s3c24x0.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c24x0.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C24X0 SoC
- ************************************************/
-
-#ifndef __S3C24X0_H__
-#define __S3C24X0_H__
-
-typedef volatile u8 S3C24X0_REG8;
-typedef volatile u16 S3C24X0_REG16;
-typedef volatile u32 S3C24X0_REG32;
-
-/* Memory controller (see manual chapter 5) */
-struct s3c24x0_memctl {
- S3C24X0_REG32 BWSCON;
- S3C24X0_REG32 BANKCON[8];
- S3C24X0_REG32 REFRESH;
- S3C24X0_REG32 BANKSIZE;
- S3C24X0_REG32 MRSRB6;
- S3C24X0_REG32 MRSRB7;
-};
-
-
-/* USB HOST (see manual chapter 12) */
-struct s3c24x0_usb_host {
- S3C24X0_REG32 HcRevision;
- S3C24X0_REG32 HcControl;
- S3C24X0_REG32 HcCommonStatus;
- S3C24X0_REG32 HcInterruptStatus;
- S3C24X0_REG32 HcInterruptEnable;
- S3C24X0_REG32 HcInterruptDisable;
- S3C24X0_REG32 HcHCCA;
- S3C24X0_REG32 HcPeriodCuttendED;
- S3C24X0_REG32 HcControlHeadED;
- S3C24X0_REG32 HcControlCurrentED;
- S3C24X0_REG32 HcBulkHeadED;
- S3C24X0_REG32 HcBuldCurrentED;
- S3C24X0_REG32 HcDoneHead;
- S3C24X0_REG32 HcRmInterval;
- S3C24X0_REG32 HcFmRemaining;
- S3C24X0_REG32 HcFmNumber;
- S3C24X0_REG32 HcPeriodicStart;
- S3C24X0_REG32 HcLSThreshold;
- S3C24X0_REG32 HcRhDescriptorA;
- S3C24X0_REG32 HcRhDescriptorB;
- S3C24X0_REG32 HcRhStatus;
- S3C24X0_REG32 HcRhPortStatus1;
- S3C24X0_REG32 HcRhPortStatus2;
-};
-
-
-/* INTERRUPT (see manual chapter 14) */
-struct s3c24x0_interrupt {
- S3C24X0_REG32 SRCPND;
- S3C24X0_REG32 INTMOD;
- S3C24X0_REG32 INTMSK;
- S3C24X0_REG32 PRIORITY;
- S3C24X0_REG32 INTPND;
- S3C24X0_REG32 INTOFFSET;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 SUBSRCPND;
- S3C24X0_REG32 INTSUBMSK;
-#endif
-};
-
-
-/* DMAS (see manual chapter 8) */
-struct s3c24x0_dma {
- S3C24X0_REG32 DISRC;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DISRCC;
-#endif
- S3C24X0_REG32 DIDST;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DIDSTC;
-#endif
- S3C24X0_REG32 DCON;
- S3C24X0_REG32 DSTAT;
- S3C24X0_REG32 DCSRC;
- S3C24X0_REG32 DCDST;
- S3C24X0_REG32 DMASKTRIG;
-#ifdef CONFIG_S3C2400
- S3C24X0_REG32 res[1];
-#endif
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 res[7];
-#endif
-};
-
-struct s3c24x0_dmas {
- struct s3c24x0_dma dma[4];
-};
-
-
-/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
-/* (see S3C2410 manual chapter 7) */
-struct s3c24x0_clock_power {
- S3C24X0_REG32 LOCKTIME;
- S3C24X0_REG32 MPLLCON;
- S3C24X0_REG32 UPLLCON;
- S3C24X0_REG32 CLKCON;
- S3C24X0_REG32 CLKSLOW;
- S3C24X0_REG32 CLKDIVN;
-};
-
-
-/* LCD CONTROLLER (see manual chapter 15) */
-struct s3c24x0_lcd {
- S3C24X0_REG32 LCDCON1;
- S3C24X0_REG32 LCDCON2;
- S3C24X0_REG32 LCDCON3;
- S3C24X0_REG32 LCDCON4;
- S3C24X0_REG32 LCDCON5;
- S3C24X0_REG32 LCDSADDR1;
- S3C24X0_REG32 LCDSADDR2;
- S3C24X0_REG32 LCDSADDR3;
- S3C24X0_REG32 REDLUT;
- S3C24X0_REG32 GREENLUT;
- S3C24X0_REG32 BLUELUT;
- S3C24X0_REG32 res[8];
- S3C24X0_REG32 DITHMODE;
- S3C24X0_REG32 TPAL;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 LCDINTPND;
- S3C24X0_REG32 LCDSRCPND;
- S3C24X0_REG32 LCDINTMSK;
- S3C24X0_REG32 LPCSEL;
-#endif
-};
-
-
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
- S3C24X0_REG32 NFCONF;
- S3C24X0_REG32 NFCMD;
- S3C24X0_REG32 NFADDR;
- S3C24X0_REG32 NFDATA;
- S3C24X0_REG32 NFSTAT;
- S3C24X0_REG32 NFECC;
-};
-
-
-/* UART (see manual chapter 11) */
-struct s3c24x0_uart {
- S3C24X0_REG32 ULCON;
- S3C24X0_REG32 UCON;
- S3C24X0_REG32 UFCON;
- S3C24X0_REG32 UMCON;
- S3C24X0_REG32 UTRSTAT;
- S3C24X0_REG32 UERSTAT;
- S3C24X0_REG32 UFSTAT;
- S3C24X0_REG32 UMSTAT;
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 URXH;
-#else /* Little Endian */
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 URXH;
- S3C24X0_REG8 res2[3];
-#endif
- S3C24X0_REG32 UBRDIV;
-};
-
-
-/* PWM TIMER (see manual chapter 10) */
-struct s3c24x0_timer {
- S3C24X0_REG32 TCNTB;
- S3C24X0_REG32 TCMPB;
- S3C24X0_REG32 TCNTO;
-};
-
-struct s3c24x0_timers {
- S3C24X0_REG32 TCFG0;
- S3C24X0_REG32 TCFG1;
- S3C24X0_REG32 TCON;
- struct s3c24x0_timer ch[4];
- S3C24X0_REG32 TCNTB4;
- S3C24X0_REG32 TCNTO4;
-};
-
-
-/* USB DEVICE (see manual chapter 13) */
-struct s3c24x0_usb_dev_fifos {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 EP_FIFO_REG;
-#else /* little endian */
- S3C24X0_REG8 EP_FIFO_REG;
- S3C24X0_REG8 res[3];
-#endif
-};
-
-struct s3c24x0_usb_dev_dmas {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
-#else /* little endian */
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
- S3C24X0_REG8 res6[3];
-#endif
-};
-
-struct s3c24x0_usb_device {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res4[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res6[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
-#else /* little endian */
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res3[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res5[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res9[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
- S3C24X0_REG8 res16[3];
-#endif /* __BIG_ENDIAN */
- struct s3c24x0_usb_dev_fifos fifo[5];
- struct s3c24x0_usb_dev_dmas dma[5];
-};
-
-
-/* WATCH DOG TIMER (see manual chapter 18) */
-struct s3c24x0_watchdog {
- S3C24X0_REG32 WTCON;
- S3C24X0_REG32 WTDAT;
- S3C24X0_REG32 WTCNT;
-};
-
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
- S3C24X0_REG32 IICCON;
- S3C24X0_REG32 IICSTAT;
- S3C24X0_REG32 IICADD;
- S3C24X0_REG32 IICDS;
-};
-
-
-/* IIS (see manual chapter 21) */
-struct s3c24x0_i2s {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 IISFIFO;
-#else /* little endian */
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFIFO;
- S3C24X0_REG16 res5;
-#endif
-};
-
-
-/* I/O PORT (see manual chapter 9) */
-struct s3c24x0_gpio {
-#ifdef CONFIG_S3C2400
- S3C24X0_REG32 PACON;
- S3C24X0_REG32 PADAT;
-
- S3C24X0_REG32 PBCON;
- S3C24X0_REG32 PBDAT;
- S3C24X0_REG32 PBUP;
-
- S3C24X0_REG32 PCCON;
- S3C24X0_REG32 PCDAT;
- S3C24X0_REG32 PCUP;
-
- S3C24X0_REG32 PDCON;
- S3C24X0_REG32 PDDAT;
- S3C24X0_REG32 PDUP;
-
- S3C24X0_REG32 PECON;
- S3C24X0_REG32 PEDAT;
- S3C24X0_REG32 PEUP;
-
- S3C24X0_REG32 PFCON;
- S3C24X0_REG32 PFDAT;
- S3C24X0_REG32 PFUP;
-
- S3C24X0_REG32 PGCON;
- S3C24X0_REG32 PGDAT;
- S3C24X0_REG32 PGUP;
-
- S3C24X0_REG32 OPENCR;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 EXTINT;
-#endif
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 GPACON;
- S3C24X0_REG32 GPADAT;
- S3C24X0_REG32 res1[2];
- S3C24X0_REG32 GPBCON;
- S3C24X0_REG32 GPBDAT;
- S3C24X0_REG32 GPBUP;
- S3C24X0_REG32 res2;
- S3C24X0_REG32 GPCCON;
- S3C24X0_REG32 GPCDAT;
- S3C24X0_REG32 GPCUP;
- S3C24X0_REG32 res3;
- S3C24X0_REG32 GPDCON;
- S3C24X0_REG32 GPDDAT;
- S3C24X0_REG32 GPDUP;
- S3C24X0_REG32 res4;
- S3C24X0_REG32 GPECON;
- S3C24X0_REG32 GPEDAT;
- S3C24X0_REG32 GPEUP;
- S3C24X0_REG32 res5;
- S3C24X0_REG32 GPFCON;
- S3C24X0_REG32 GPFDAT;
- S3C24X0_REG32 GPFUP;
- S3C24X0_REG32 res6;
- S3C24X0_REG32 GPGCON;
- S3C24X0_REG32 GPGDAT;
- S3C24X0_REG32 GPGUP;
- S3C24X0_REG32 res7;
- S3C24X0_REG32 GPHCON;
- S3C24X0_REG32 GPHDAT;
- S3C24X0_REG32 GPHUP;
- S3C24X0_REG32 res8;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 DCLKCON;
- S3C24X0_REG32 EXTINT0;
- S3C24X0_REG32 EXTINT1;
- S3C24X0_REG32 EXTINT2;
- S3C24X0_REG32 EINTFLT0;
- S3C24X0_REG32 EINTFLT1;
- S3C24X0_REG32 EINTFLT2;
- S3C24X0_REG32 EINTFLT3;
- S3C24X0_REG32 EINTMASK;
- S3C24X0_REG32 EINTPEND;
- S3C24X0_REG32 GSTATUS0;
- S3C24X0_REG32 GSTATUS1;
- S3C24X0_REG32 GSTATUS2;
- S3C24X0_REG32 GSTATUS3;
- S3C24X0_REG32 GSTATUS4;
-#endif
-};
-
-
-/* RTC (see manual chapter 17) */
-struct s3c24x0_rtc {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[67];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res3[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res17[3];
- S3C24X0_REG8 BCDYEAR;
-#else /* little endian */
- S3C24X0_REG8 res0[64];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res2[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDYEAR;
- S3C24X0_REG8 res17[3];
-#endif
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2400_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCDAT;
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2410_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCTSC;
- S3C24X0_REG32 ADCDLY;
- S3C24X0_REG32 ADCDAT0;
- S3C24X0_REG32 ADCDAT1;
-};
-
-
-/* SPI (see manual chapter 22) */
-struct s3c24x0_spi_channel {
- S3C24X0_REG8 SPCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 SPSTA;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 SPPIN;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 SPPRE;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 SPTDAT;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 SPRDAT;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 res7[16];
-};
-
-struct s3c24x0_spi {
- struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
-};
-
-
-/* MMC INTERFACE (see S3C2400 manual chapter 19) */
-struct s3c2400_mmc {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG16 res7;
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 res10;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 MMDAT;
-#else
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG16 res7;
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG16 res10;
- S3C24X0_REG8 MMDAT;
- S3C24X0_REG8 res11[3];
-#endif
-};
-
-
-/* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
- S3C24X0_REG32 SDICON;
- S3C24X0_REG32 SDIPRE;
- S3C24X0_REG32 SDICARG;
- S3C24X0_REG32 SDICCON;
- S3C24X0_REG32 SDICSTA;
- S3C24X0_REG32 SDIRSP0;
- S3C24X0_REG32 SDIRSP1;
- S3C24X0_REG32 SDIRSP2;
- S3C24X0_REG32 SDIRSP3;
- S3C24X0_REG32 SDIDTIMER;
- S3C24X0_REG32 SDIBSIZE;
- S3C24X0_REG32 SDIDCON;
- S3C24X0_REG32 SDIDCNT;
- S3C24X0_REG32 SDIDSTA;
- S3C24X0_REG32 SDIFSTA;
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 SDIDAT;
-#else
- S3C24X0_REG8 SDIDAT;
- S3C24X0_REG8 res[3];
-#endif
- S3C24X0_REG32 SDIIMSK;
-};
-
-#endif /*__S3C24X0_H__*/