summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorTang Yuantian <Yuantian.Tang@freescale.com>2014-11-21 11:17:15 +0800
committerYork Sun <yorksun@freescale.com>2014-12-11 09:41:18 -0800
commita7787b78503a2c67fe02f1fcdd995fb6f3830f4b (patch)
tree26184f7b53fe7c7771f9de0a3505ece5054fa543 /include
parentda5ce448c731321ba8cad5502a35c669b5e1bf8c (diff)
downloadu-boot-imx-a7787b78503a2c67fe02f1fcdd995fb6f3830f4b.zip
u-boot-imx-a7787b78503a2c67fe02f1fcdd995fb6f3830f4b.tar.gz
u-boot-imx-a7787b78503a2c67fe02f1fcdd995fb6f3830f4b.tar.bz2
fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/fsl_ddr_sdram.h12
1 files changed, 9 insertions, 3 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 5b03c14..095b33e 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -114,6 +114,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_BI 0x00000001
+#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG2_D_INIT 0x00000010
#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
#define SDRAM_CFG2_ODT_NEVER 0
@@ -163,6 +164,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
@@ -202,6 +204,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define DDR_CDR_ODT_120ohm 0x6
#endif
+#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
@@ -414,9 +418,11 @@ static int __board_need_mem_reset(void)
int board_need_mem_reset(void)
__attribute__((weak, alias("__board_need_mem_reset")));
-void __weak board_mem_sleep_setup(void)
-{
-}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void);
+bool is_warm_boot(void);
+int fsl_dp_resume(void);
+#endif
/*
* The 85xx boards have a common prototype for fixed_sdram so put the