summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorMasahiro Yamada <yamada.m@jp.panasonic.com>2014-04-04 15:25:02 +0900
committerTom Rini <trini@ti.com>2014-04-18 10:42:29 -0400
commita146e8b189abf73b8bac0bfa9c8c3c1b3bfe5507 (patch)
tree6a9eeb210b7141ba94a1ba6722e82fe80631867f /include
parente1b7e1e3cfa8db7edfa494709ed2d477f73c2b66 (diff)
downloadu-boot-imx-a146e8b189abf73b8bac0bfa9c8c3c1b3bfe5507.zip
u-boot-imx-a146e8b189abf73b8bac0bfa9c8c3c1b3bfe5507.tar.gz
u-boot-imx-a146e8b189abf73b8bac0bfa9c8c3c1b3bfe5507.tar.bz2
powerpc: remove NX823 board support
Enough time has passed since this board was moved to Orphan. Remove. - Remove board/nx823/* - Remove include/configs/NX823.h - Clean-up ifdef(CONFIG_NX823) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-generic/u-boot.h3
-rw-r--r--include/commproc.h27
-rw-r--r--include/configs/NX823.h344
3 files changed, 0 insertions, 374 deletions
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index e781967..c18e4ca 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -108,9 +108,6 @@ typedef struct bd_info {
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
-#if defined(CONFIG_NX823)
- unsigned char bi_sernum[8];
-#endif
#if defined(CONFIG_4xx)
#if defined(CONFIG_440GX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
diff --git a/include/commproc.h b/include/commproc.h
index c10a79c..12b9421 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -888,33 +888,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00003E00)
#endif /* CONFIG_LWMON */
-/*** NX823 ***********************************************/
-
-#if defined(CONFIG_NX823)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
-
-#endif /* CONFIG_NX823 */
-
/*** MBX ************************************************************/
#ifdef CONFIG_MBX
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
deleted file mode 100644
index 6d468df..0000000
--- a/include/configs/NX823.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-/*#define CONFIG_VIDEO 1 */
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
-#define CONFIG_BOOTARGS "ramdisk_size=8000 "\
- "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
- "nfsaddrs=10.77.77.20:10.77.77.250"
-#define CONFIG_BOOTCOMMAND "bootm 400e0000"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#undef CONFIG_WATCHDOG /* watchdog disabled, for now */
-#define CONFIG_SOURCE
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_SOURCE
-
-
-/* call various generic functions */
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define xEMBED
-#ifdef EMBED
-#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */
-#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE
-#else
-#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */
-#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
-#endif
-
-#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */
-#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */
-#define CONFIG_SYS_FLASH_SN_BYTES 8
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 12-30
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 12-16
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 12-18
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 12-23
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-#define MPC8XX_SPEED 66666666L
-#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */
-#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
-#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
-#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 5-3
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_8_CLK )
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-/*
- * BR1/2 and OR1/2 (SDRAM)
- */
-#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM)
-
-#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* IO and memory mapped stuff */
-#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */
-#define NX823_IO_BASE 0xFF000000 /* start of IO */
-#define GPOUT_OFFSET (3<<16)
-#define QUART_OFFSET (4<<16)
-#define VIDAC_OFFSET (5<<16)
-#define CPLD_OFFSET (6<<16)
-#define SED1386_OFFSET (7<<16)
-
-/*
- * BR3 and OR3 (general purpose output latches)
- */
-#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET)
-#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI)
-#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING)
-#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V)
-
-/*
- * BR4 and OR4 (QUART)
- */
-#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET)
-#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
-#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
-#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V)
-
-/*
- * BR5 and OR5 (Video DAC)
- */
-#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET)
-#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
-#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V)
-
-/*
- * BR6 and OR6 (CPLD)
- * FIXME timing not verified for CPLD
- */
-#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET)
-#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
-#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
-#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V )
-
-/*
- * BR7 and OR7 (SED1386)
- * FIXME timing not verified for SED controller
- */
-#define SED1386_BASE 0xF7000000
-#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA)
-#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
-#define CONFIG_ETHADDR 00:10:20:30:40:50
-#define CONFIG_IPADDR 10.77.77.20
-#define CONFIG_SERVERIP 10.77.77.250
-
-#endif /* __CONFIG_H */