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authorJason <r64343@freescale.com>2010-03-17 16:41:56 +0800
committerJason <r64343@freescale.com>2010-03-17 18:13:37 +0800
commit762d994929deb79569986bda8e4d7b56e06d14f0 (patch)
treef853eb6f029a9ab6683415863fbe85b4799d71cc /include
parent029aff138902466bdfc1e62c761e89f8d37e83ea (diff)
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ENGR00121202 Add uboot support for MX53
Add uboot support for MX53 Signed-off-by:Jason Liu <r64343@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-mx53/imx_spi_nor.h70
-rw-r--r--include/asm-arm/arch-mx53/iomux.h249
-rw-r--r--include/asm-arm/arch-mx53/mx53.h422
-rw-r--r--include/asm-arm/arch-mx53/mx53_pins.h374
-rw-r--r--include/asm-arm/mach-types.h13
-rw-r--r--include/configs/mx53_evk.h225
6 files changed, 1353 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mx53/imx_spi_nor.h b/include/asm-arm/arch-mx53/imx_spi_nor.h
new file mode 100644
index 0000000..9425d59
--- /dev/null
+++ b/include/asm-arm/arch-mx53/imx_spi_nor.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_SPI_NOR_H_
+#define _IMX_SPI_NOR_H_
+
+#define READ 0x03 /* tx:1 byte cmd + 3 byte addr;rx:variable bytes */
+#define READ_HS 0x0B /* tx:1 byte cmd + 3 byte addr + 1 byte dummy; */
+#define RDSR 0x05 /* read stat reg 1 byte tx cmd + 1 byte rx status */
+#define RDSR_BUSY (1 << 0) /* 1=write-in-progress (default 0) */
+#define RDSR_WEL (1 << 1) /* 1=write enable (default 0) */
+#define RDSR_BP0 (1 << 2) /* block write prot level (default 1) */
+#define RDSR_BP1 (1 << 3) /* block write prot level (default 1) */
+#define RDSR_BP2 (1 << 4) /* block write prot level (default 1) */
+#define RDSR_BP3 (1 << 5) /* block write prot level (default 1) */
+#define RDSR_AAI (1 << 6) /* 1=AAI prog mode; 0=byte prog (def 0) */
+#define RDSR_BPL (1 << 7) /* 1=BP3,BP2,BP1,BP0 RO; 0=R/W (def 0) */
+#define WREN 0x06 /* write enable. 1 byte tx cmd */
+#define WRDI 0x04 /* write disable. 1 byte tx cmd */
+#define EWSR 0x50 /* Enable write status. 1 byte tx cmd */
+#define WRSR 0x01 /* Write stat reg. 1 byte tx cmd + 1 byte tx val */
+#define ERASE_4K 0x20 /* sector erase. 1 byte cmd + 3 byte addr */
+#define ERASE_32K 0x52 /* 32K block erase. 1 byte cmd + 3 byte addr */
+#define ERASE_64K 0xD8 /* 64K block erase. 1 byte cmd + 3 byte addr */
+#define ERASE_CHIP 0x60 /* whole chip erase */
+#define BYTE_PROG 0x02 /* all tx: 1 cmd + 3 addr + 1 data */
+#define AAI_PROG 0xAD /* all tx: [1 cmd + 3 addr + 2 data] + RDSR */
+ /* + [1cmd + 2 data] + .. + [WRDI] + [RDSR] */
+#define JEDEC_ID 0x9F /* read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID */
+
+/* Atmel SPI-NOR commands */
+#define WR_2_MEM_DIR 0x82
+#define BUF1_WR 0x84
+#define BUF2_WR 0x87
+#define BUF1_TO_MEM 0x83
+#define BUF2_TO_MEM 0x86
+#define STAT_READ 0xD7
+#define STAT_PG_SZ (1 << 0) /* 1=Page size is 512, 0=Page size is 528 */
+#define STAT_PROT (1 << 1) /* 1=sector protection enabled (default 0) */
+#define STAT_COMP (1 << 6)
+#define STAT_BUSY (1 << 7) /* 1=Device not busy */
+#define CONFIG_REG1 0x3D
+#define CONFIG_REG2 0x2A
+#define CONFIG_REG3 0x80
+#define CONFIG_REG4 0xA6
+
+#define SZ_64K 0x10000
+#define SZ_32K 0x8000
+#define SZ_4K 0x1000
+
+#endif /* _IMX_SPI_NOR_H_ */
diff --git a/include/asm-arm/arch-mx53/iomux.h b/include/asm-arm/arch-mx53/iomux.h
new file mode 100644
index 0000000..2184863
--- /dev/null
+++ b/include/asm-arm/arch-mx53/iomux.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX53_IOMUX_H__
+#define __MACH_MX53_IOMUX_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx53.h>
+#include <asm/arch/mx53_pins.h>
+
+/*!
+ * @file mach-mx53/iomux.h
+ *
+ * @brief I/O Muxing control definitions and functions
+ *
+ * @ingroup GPIO_MX53
+ */
+
+typedef unsigned int iomux_pin_name_t;
+
+/*!
+ * various IOMUX output functions
+ */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
+ IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
+ IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
+ IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
+ IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
+ IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
+ IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
+ IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
+ IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
+ IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/*!
+ * various IOMUX pad functions
+ */
+typedef enum iomux_pad_config {
+ PAD_CTL_SRE_SLOW = 0x0 << 0,
+ PAD_CTL_SRE_FAST = 0x1 << 0,
+ PAD_CTL_DRV_LOW = 0x0 << 1,
+ PAD_CTL_DRV_MEDIUM = 0x1 << 1,
+ PAD_CTL_DRV_HIGH = 0x2 << 1,
+ PAD_CTL_DRV_MAX = 0x3 << 1,
+ PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
+ PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
+ PAD_CTL_100K_PD = 0x0 << 4,
+ PAD_CTL_47K_PU = 0x1 << 4,
+ PAD_CTL_100K_PU = 0x2 << 4,
+ PAD_CTL_22K_PU = 0x3 << 4,
+ PAD_CTL_PUE_KEEPER = 0x0 << 6,
+ PAD_CTL_PUE_PULL = 0x1 << 6,
+ PAD_CTL_PKE_NONE = 0x0 << 7,
+ PAD_CTL_PKE_ENABLE = 0x1 << 7,
+ PAD_CTL_HYS_NONE = 0x0 << 8,
+ PAD_CTL_HYS_ENABLE = 0x1 << 8,
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
+ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
+ PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
+ PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
+} iomux_pad_config_t;
+
+/*!
+ * various IOMUX input select register index
+ */
+typedef enum iomux_input_select {
+ MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, /*0x760*/
+ MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
+ MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT,
+ MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, /*0x780*/
+ MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
+ MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+ MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+ MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+ MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, /*0x7B0*/
+ MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, /*0x7E0*/
+ MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
+ MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
+ MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT,
+ MUX_IN_FEC_FEC_COL_SELECT_INPUT, /*0x800*/
+ MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT,
+ MUX_IN_GPC_PMIC_RDY_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT,
+ MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+ MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
+ MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, /*0x840*/
+ MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT,
+ MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT,
+ MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT,
+ MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
+ MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
+ MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
+ MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT, /*0x870*/
+ MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
+} iomux_input_select_t;
+
+/*!
+ * various IOMUX input functions
+ */
+typedef enum iomux_input_config {
+ INPUT_CTL_PATH0 = 0x0,
+ INPUT_CTL_PATH1,
+ INPUT_CTL_PATH2,
+ INPUT_CTL_PATH3,
+ INPUT_CTL_PATH4,
+ INPUT_CTL_PATH5,
+ INPUT_CTL_PATH6,
+ INPUT_CTL_PATH7,
+} iomux_input_config_t;
+
+struct mxc_iomux_pin_cfg {
+ iomux_pin_name_t pin;
+ u8 mux_mode;
+ u16 pad_cfg;
+ u8 in_select;
+ u8 in_mode;
+};
+
+/*!
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param config config as defined in \b #iomux_pin_ocfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+
+/*!
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param config config as defined in \b #iomux_pin_ocfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+
+/*!
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param config the ORed value of elements defined in
+ * \b #iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
+
+/*!
+ * This function gets the current pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return current pad value
+ */
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
+
+/*!
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in
+ * \b #iomux_input_select_t
+ * @param config the binary value of elements defined in \b #iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
+
+#endif /* __MACH_MX53_IOMUX_H__ */
diff --git a/include/asm-arm/arch-mx53/mx53.h b/include/asm-arm/arch-mx53/mx53.h
new file mode 100644
index 0000000..e985357
--- /dev/null
+++ b/include/asm-arm/arch-mx53/mx53.h
@@ -0,0 +1,422 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX53_H__
+#define __ASM_ARCH_MXC_MX53_H__
+
+#define __REG(x) (*((volatile u32 *)(x)))
+#define __REG16(x) (*((volatile u16 *)(x)))
+#define __REG8(x) (*((volatile u8 *)(x)))
+
+ /*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */
+#define IRAM_PARTITIONS 16
+#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */
+
+/*
+ * NFC
+ */
+#define NFC_BASE_ADDR_AXI 0xF7FF0000 /* NAND flash AXI */
+#define NFC_AXI_SIZE SZ_64K
+
+#define TZIC_BASE_ADDR 0x0FFFC000
+
+#define DEBUG_BASE_ADDR 0x40000000
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 0x50000000
+
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define ESAI_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
+#define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*!
+ * defines for SPBA modules
+ */
+#define SPBA_SDHC1 0x04
+#define SPBA_SDHC2 0x08
+#define SPBA_UART3 0x0C
+#define SPBA_CSPI1 0x10
+#define SPBA_SSI2 0x14
+#define SPBA_ESAI 0x18
+#define SPBA_SDHC3 0x20
+#define SPBA_SDHC4 0x24
+#define SPBA_SPDIF 0x28
+#define SPBA_ASRC 0x2C
+#define SPBA_ATA 0x30
+#define SPBA_CTRL 0x3C
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x53F00000
+
+#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
+#define CAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C8000)
+#define CAN2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000CC000)
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
+#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
+#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
+#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x63F00000
+
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
+#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
+#define MLB_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
+#define PTP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000FC000)
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR 0x70000000
+#define CSD1_BASE_ADDR 0xB0000000
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_BASE 0
+#define MXC_INT_RESV0 0
+#define MXC_INT_MMC_SDHC1 1
+#define MXC_INT_MMC_SDHC2 2
+#define MXC_INT_MMC_SDHC3 3
+#define MXC_INT_MMC_SDHC4 4
+#define MXC_INT_DAP 5
+#define MXC_INT_SDMA 6
+#define MXC_INT_IOMUX 7
+#define MXC_INT_NFC 8
+#define MXC_INT_VPU 9
+#define MXC_INT_IPU_ERR 10
+#define MXC_INT_IPU_SYN 11
+#define MXC_INT_GPU 12
+#define MXC_INT_UART4 13
+#define MXC_INT_USB_H1 14
+#define MXC_INT_EMI 15
+#define MXC_INT_USB_H2 16
+#define MXC_INT_USB_H3 17
+#define MXC_INT_USB_OTG 18
+#define MXC_INT_SAHARA_H0 19
+#define MXC_INT_SAHARA_H1 20
+#define MXC_INT_SCC_SMN 21
+#define MXC_INT_SCC_STZ 22
+#define MXC_INT_SCC_SCM 23
+#define MXC_INT_SRTC_NTZ 24
+#define MXC_INT_SRTC_TZ 25
+#define MXC_INT_RTIC 26
+#define MXC_INT_CSU 27
+#define MXC_INT_SATA 28
+#define MXC_INT_SSI1 29
+#define MXC_INT_SSI2 30
+#define MXC_INT_UART1 31
+#define MXC_INT_UART2 32
+#define MXC_INT_UART3 33
+#define MXC_INT_RTC 34
+#define MXC_INT_PTP 35
+#define MXC_INT_CSPI1 36
+#define MXC_INT_CSPI2 37
+#define MXC_INT_CSPI 38
+#define MXC_INT_GPT 39
+#define MXC_INT_EPIT1 40
+#define MXC_INT_EPIT2 41
+#define MXC_INT_GPIO1_INT7 42
+#define MXC_INT_GPIO1_INT6 43
+#define MXC_INT_GPIO1_INT5 44
+#define MXC_INT_GPIO1_INT4 45
+#define MXC_INT_GPIO1_INT3 46
+#define MXC_INT_GPIO1_INT2 47
+#define MXC_INT_GPIO1_INT1 48
+#define MXC_INT_GPIO1_INT0 49
+#define MXC_INT_GPIO1_LOW 50
+#define MXC_INT_GPIO1_HIGH 51
+#define MXC_INT_GPIO2_LOW 52
+#define MXC_INT_GPIO2_HIGH 53
+#define MXC_INT_GPIO3_LOW 54
+#define MXC_INT_GPIO3_HIGH 55
+#define MXC_INT_GPIO4_LOW 56
+#define MXC_INT_GPIO4_HIGH 57
+#define MXC_INT_WDOG1 58
+#define MXC_INT_WDOG2 59
+#define MXC_INT_KPP 60
+#define MXC_INT_PWM1 61
+#define MXC_INT_I2C1 62
+#define MXC_INT_I2C2 63
+#define MXC_INT_I2C3 64
+#define MXC_INT_MLB 65
+#define MXC_INT_ASRC 66
+#define MXC_INT_SPDIF 67
+#define MXC_INT_RESV1 68
+#define MXC_INT_IIM 69
+#define MXC_INT_ATA 70
+#define MXC_INT_CCM1 71
+#define MXC_INT_CCM2 72
+#define MXC_INT_GPC1 73
+#define MXC_INT_GPC2 74
+#define MXC_INT_SRC 75
+#define MXC_INT_NM 76
+#define MXC_INT_PMU 77
+#define MXC_INT_CTI_IRQ 78
+#define MXC_INT_CTI1_TG0 79
+#define MXC_INT_CTI1_TG1 80
+#define MXC_INT_ESAI 81
+#define MXC_INT_CAN1 82
+#define MXC_INT_CAN2 83
+#define MXC_INT_GPU2_IRQ 84
+#define MXC_INT_GPU2_BUSY 85
+#define MXC_INT_UART5 86
+#define MXC_INT_FEC 87
+#define MXC_INT_OWIRE 88
+#define MXC_INT_CTI1_TG2 89
+#define MXC_INT_SJC 90
+#define MXC_INT_RESV2 91
+#define MXC_INT_TVE 92
+#define MXC_INT_FIRI 93
+#define MXC_INT_PWM2 94
+#define MXC_INT_RESV3 95
+#define MXC_INT_SSI3 96
+#define MXC_INT_RESV4 97
+#define MXC_INT_CTI1_TG3 98
+#define MXC_INT_RESV5 99
+#define MXC_INT_VPU_IDLE 100
+#define MXC_INT_EMI_NFC 101
+#define MXC_INT_GPU_IDLE 102
+#define MXC_INT_GPIO5_LOW 103
+#define MXC_INT_GPIO5_HIGH 104
+#define MXC_INT_GPIO6_LOW 105
+#define MXC_INT_GPIO6_HIGH 106
+#define MXC_INT_GPIO7_LOW 107
+#define MXC_INT_GPIO7_HIGH 108
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR 0x00
+#define GPIO_GDIR 0x04
+#define GPIO_PSR 0x08
+#define GPIO_ICR1 0x0C
+#define GPIO_ICR2 0x10
+#define GPIO_IMR 0x14
+#define GPIO_ISR 0x18
+#define GPIO_INT_LOW_LEV 0x0
+#define GPIO_INT_HIGH_LEV 0x1
+#define GPIO_INT_RISE_EDGE 0x2
+#define GPIO_INT_FALL_EDGE 0x3
+#define GPIO_INT_NONE 0x4
+
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR 0x14
+#define CLKCTL_CBCMR 0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR 0x30
+#define CLKCTL_CHSCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR 0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR 0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6C
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7C
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define CHIP_REV_1_0 0x10
+#define PLATFORM_ICGC 0x14
+
+/* Assuming 24MHz input clock with doubler ON */
+/* MFI PDF */
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (48 - 1)
+#define DP_MFN_850 41
+
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_800 (3 - 1)
+#define DP_MFN_800 1
+
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define DP_MFD_700 (24 - 1)
+#define DP_MFN_700 7
+
+#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_600 (4 - 1)
+#define DP_MFN_600 1
+
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_665 (96 - 1)
+#define DP_MFN_665 89
+
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define DP_MFD_532 (24 - 1)
+#define DP_MFN_532 13
+
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define DP_MFD_400 (3 - 1)
+#define DP_MFN_400 1
+
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define DP_MFD_216 (4 - 1)
+#define DP_MFN_216 3
+
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+#ifndef __ASSEMBLER__
+
+enum boot_device {
+ UNKNOWN_BOOT,
+ NAND_BOOT,
+ SPI_NOR_BOOT,
+ MMC_BOOT,
+};
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_A_CLK,
+ MXC_AXI_B_CLK,
+ MXC_EMI_SLOW_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+};
+
+enum mxc_peri_clocks {
+ MXC_UART1_BAUD,
+ MXC_UART2_BAUD,
+ MXC_UART3_BAUD,
+ MXC_SSI1_BAUD,
+ MXC_SSI2_BAUD,
+ MXC_CSI_BAUD,
+ MXC_MSTICK1_CLK,
+ MXC_MSTICK2_CLK,
+ MXC_SPI1_CLK,
+ MXC_SPI2_CLK,
+};
+
+extern unsigned int mxc_get_clock(enum mxc_clock clk);
+extern unsigned int get_board_rev(void);
+extern int is_soc_rev(int rev);
+extern enum boot_device get_boot_device(void);
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_MXC_MX53_H__ */
diff --git a/include/asm-arm/arch-mx53/mx53_pins.h b/include/asm-arm/arch-mx53/mx53_pins.h
new file mode 100644
index 0000000..e5afcd7
--- /dev/null
+++ b/include/asm-arm/arch-mx53/mx53_pins.h
@@ -0,0 +1,374 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_MXC_MX53_PINS_H__
+#define __ASM_ARCH_MXC_MX53_PINS_H__
+
+/*!
+ * @file arch-mxc/mx53_pins.h
+ *
+ * @brief MX53 I/O Pin List
+ *
+ * @ingroup GPIO_MX53
+ */
+
+#ifndef __ASSEMBLY__
+
+/*!
+ * @name IOMUX/PAD Bit field definitions
+ */
+
+/*! @{ */
+
+/*!
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
+ * -------------------------------------------------------------------
+ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 9 contains MUX_I used to identify the register
+ * offset (0-based. base is IOMUX_module_base) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
+ * similar field definitions are used for the pad control register.
+ * For example, the MX53_PIN_GPIO_19 is defined in the enumeration:
+ * ( (0x20 - MUX_I_START) << MUX_I)|( (0x348 - PAD_I_START) << PAD_I)
+ * It means the mux control register is at register offset 0x20. The pad control
+ * register offset is: 0x348 and also occupy the least significant bits
+ * within the register.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I 0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I 10
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent which
+ * mux mode is for GPIO (0-based)
+ */
+#define GPIO_I 21
+
+#define MUX_IO_P 29
+#define MUX_IO_I 24
+
+#define NON_GPIO_PORT 0x7
+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
+
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define NON_PAD_I PIN_TO_PAD_MASK
+#define MUX_I_START 0x0020
+#define PAD_I_START 0x348
+#define INPUT_CTL_START 0x730
+#define MUX_I_END (PAD_I_START - 4)
+
+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+ ((mi) << MUX_I) | \
+ ((pi - PAD_I_START) << PAD_I) | \
+ ((ga) << GPIO_I))
+
+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
+ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
+ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
+
+/*! @} End IOMUX/PAD Bit field definitions */
+
+/*!
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX53 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+ MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
+ MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
+ MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
+ MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
+ MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
+ MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
+ MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
+ MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
+ MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
+ MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
+ MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
+ MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
+ MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
+ MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
+ MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
+ MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
+ MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
+ MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
+ MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
+ MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
+ MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
+ MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
+ MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
+ MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
+ MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
+ MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
+ MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
+ MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
+ MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
+ MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
+ MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
+ MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
+ MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
+ MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
+ MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
+ MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
+ MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
+ MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
+ MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
+ MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
+ MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
+ MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
+ MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
+ MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
+ MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
+ MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
+ MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
+ MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
+ MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
+ MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
+ MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
+ MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
+ MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
+ MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
+ MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
+ MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
+ MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
+ MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
+ MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
+ MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
+ MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
+ MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
+ MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
+ MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
+ MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
+ MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
+ MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
+ MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
+ MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
+ MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
+ MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
+ MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
+ MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
+ MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
+ MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
+ MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
+ MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
+ MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
+ MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
+ MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
+ MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
+ MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
+ MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
+ MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
+ MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
+ MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
+ MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
+ MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
+ MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
+ MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
+ MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
+ MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
+ MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
+ MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
+ MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
+ MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
+ MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
+ MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
+ MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
+ MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
+ MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
+ MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
+ MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
+ MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
+ MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
+ MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
+ MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
+ MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
+ MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
+ MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
+ MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
+ MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
+ MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
+ MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
+ MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
+ MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
+ MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
+ MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
+ MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
+ MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
+ MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
+ MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
+ MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
+ MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
+ MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
+ MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
+ MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
+ MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
+ MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
+ MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
+ MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
+ MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
+ MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
+ MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
+ MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
+ MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
+ MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
+ MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
+ MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
+ MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
+ MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
+ MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
+ MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
+ MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
+ MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
+ MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
+ MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
+ MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
+ MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
+ MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
+ MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
+ MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
+ MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
+ MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
+ MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
+ MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
+ MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
+ MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
+ MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
+ MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
+ MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
+ MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
+ MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
+ MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
+ MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
+ MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
+ MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
+ MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
+ MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
+ MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
+ MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
+ MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
+ MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
+ MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
+ MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
+ MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
+ MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
+ MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
+ MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
+ MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
+ MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
+ MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
+ MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
+ MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
+ MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
+ MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
+ MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
+ MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
+ MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
+ MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
+ MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
+ MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
+ MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
+ MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
+ MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
+ MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
+ MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
+ MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
+ MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
+ MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
+ MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
+ MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
+ MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
+ MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
+ MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
+ MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
+ MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
+ MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
+ MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
+ MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
+ MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
+ MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
+ MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
+ MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
+ MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
+ MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
+ MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
+ MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
+ MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
+ MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
+ MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
+ MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
+ MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
+ MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
+ MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
+ MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
+ MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
+ MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
+ MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
+ MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
+ MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
+ MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
+ MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
+ MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
+ MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
+ MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
+ MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
+ MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
+ MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
+ MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
+ MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
+ MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
+ MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
+ MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
+ MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
+ MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
+ MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
+ MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
+ MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
+ MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
+ MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
+ MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
+ MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
+ MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
+ MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
+ MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
+ MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_MX53_PINS_H__ */
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 5293d67..dc3ec1a 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -2241,6 +2241,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_OMAP3_WL_FF 2258
#define MACH_TYPE_SIMCOM 2259
#define MACH_TYPE_MCWEBIO 2260
+#define MACH_TYPE_MX53_EVK 2716
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -27406,6 +27407,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_mx51_babbage() (0)
#endif
+#ifdef CONFIG_MACH_MX53_EVK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX53_EVK
+# endif
+# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK)
+#else
+# define machine_is_mx53_evk() (0)
+#endif
+
#ifdef CONFIG_MACH_S3C2440TURKIYE
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
new file mode 100644
index 0000000..010ac76
--- /dev/null
+++ b/include/configs/mx53_evk.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx53.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_SYS_APCS_GNU
+
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_EVK
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX53_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX53_UART 1
+#define CONFIG_MX53_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+#endif
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */