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authorRafal Jaworowski <raj@pollux.denx.de>2005-10-17 02:39:53 +0200
committerRafal Jaworowski <raj@pollux.denx.de>2005-10-17 02:39:53 +0200
commit6902df56a0b493f369153b09d11afcd74a580561 (patch)
tree1f52eec48325cca757cf2ea3d65a448cbecaec9d /include
parent326bf40fb7a4862da5dcc4e166721633b3422835 (diff)
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Add PCI support for the TQM834x board.
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/global_data.h1
-rw-r--r--include/asm-ppc/immap_83xx.h37
-rw-r--r--include/configs/TQM834x.h50
3 files changed, 20 insertions, 68 deletions
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 9681a74..b73af96 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -62,6 +62,7 @@ typedef struct global_data {
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
+ u32 pci_clk;
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index f704db6..6c2c712 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -28,43 +28,6 @@ typedef struct law8349 {
#define LAWBAR_BAR 0xFFFFF000
#define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */
-/*
- * This Macro were moved into mmu.h
- */
-#if 0
-/* 0 The local bus local access window n is disabled. 1 The local bus
- * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
- * combine to identify an address range for this window.
- */
-#define LAWAR_EN 0x80000000
-/* Identifies the size of the window from the starting address. Window
- * size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is
- * undefined.
- */
-#define LAWAR_SIZE 0x0000003F
-#define LAWAR_SIZE_4K 0x0000000B
-#define LAWAR_SIZE_8K 0x0000000C
-#define LAWAR_SIZE_16K 0x0000000D
-#define LAWAR_SIZE_32K 0x0000000E
-#define LAWAR_SIZE_64K 0x0000000F
-#define LAWAR_SIZE_128K 0x00000010
-#define LAWAR_SIZE_256K 0x00000011
-#define LAWAR_SIZE_512K 0x00000012
-#define LAWAR_SIZE_1M 0x00000013
-#define LAWAR_SIZE_2M 0x00000014
-#define LAWAR_SIZE_4M 0x00000015
-#define LAWAR_SIZE_8M 0x00000016
-#define LAWAR_SIZE_16M 0x00000017
-#define LAWAR_SIZE_32M 0x00000018
-#define LAWAR_SIZE_64M 0x00000019
-#define LAWAR_SIZE_128M 0x0000001A
-#define LAWAR_SIZE_256M 0x0000001B
-#define LAWAR_SIZE_512M 0x0000001C
-#define LAWAR_SIZE_1G 0x0000001D
-#define LAWAR_SIZE_2G 0x0000001E
-#define LAWAR_RES ~(LAWAR_EN|LAWAR_SIZE)
-#endif
-
} law8349_t;
/*
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 96a1ad2..0fad36a 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -122,6 +122,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
+
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
/* disable remaining mappings */
@@ -241,7 +242,7 @@ extern int tqm834x_num_flash_banks;
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI
#endif
#define CONFIG_MPC83XX_TSEC1 1
@@ -262,45 +263,32 @@ extern int tqm834x_num_flash_banks;
* General PCI
* Addresses are mapped 1-1.
*/
-/* FIXME: Real PCI support will come in a follow-up update. */
-#undef CONFIG_PCI
-
-#define CFG_PCI1_MEM_BASE 0x80000000
-#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0x00000000
-#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
-
-#define CFG_PCI2_MEM_BASE 0xA0000000
-#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0x00000000
-#define CFG_PCI2_IO_PHYS 0xe3000000
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CONFIG_PCI
+
#if defined(CONFIG_PCI)
-#define PCI_ALL_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* PCI1 host bridge */
+#define CFG_PCI1_MEM_BASE 0xc0000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
+ #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE
+ #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
#endif
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
@@ -418,7 +406,7 @@ extern int tqm834x_num_flash_banks;
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
+ HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\