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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-09-11 09:59:27 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-09-11 09:59:27 +0200
commit5480ac32171ab0e38c48c9f585fa650c7867f6a1 (patch)
tree6672a47e3675e7e79fd0fbf9b491045230b24eed /include
parent68e1747f9c0506159e8ecc9a4feb58e9c65a7b39 (diff)
parent5c18a1cf3e56e0177388258696be4a17a672e9d0 (diff)
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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Conflicts: tools/Makefile
Diffstat (limited to 'include')
-rw-r--r--include/configs/arndale.h255
-rw-r--r--include/configs/exynos5250-dt.h2
-rw-r--r--include/configs/s5p_goni.h3
-rw-r--r--include/configs/smdkc100.h3
-rw-r--r--include/power/max77686_pmic.h26
5 files changed, 288 insertions, 1 deletions
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
new file mode 100644
index 0000000..ed44a04
--- /dev/null
+++ b/include/configs/arndale.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Configuration settings for the SAMSUNG Arndale board.
+ */
+
+#ifndef __CONFIG_ARNDALE_H
+#define __CONFIG_ARNDALE_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
+#define CONFIG_EXYNOS5250
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_ARCH_DEVICE_TREE exynos5250
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR 0x50000000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
+#define CONFIG_SILENT_CONSOLE
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
+
+#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "ARNDALE # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING " for ARNDALE"
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE (512)
+#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+
+#define CONFIG_SPI_BOOTING
+#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
+#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+
+#define CONFIG_IRAM_STACK 0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_HARD_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
+#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_MAX_I2C_NUM 8
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_I2C_EDID
+
+/* PMIC */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX77686
+
+#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE 0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK 1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8f8f85f..8c21909 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -13,7 +13,7 @@
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P /* S5P Family */
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
-#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
+#define CONFIG_EXYNOS5250
#include <asm/arch/cpu.h> /* get chip and board defs */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index d0fafd7..c303244 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -29,6 +29,9 @@
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
+/* Text Base */
+#define CONFIG_SYS_TEXT_BASE 0x34800000
+
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index a572e62..507a5d3 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -34,6 +34,9 @@
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
+/* Text Base */
+#define CONFIG_SYS_TEXT_BASE 0x34800000
+
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index 91b7ba7..c98db1b 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -139,6 +139,32 @@ enum {
EN_LDO = (0x3 << 6),
};
+enum {
+ OPMODE_OFF = 0,
+ OPMODE_STANDBY,
+ OPMODE_LPM,
+ OPMODE_ON,
+};
+
+int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
+int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
+
+#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
+#define MAX77686_LDO_VOLT_MASK 0x3f
+#define MAX77686_LDO_MODE_MASK 0xc0
+#define MAX77686_LDO_MODE_OFF (0x00 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
+#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
+#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
+#define MAX77686_BUCK_MODE_MASK 0x03
+#define MAX77686_BUCK_MODE_SHIFT_1 0x00
+#define MAX77686_BUCK_MODE_SHIFT_2 0x04
+#define MAX77686_BUCK_MODE_OFF 0x00
+#define MAX77686_BUCK_MODE_STANDBY 0x01
+#define MAX77686_BUCK_MODE_LPM 0x02
+#define MAX77686_BUCK_MODE_ON 0x03
+
/* Buck1 1 volt value */
#define MAX77686_BUCK1OUT_1V 0x5
/* Buck1 1.05 volt value */