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authorSandeep Paulraj <s-paulraj@ti.com>2009-05-09 12:35:20 -0400
committerScott Wood <scottwood@freescale.com>2009-07-07 17:58:02 -0500
commit496863b2440dd7cd69a1ad2443a9badd5f8968d1 (patch)
treee5b712bed4d7f5ad803a94918778cbf2be2d6b17 /include
parent0c1684437ef810c503df29e8d73f63191aa63862 (diff)
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NAND DaVinci: Update to ALE/CLE Mask values
All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8 except the DM646x. This was decided by the design team driving the design. This patch updates the CLE and ALE values for DM646x. Updated patches for DM646x will be sent shortly. This applies to u-boot-nand-flash git Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-davinci/nand_defs.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h
index ba75cd6..f202072 100644
--- a/include/asm-arm/arch-davinci/nand_defs.h
+++ b/include/asm-arm/arch-davinci/nand_defs.h
@@ -28,8 +28,13 @@
#include <asm/arch/hardware.h>
+#ifdef CONFIG_SOC_DM646x
+#define MASK_CLE 0x80000
+#define MASK_ALE 0x40000
+#else
#define MASK_CLE 0x10
#define MASK_ALE 0x08
+#endif
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30