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authorKumar Gala <galak@kernel.crashing.org>2009-03-19 02:32:23 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:05:28 -0500
commit418ec8584343f04048e2cc7ee96b6b29be54ad97 (patch)
treedd51d6d73890ab779b24650c09475984dddcc5ce /include
parent01df521217957d77d53c2d570183eded7030938f (diff)
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ppc/p4080: Add support for CoreNet style platform LAWs
On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/fsl_law.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index e06a1a6..31bb754 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -1,8 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
+#define LAW_EN 0x80000000
+
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
@@ -36,6 +46,25 @@ enum law_size {
LAW_SIZE_32G,
};
+#ifdef CONFIG_FSL_CORENET
+enum law_trgt_if {
+ LAW_TRGT_IF_PCIE_1 = 0x00,
+ LAW_TRGT_IF_PCIE_2 = 0x01,
+ LAW_TRGT_IF_PCIE_3 = 0x02,
+ LAW_TRGT_IF_RIO_1 = 0x08,
+ LAW_TRGT_IF_RIO_2 = 0x09,
+
+ LAW_TRGT_IF_DDR_1 = 0x10,
+ LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
+ LAW_TRGT_IF_DDR_INTRLV = 0x14,
+
+ LAW_TRGT_IF_BMAN = 0x18,
+ LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_LBC = 0x1f,
+ LAW_TRGT_IF_QMAN = 0x3c,
+};
+#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
+#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
@@ -64,6 +93,7 @@ enum law_trgt_if {
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
+#endif /* CONFIG_FSL_CORENET */
struct law_entry {
int index;
@@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if
extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
+extern struct law_entry find_law(phys_addr_t addr);
extern void disable_law(u8 idx);
extern void init_laws(void);
extern void print_laws(void);