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authorRoy Zang <tie-fei.zang@freescale.com>2011-01-07 00:06:47 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-01-14 01:32:22 -0600
commit3b4456ec391877a950dd5e98ee20df6560f0e1af (patch)
tree1690d31ee59b2bbc8e6d5db326aac3c06bc43a6b /include
parentd621da0066dff92a76ca3c6fb031a7f823a811f3 (diff)
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fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/configs/P4080DS.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 705b226..a15dd76 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -36,6 +36,7 @@
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_P4080_ERRATUM_SERDES8