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authorHoward Gregory <Greg.Howard@freescale.com>2008-11-04 14:55:33 +0800
committerKim Phillips <kim.phillips@freescale.com>2008-11-19 18:42:54 -0600
commit2f2a5c3714d17f4ead18b713128b7226e0e822f4 (patch)
treeb33da65162c3888af8e1496349c241a1941aa14d /include
parent9b827cf1720acda2473afa516956eab6f7cca9a1 (diff)
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mpc83xx: Improve the performance of DDR memory
modify the CAS timings. my understanding is that these settings decrease various wait times in the DDR interface. Because these wait times are in clock cycles, and the DDR clock on the 8315 RDB runs slower than on some other 83xx platforms, we can dial down these values without a problem, thereby decreasing the latency of memory a little. Signed-off-by: Howard Gregory <Greg.Howard@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8315ERDB.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 1225270..add65f0 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -118,23 +118,23 @@
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
/* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
- | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+ | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
- /* 0x39356222 */
+ /* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
- /* 0x121048c7 */
+ | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
/* 0x03600100 */