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authorTom Rini <trini@konsulko.com>2016-09-22 16:51:19 -0400
committerTom Rini <trini@konsulko.com>2016-09-22 16:51:19 -0400
commit201c9d884dcadb4e76981c30e9915f73de2d09b5 (patch)
treeaf1030f3a441f1538085eaa586e0e8392f2429ab /include
parent82f5279b0cd99a9163d34cfe926d0316d9dc0d37 (diff)
parent4f0b8efa50a543efd407fb8b2e9ad0de49467a15 (diff)
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Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'include')
-rw-r--r--include/configs/rk3288_common.h1
-rw-r--r--include/configs/rk3399_common.h12
-rw-r--r--include/linux/usb/dwc3.h14
3 files changed, 27 insertions, 0 deletions
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 21b6082..e8bf987 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -9,6 +9,7 @@
#include <asm/arch/hardware.h>
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index e9626a5..b026122 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -83,4 +83,16 @@
#endif
+/* enable usb config for usb ether */
+#define CONFIG_USB_HOST_ETHER
+
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_ASIX88179
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RTL8152
+
+/* rockchip xhci host driver */
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
#endif
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 6d1e365..a027446 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -180,7 +180,21 @@ struct dwc3 { /* offset: 0xC100 */
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
+#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
+
+/* Global USB2 PHY Configuration Mask */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
+
+/* Global USB2 PHY Configuration Offset */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
+
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
+ DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
+ DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)