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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-26 08:02:30 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:50 -0500 |
| commit | 1167a2fd56138b716e01370c4267f3b70bf9ffa0 (patch) | |
| tree | 74cfb5d7919a1063de8f7632df44ed81e53c5181 /include | |
| parent | e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e (diff) | |
| download | u-boot-imx-1167a2fd56138b716e01370c4267f3b70bf9ffa0.zip u-boot-imx-1167a2fd56138b716e01370c4267f3b70bf9ffa0.tar.gz u-boot-imx-1167a2fd56138b716e01370c4267f3b70bf9ffa0.tar.bz2 | |
FSL DDR: Convert MPC8544DS to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8544DS.h | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 9a77b7b..5738192 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -46,15 +46,6 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_DLL -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_DDR_ECC_CMD #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ /* @@ -64,8 +55,6 @@ */ #define CONFIG_ASSUME_AMD_FLASH -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -101,17 +90,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD + +#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +/* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -/* - * Make sure required options are set - */ +/* Make sure required options are set */ #ifndef CONFIG_SPD_EEPROM #error ("CONFIG_SPD_EEPROM is required") #endif @@ -242,6 +241,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 + /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ |