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authorPeng Fan <peng.fan@nxp.com>2016-12-11 19:24:25 +0800
committerStefano Babic <sbabic@denx.de>2016-12-16 11:38:24 +0100
commit0e81982de08fc93118c3dc49cc81def0d3801445 (patch)
treeb221f86e0280526edfdd51d34d68f7a0b41aa023 /include/sparse_defs.h
parent40913fb595d1f909acbe098b3cbb076c8a635dda (diff)
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imx: mx6: fix mmdc ch0 clk for 6SL
>From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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