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authorLokesh Vutla <lokeshvutla@ti.com>2012-05-22 00:03:24 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:23 +0200
commit43037d76316db1a53be16a4c1ed97203257fa4ee (patch)
treec549887069235d35144830a8ec0bcf9346c1d1ca /include/smiLynxEM.h
parenteb4e18e89eec8d63f064cb5ec597ba9387fe4987 (diff)
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OMAP5: ADD precalculated timings for ddr3
Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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