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authorYe.Li <B37916@freescale.com>2015-08-28 14:09:52 +0800
committerYe.Li <B37916@freescale.com>2015-09-01 11:08:57 +0800
commit25e3d0cc8713de576b4d78c4c80dea7220f40858 (patch)
tree71f1a44b2d1d2ab1cd73a580703887938d343500 /include/recovery.h
parentf432dfdaeb80ecb2a78805422baef64493f63060 (diff)
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MLK-11427 imx: mx7d: Update DDR script for mx7d sabresd board
Updated items: memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001 This is just enable when LPDDR4 is enabled . memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046 T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45) memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083 PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81 memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000 DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68 memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004 DEV_ZQINIT_X32 . Should be 16 clocks memory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109 T_FAW=(40ns*528Mhz)/2)=11 memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d tXPDLL=24ns*528Mhz=13clocks File: MX7D_EVK_DDR3_1GB_32bit.ds Test result: 3 boards pass 2 days stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
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